Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1- 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tanzawa (US2023017005) in view of Song et al (US20230066757) hereinafter Song.
As to claim 1, Tanzawa discloses a memory device comprising: memory bank circuitry comprising memory cells (Fig. 1, and memory array, 11);
sense amplifier circuitry coupled to the memory bank circuitry (Fig. 2, and module13);
buffer circuitry coupled to an output of the sense amplifier circuitry (Fig. 2, and module 17); and Tanzawa does not explicitly disclose selection circuitry configured to receive a first data signal from the sense amplifier circuitry and a second data signal from the buffer circuitry, and output a selected one of the first data signal and the second data signal.
Song teaches selection circuitry configured to receive a first data signal from the sense amplifier circuitry and a second data signal from the buffer circuitry, and output a selected one of the first data signal and the second data signal (Fig. 2 with a plurality of memory cell banks (module 110a, 110b) coupled to sense amplifier 120 . Memory cells MCA, and MCB are coupled to the output by the selection line, SE. Fig. 4 illustrates associated buffer 180 coupled to the controller to the cells via pad such as pad2 to the cell array, paras. 0074 – 0076).
One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the control circuitry of Song in the system of Tanzawa to enable a granular management of the memory arrays at the cell level, para. (0006).
As to claim 9, Tanzawa discloses a method comprising: outputting, from sense amplifier circuitry of a memory device, a first data signal based on a first command, wherein the first data signal corresponds to a first one or more memory cells of the memory device (Fig. 2 with memory array 11, coupled to sense amp. 13, coupled to output buffer 17, where command from bus decodes to enable data output, paras. 0020 – 0022); outputting, from buffer circuitry of the memory device, a second data signal, wherein the second data signal corresponds to a second command, and wherein the second data signal corresponds to a second one or more of the memory cells of the memory device (Fig. 2 where a second command decodes a second memory cell to enable a data output on bus, para. 0023);
Song teaches selection circuitry configured to receive a first data signal from the sense amplifier circuitry and a second data signal from the buffer circuitry, and output a selected one of the first data signal and the second data signal (Fig. 2 with a plurality of memory cell banks (module 110a, 110b) coupled to sense amplifier 120 . Memory cells MCA, and MCB are coupled to the output by the selection line, SE. Fig. 4 illustrates associated buffer 180 coupled to the controller to the cells via pad such as pad2 to the cell array, paras. 0074 – 0076). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the control circuitry of Song in the system of Tanzawa to enable a granular management of the memory arrays at the cell level, para. (0006).
As to claim 16, Tanzawa discloses a computing system comprising: a memory controller configured to output a first command and a second command (Fig. 1, with controller 3, para. 0018); and a memory device comprising: sense amplifier circuitry configured to output a first data signal based on the first command and a second data signal associated with the second command (Fig. 2 with sense amp. 13 coupled to a memory array to decode a plurality of memory locations para. 0021);
Song teaches buffer circuitry configured to store the second data signal based on receiving the second command (Fig. 4 illustrates associated buffer 180 coupled to the controller to the cells via pad such as pad2 to the cell array, paras. 0074 – 0076);
Further, Song teaches selection circuitry configured to receive a first data signal from the sense amplifier circuitry and a second data signal from the buffer circuitry, and output a selected one of the first data signal and the second data signal (Fig. 2 with a plurality of memory cell banks (module 110a, 110b) coupled to sense amplifier 120 . Memory cells MCA, and MCB are coupled to the output by the selection line, SE. Fig. 4 illustrates associated buffer 180 coupled to the controller to the cells via pad such as pad2 to the cell array, paras. 0074 – 0076). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the control circuitry of Song in the system of Tanzawa to enable a granular management of the memory arrays at the cell level, para. (0006).
As to claim 2, Tanzawa discloses the memory device, wherein the first data signal is associated with a first one or more of the memory cells and the second data signal is associated with a second one or more of the memory cells (Fig. 2, and paras. 0022, 0023).
As to claims 3, and 17, Tanzawa discloses the memory device, wherein the sense amplifier circuitry is configured to store data associated with a second one or more of the memory cells within the buffer circuitry (Fig. 13, where buffer circuit module 180 coupled to sense amplifier 120, and cells, 110), and para. 22).
As to claim 4, Tanzawa discloses the memory device, wherein the first data signal is associated with a first read command and the second data signal is associated with a second read command (Fig. 2, and paras. 0024, 0025 where the common buffer 15 is used detailing a read command).
As to claims 5, and 18, Tanzawa discloses the memory device, wherein the sense amplifier circuitry is configured to store data associated with a third read command within the buffer circuitry (Fig. 3, and para. 0028, where buffer 17 captures data to store).
As to claim 6, Tanzawa discloses the memory device, wherein the buffer circuitry comprises row buffer circuitries, each of the row buffer circuitries is configured to store data associated with a data signal, and wherein the buffer circuitry is configured to output a data signal from one of the row buffer circuitries based on a read command (Fig. 2, and para. 0025, where address decoder 21 manages the unique plurality use of buffer).
As to claims 7, 15, and 19, Tanzawa discloses the memory device, wherein the sense amplifier circuitry is configured to refresh one or more of the memory cells and the selection circuitry is configured to output the second data signal from the buffer circuitry during at least partially overlapping periods (Figs. 3 and 8, and paras.0133, 0134, where the control logic determines the occurrence of the activated row, and perform refresh to cells) .
As to claims 8, and 20, Song discloses the memory device, wherein the buffer circuitry is configured to store a number of bits that is less than a number of bits within a page of the memory device (Fig. 7, and para. 0118. Fig. 3 illustrates the coupling of the buffer to the cells, para. 0075). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the control circuitry of Song in the system of Tanzawa enable a granular management of the memory arrays at the cell level, para. (0006).
As to claim 10, Tanzawa discloses the method further comprising: receiving the first command (Fig. 2, and para. 0028);
and Song teaches outputting, from the selection circuitry, the first data signal based on receiving the first command (para. 0074). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the control circuitry of Song in the system of Tanzawa enable a granular management of the memory arrays at the cell level, para. (0006).
As to claim 11, Tanzawa discloses the method further comprising: receiving the second command (Fig. 2, and para. 0028 where a second command for a second memory location is issued); and Song teaches outputting, from the selection circuitry, the second data signal based on receiving the second command (para. 0074). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the control circuitry of Song in the system of Tanzawa enable a granular management of the memory arrays at the cell level, para. (0006).
As to claim 12, Tanzawa discloses the method further comprising: receiving a third command, wherein a target of the third command is a third one or more of the memory cells of the memory device (Fig. 2, and para. 0022); outputting, from the sense amplifier circuitry, a third data signal associated with the third one or more of the memory cells; storing the third data signal in the buffer circuitry (Fig. 2, and para. 0028); and Song teaches outputting, from the selection circuitry, the third data signal (para. 0074). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the control circuitry of Song in the system of Tanzawa enable a granular management of the memory arrays at the cell level, para. (0006).
As to claim 13, Song discloses the method further comprising selecting one of the second data signal and the third data signal to be output from the buffer circuitry ((Fig. 2 with a plurality of memory cell banks (module 110a, 110b) coupled to sense amplifier 120 . Memory cells MCA, and MCB are coupled to the output by the selection line, SE. Fig. 4 illustrates associated buffer 180 coupled to the controller to the cells via pad such as pad2 to the cell array, paras. 0074 – 0076). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the control circuitry of Song in the system of Tanzawa enable a granular management of the memory arrays at the cell level, para. (0006).
As to claim 14, Tanzawa discloses the method further comprising: receiving a fourth command, wherein a target of the fourth command is a fourth one or more of the memory cells of the memory device (Fig. 2, and para. 0028); and Song teaches outputting, from the sense amplifier circuitry, a fourth data signal associated with the fourth one or more of the memory cells; receiving, at the selection circuitry, the second data signal from the buffer circuitry and the fourth data signal from the sense amplifier circuitry; and outputting, from the selection circuitry, fourth data signal based on receiving the fourth command (Fig. 2 with a plurality of memory cell banks (module 110a, 110b) coupled to sense amplifier 120 . Memory cells MCA, and MCB are coupled to the output by the selection line, SE. Fig. 4 illustrates associated buffer 180 coupled to the controller to the cells via pad such as pad2 to the cell array, paras. 0074 – 0076). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the control circuitry of Song in the system of Tanzawa enable a granular management of the memory arrays at the cell level, para. (0006).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US20240086071, US20200409852, and US20190278712, among other teach the management of memory latency factors.
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/C.A.D/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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