Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Referring to claims 1 and 11, the claim 1, for example, recites, “determine an error detection result for a set of bits from the first partition based at least in part on a first comparison of a first function of the set of bits with a set of first parity bits from the second partition and a second comparison of a second function of the set of bits with a second parity bit from the first partition”. This is not clear as claimed. It is not clear how a set of first “parity bits” can be compared to a “first function” of the set of bits. Similarly, it is not clear how a comparison can be made between “a second function” and “a second parity bit”. When reviewing the specification, it appears that in both instances, the parity bit(s) are being compared to the result that the first/second function generates as opposed to the function itself as claimed. Claim 11 has the same lack of clarity recited.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over: claims 1-25 of U.S. Patent No. 11,436,082 B2; claims 1-20 of U.S. Patent No. 11,755,409 B2 claims 1-20 of U.S. Patent No. 12,141,029 B2 Although the claims at issue are not identical, they are not patentably distinct from each other because the claim limitations are encompassed within, and therefore, obvious variations over the claims of the ‘082, ‘409, and ‘029 patents. For example, representative claims are outlined below to show they are not patentably distinct from each other. The underlined portions are functionally equivalent to their respective portions in each of the patents. Claim 1 – this application1. A memory device, comprising: one or more memory arrays comprising a first partition and a second partition; and one or more controllers coupled with the one or more memory arrays and configured to cause the memory device to: determine an error detection result for a set of bits from the first partition based at least in part on a first comparison of a first function of the set of bits with a set of first parity bits from the second partition and a second comparison of a second function of the set of bits with a second parity bit from the first partition; and transmit the set of bits to a host device based at least in part on the error detection result.Claim 18 – ‘08218. An apparatus, comprising: a processor, memory in electronic communication with the processor, and instructions stored in the memory and executable by the processor to cause the apparatus to: perform a read operation at a memory array of the apparatus having a data partition and an error check partition to obtain a first set of bits from the data partition and a second set of bits from the error check partition; determine a syndrome from a comparison of a subset of the second set of bits with a result of a first function of a subset of the first set of bits; determine a first error detection result for the subset of the first set of bits based at least in part on a value of the syndrome; obtain a parity bit from the first set of bits; determine a second error detection result for the subset of the first set of bits based on a comparison of the parity bit with a second function of the subset of the first set of bits; and transmit the first set of bits to a host device based at least in part on the first error detection result and the second error detection result.Claim 1 – ‘4091. A method at a memory device, comprising: performing a read operation at a memory array to obtain a first set of bits, a second set of bits, and a parity bit; determining a first error detection result for the first set of bits based at least in part on a first function of the first set of bits and the second set of bits; determining a second error detection result for the first set of bits based on a comparison of the parity bit with a result of a second function of the first set of bits; and transmitting the first set of bits or the second set of bits to a host device based at least in part on the first error detection result and the second error detection result.Claim 18 – ‘029A memory device, comprising: one or more memory arrays comprising a first partition and a second partition; and one or more controllers coupled with the one or more memory arrays and configured to cause the memory device to: receive a read command; read a set of data bits and one or more parity bits from the first partition, and a set of error control bits associated with the set of data bits from the second partition based at least in part on receiving the read command; perform a first error control operation using the set of data bits and the set of error control bits based at least in part on reading the set of data bits and the set of error control bits; and perform a second error control operation using the one or more parity bits based at least in part on reading the one or more parity bits; wherein to perform the first error control operation the one or more controllers are further configured to cause the memory device to: determine a syndrome based at least in part on comparing the set of error control bits to a function of the set of data bits; and determine a first error control result based at least in part on a value of the syndrome; and wherein to perform the second error control operation the one or more controllers are further configured to cause the memory device to: generate one or more second parity bits based at least in part on the set of data bits or the set of error control bits, or a combination thereof; and determine a second error control result based at least in part on comparing the one or more parity bits with the one or more second parity bits.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Justin Knapp whose telephone number is (571)270-3008. The examiner can normally be reached 8:00 am - 4:30 pm (ET).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Justin R. Knapp
Primary Examiner
Art Unit 2112
/JUSTIN R KNAPP/Primary Examiner, Art Unit 2112