DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in the Republic of Korea on 1 December 2023. It is noted, however, that applicant has not filed a certified copy of the 10-2023-0172008 application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1 and 3 rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 1 includes the amended limitation “a processor”. The specification does not mention a processor. The specification is silent as to whether a processor is used. A processor is not inherent since the system could just as easily use dedicated custom logic to access the memory. Thus, the specification does not contain a written description of a processor.
Claim 1 also includes the amended limitation “identification and mapping of a memory chip of the memory chips are performed only by accessing a logical address mapped to the physical address in the mapping table”. The specification is silent as to whether the identification and mapping of a memory chip is performed only by accessing a logical address mapped to the physical address in the mapping table. This feature cannot be inherent since other elements may also need to be accessed. For example, figure 6 shows using both a mapping table and a type mapping table. Furthermore, figure 6 shows using the type mapping table for mapping memory chips to identifiers, but using the mapping table for mapping logical addresses to physical addresses. This contradicts the claim where both functions are performed by a single mapping table.
Claim 3 is rejected based on its dependence on claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2017/0249256).
In regards to claim 1, Kim teaches a system for mapping two or more different types of memories, the system comprising:
a storage comprising two or more memory chips of different memory types (“The plurality of memory devices 230_0 to 230_m may include the same kind of memory devices or different kinds of memory devices.”, paragraph 0060);
a mapping table (“The address mapping block 330 may map a logical address to a physical address according to the variable address mapping table VAR_MAP_TABLE and a fixed address mapping table FIX_MAP_TABLE.”, paragraph 0036); and
a processor configured to perform mapping of the memory chips by using the mapping table (“Each of the host devices 210_0 to 210_n may include a device, such as a central processing unit (CPU), a graphic processing unit (GPU), a video encoder/decoder, an image signal processor (ISP) and a display device. Each of the host devices 210_0 to 210_n may perform a calculation and control each of the memory devices 230_0 to 230_m to access data such as data needed for the calculation or calculation result data.”, paragraph 0020),
wherein the mapping table is configured to map the memory chips having absolute addresses to identifiers (IDs) for distinguishing the memory chips (“In the case generally designated with numeral 402 wherein the address mapping block 330 of FIG. 2 is employed according to an embodiment of the present invention, among entire bits of a logical address ADD<0:p−1>, second bits ADD<q:p−1> (q is a natural number less than p) are mapped to second bits RANK<0:a−1>, CS<0:b−1> and ROW<0:c−1> of a physical address according to the fixed address mapping table FIX_MAP_TABLE”, paragraph 0045; “The rank address may be an address to select a rank unit including at least two memory devices. The chip select address may be an address to select one memory device.”, paragraph 0043),
each of the IDs mapped to the memory chips is converted to a binary number (“In the case generally designated with numeral 402 wherein the address mapping block 330 of FIG. 2 is employed according to an embodiment of the present invention, among entire bits of a logical address ADD<0:p−1>, second bits ADD<q:p−1> (q is a natural number less than p) are mapped to second bits RANK<0:a−1>, CS<0:b−1> and ROW<0:c−1> of a physical address according to the fixed address mapping table FIX_MAP_TABLE”, paragraph 0045), and
each of the binary numbers is linked to an unused upper bit of a physical address in the mapping table so that identification and mapping of a memory chip of the memory chips are performed only by accessing a logical address mapped to the physical address in the mapping table (“In the case generally designated with numeral 402 wherein the address mapping block 330 of FIG. 2 is employed according to an embodiment of the present invention, among entire bits of a logical address ADD<0:p−1>, second bits ADD<q:p−1> (q is a natural number less than p) are mapped to second bits RANK<0:a−1>, CS<0:b−1> and ROW<0:c−1> of a physical address according to the fixed address mapping table FIX_MAP_TABLE”, paragraph 0045).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2017/0249256) in view of Confalonieri et al. (US 2018/0129424).
In regards to claim 3, Kim further teaches that the storage comprises different types of a first memory and a second memory (“The plurality of memory devices 230_0 to 230_m may include the same kind of memory devices or different kinds of memory devices.”, paragraph 0060), and
data d, e, f, g, h, and i are stored at addresses 0, 1, 2, 3, 4, and 5 of the second memory (“The host devices 210_0 to 210_n may transmit requests for storing data in the memory devices 230_0 to 230_m or reading out data stored in the memory devices 230_0 to 230_m.”, paragraph 0020), and
the first memory is loaded with data a, b, and c (“The host devices 210_0 to 210_n may transmit requests for storing data in the memory devices 230_0 to 230_m or reading out data stored in the memory devices 230_0 to 230_m.”, paragraph 0020).
Kim fails to teach that the first memory is loaded with data d, e, and f, and the data d, e, and f are duplicate data that are maintained as the latest data in the first memory. Confalonieri teaches that the first memory is loaded with data d, e, and f, and the data d, e, and f are duplicate data that are maintained as the latest data in the first memory (“a storage class residency bit of 1 and a flash residency bit of 1 indicates the subset of data is stored (e.g., LBA 442 is mapped to PBA 448 to locate the data) in both the SCM and the flash memory.”, paragraph 0061). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Kim with Confalonieri such that the first memory is loaded with data d, e, and f, and the data d, e, and f are duplicate data that are maintained as the latest data in the first memory in order to take advantage of the best properties of both types of memory.
Response to Arguments
Applicant’s arguments, see page 6-7, filed 22 January 2026, with respect to the objections and 101 rejection have been fully considered and are persuasive. The objections and 101 rejection have been withdrawn.
Applicant’s arguments with respect to the anticipation rejection have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 11 February 2026