DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10 June 2026 has been entered.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in the Republic of Korea on 1 December 2023. It is noted, however, that applicant has not filed a certified copy of the 10-2023-0172008 application as required by 37 CFR 1.55.
Response to Amendment
The amendment filed 10 June 2026 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: the changes to figure 5. Applicant cannot rely on the Korean application to provide support for the changes because Applicant has not provided a copy of the Korean application. Applicant is required to cancel the new matter or provide a certified copy of the Korean application showing support for this change in the reply to this Office Action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1, 3, and 4 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 1 includes the amended limitation “a processor”. The specification does not mention a processor. The specification is silent as to whether a processor is used. A processor is not inherent since the system could just as easily use dedicated custom logic to access the memory. Thus, the specification does not contain a written description of a processor.
Claims 3 and 4 are rejected based on their dependence on claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 4 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liu et al. (US 2024/0411690).
In regards to claim 1, Liu teaches a system for mapping two or more different types of memories, the system comprising:
a storage comprising two or more memory chips of different memory types (flash memory 302 and DRAM 304, figure 3), the storage including:
a first memory chip of a first memory type (DRAM 304, figure 3) and lacking an independent mapping table (“Consistent with the scope of the present disclosure, to enable uniform search and access of the data, a uniform, expanded L2P mapping table 612 can be maintained and stored in volatile memory device 602 to map the logical addresses of data, not only to the physical addresses 616 (e.g., PPAs) of memory regions 605 in non-volatile memory device 604, respectively, but also to the IDs 614 of memory blocks 607 in cache 606 of volatile memory device 602, respectively.”, paragraph 0086; “In some implementations, a single L2P mapping table 612 is maintained for memory system 600, and multiple L2P search engines 610 are configured to maintain the same L2P mapping table 612 and use the same L2P mapping table 612 for data search.”, paragraph 0094); and
a second memory chip of a second memory type (flash memory 302, figure 3) and including a mapping table (“Consistent with the scope of the present disclosure, to enable uniform search and access of the data, a uniform, expanded L2P mapping table 612 can be maintained and stored in volatile memory device 602 to map the logical addresses of data, not only to the physical addresses 616 (e.g., PPAs) of memory regions 605 in non-volatile memory device 604, respectively, but also to the IDs 614 of memory blocks 607 in cache 606 of volatile memory device 602, respectively.”, paragraph 0086),
wherein the mapping table includes:
a first field configured to store physical addresses corresponding to data stored in the first and second memory chips (“As described above, the L2P mapping table may be used to map a plurality of logical addresses to a plurality of physical addresses, respectively.”, paragraph 0111; “Consistent with the scope of the present disclosure, to enable uniform search and access of the data, a uniform, expanded L2P mapping table 612 can be maintained and stored in volatile memory device 602 to map the logical addresses of data, not only to the physical addresses 616 (e.g., PPAs) of memory regions 605 in non-volatile memory device 604, respectively, but also to the IDs 614 of memory blocks 607 in cache 606 of volatile memory device 602, respectively.”, paragraph 0086),
a second field configured to store identifiers (IDs) of the first and second memory chips, the IDs representing memory types of the first and second memory chips (“In the example approach of FIG. 11A, the plurality of physical addresses may be classified into either a first type of volatile memory addresses (e.g., IDs of memory blocks of a volatile memory device such as a DRAM) or a second type of non-volatile memory addresses (e.g., physical addresses of memory regions of a non-volatile memory device such as PPAs of a NAND memory device). In order to distinguish between the first type of volatile memory addresses and the second type of non-volatile memory addresses, at least one bit of an address data width can be reserved for marking the types of the physical addresses.”, paragraph 0111),
a third field configured to store logical addresses corresponding to the physical addresses and the IDs of the first and second memory chips (“As described above, the L2P mapping table may be used to map a plurality of logical addresses to a plurality of physical addresses, respectively.”, paragraph 0111),
each of the IDs is converted to a binary number (“For example, the first type of volatile memory addresses can be identified by marking the most significant bit of each address to be ‘0,’ and the second type of non-volatile memory addresses can be identified by marking the most significant bit of each address to be ‘1.’”, paragraph 0112), and
the second field occupies one or more unused upper bits of the first field in the mapping table (“The most significant bit of the 32 bits can be reserved and used to mark a type of the physical address”, paragraph 0112),
wherein a processor is configured to access the first memory chip (“Host 108 can be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Host 108 can be configured to send or receive data (a.k.a. user data or host data) to or from memory system 102.”, paragraph 0065) based on the mapping table of the second memory chip (“As shown in FIG. 7, L2P mapping table 612 may map logical addresses 702 (LBAs) of host/user data to IDs 614 of memory blocks 607 in cache 606 and physical addresses 616 of memory regions 605 in non-volatile memory device 604 through addresses 704.”, paragraph 0088), thereby reducing data retrieval cost associated with providing the first memory chip with the independent mapping table (“Consistent with the scope of the present disclosure, to enable uniform search and access of the data, a uniform, expanded L2P mapping table 612 can be maintained and stored in volatile memory device 602 to map the logical addresses of data, not only to the physical addresses 616 (e.g., PPAs) of memory regions 605 in non-volatile memory device 604, respectively, but also to the IDs 614 of memory blocks 607 in cache 606 of volatile memory device 602, respectively.”, paragraph 0086).
In regards to claim 4, Liu further teaches that the first memory chip is a direct random access memory (DRAM) (DRAM 304, figure 3), and the second memory chip is a NAND flash memory (“NAND Flash memory device 400 may be one example of flash memory 302 in FIG. 3.”, paragraph 0073).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 2024/0411690) in view of Aral et al. (US 2012/0005452).
In regards to claim 3, Liu teaches claim 1. Liu fails to teach that when data stored in the first memory chip and the second memory chip are duplicate, the duplicate data is managed as the latest data in the first memory chip. Aral teaches that when data stored in the first memory chip and the second memory chip are duplicate, the duplicate data is managed as the latest data in the first memory chip (“The physical disk map tables 216 are the data structures that maintain coherency and consistency of the data in memory with the data that is (presently or ultimately) on the disks. The disk block cache 218 is the in-memory copy of the most recently read and dirty write data to be de-staged to the disks.”, paragraph 0047) in order to “maintain coherency and consistency of the data” (id.). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Liu with Aral such that when data stored in the first memory chip and the second memory chip are duplicate, the duplicate data is managed as the latest data in the first memory chip in order to “maintain coherency and consistency of the data” (id.).
Response to Arguments
Applicant's arguments filed 10 June 2026 in regards to the drawing amendment and 112 rejection have been fully considered but they are not persuasive. Applicant has not filed a certified copy of the Korean application. Therefore, Applicant cannot rely on the Korean application to provide support for this application.
Applicant’s arguments with respect to the prior art rejections have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 29 July 2026
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