DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The abstract of the disclosure is objected to because it is in claim format. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 2, lines 7-8 of claim, the following is not clear: In the last para of claim 2, it appears that the second semiconductor is turned off twice in sequence? Please advise/correct.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 11 and 12 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sato(US 2017/0019097).
The reference to Sato, see abstract figure, where a semiconductor device is shown with 1st semiconductor element(6, Si-IGBT) and a 2nd semiconductor device is shown(7, SiC MOSFET) coupled in parallel.
A 1st SOURCE semiconductor element(3) connected to top rail supply is labeled.
A 1st SINK semiconductor element(4) connected to ground rail is labeled.
A SOURCE-SINK connection semiconductor(13, resistor) path is also labeled and connected to the 1st (Si-IGBT transistor and 2nd semiconductor SiC MOSFET transistor gates.
A control circuit (2)that controls the on/off times of the SOURCE,SINK and source-sink connection semiconductor element, as labeled, is shown.
Re claim 12: the gates of the parallel connected transistors are connected to the control circuit.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2(as best understood), 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zongian Li et al(NPL: A novel gate driver for Si/SiC hybrid switch for multi-objective optimization: 29 December 2020)
Re claims 1 and 11:
The reference to Zongian Li et al, see figures 3 and 1, below, where a semiconductor device is shown with 1st semiconductor element(Si-IGBT transistor) and a 2nd semiconductor device is shown(SiC MOSFET) coupled in parallel.
A 1st SOURCE semiconductor element connected to top rail supply is labeled.
A 1st SINK semiconductor element connected to ground rail is labeled.
A SOURCE-SINK connection semiconductor path is also labeled and connected to the 1st (Si-IGBT transistor and 2nd semiconductor SiC MOSFET transistor.
A control circuit that controls the on/off times of the SOURCE,SINK and source-sink connection semiconductor element, as labeled, is shown by the waveforms in figure 2, for the elements identified in figure 3. Note resistor elements Rg(part of the source-sink output.
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522
940
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Greyscale
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media_image2.png
499
714
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Greyscale
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media_image3.png
624
776
media_image3.png
Greyscale
The waveforms show the specific order sequence of on/off for the 1st and 2nd semiconductor elements as a function of the prior stage elements as noted in the figures.
Re claim 1, 11, 12:
The reference is not explicit in the coupling of the 1st source, sink and source-sink coupling through the gates of the parallel connected transistors in figure 1 and figure 3, however, in order for the waveforms to be developed with the sequence of on/off for the parallel connected transistors, their gates have to be connected(albeit at different times) to the 1st source semiconductor, 1st sink semiconductor and the source-sink connection semi as shown in the figure 3, ultimately, to allow for a desired pulse width as shown by the waveforms.
In light of the above it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have recognized that the NPL reference Zongian et al, shows a general circuit and the parallel semiconductors with gates have to be connected to the previous stages, via the gate terminals to be allowed to operate, turn on/off, and thus a particular duty cycle is achieved as shown by the waveforms.
Re claim 2: the waveforms reflect the on/off sequence as desired with the 1st Semiconductor element turning on first then the 2nd semic element and then the 2nd and 1st semi element turned off in sequence.
Allowable Subject Matter
Claims 3-10 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARNOLD M KINKEAD whose telephone number is (571)272-1763. The examiner can normally be reached M-F 7am-5:30pm(Fri-Flex).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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ARNOLD M. KINKEAD
Primary Examiner
Art Unit 2849
/ARNOLD M KINKEAD/Primary Examiner, Art Unit 2849
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