DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. This communication is responsive to Application No. 18/942,876 filed on November 11, 2024. Claims 1-19 are subject to examination.
Information Disclosure Statement (IDS)
3. The IDS submitted on 02/27/25 fails to comply with the provisions of 37 CFR 1.98(a)(4) because it lacks the appropriate size fee assertion and/or fails to comply with the provisions of 37 CFR 1.97(a) because it lacks the appropriate size fee set forth in 37 CFR 1.17(v). It has been placed in the application file but the information referred to therein has not been considered as to the merits.
Drawing Objections
4. The elements in Figure 6 need to have descriptive label, in conformance with 37 CFR 1.84(n) and 1.84(o). For example, a descriptive label of “Converting an input data value into one or more periods of time” should be inserted into 610 in Figure 6 to properly describe the element. Appropriate correction is required.
Claim Objections/Suggestions
5. Following claims are objected to because of the following informalities:
in claim 1, “wherein the driver to drive” (line 11) should be replaced with “wherein the driver drives”, “the decoder to calculate” (lines 14-15) should be replaced with “the decoder calculates” and “and to decode” (line 16) should be replaced with “and decodes”; similar objection applies to claim 9;
in claim 2, “claim 1, the decoder comprising” (line 1) should be replaced with “claim 1, wherein the decoder comprises”; similar objection applies to claims 3-8 and 10-14;
in claim 16, “claim 15, the method comprising” (line 1) should be replaced with “claim 15, further comprising”; and
in claim 17, “claim 15, the input data value comprising” (line 1) should be replaced with “claim 15, wherein the input data value comprises”; similar objection applies to claims 18-19.
Appropriate correction is required.
Claim Interpretations
6. The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. –An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
7. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “the device to transmit” in claim 5.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If Applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, Applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
8. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
9. Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the Applicant regards as the invention.
Claim 1 recites “a transmitter comprising…” (lines 2-3) and “a receiver comprising…” (lines 4-10). Since preceding said “receiver comprising…” a coordinator (e.g., and/or) is missing, it is not clear whether the limitation/s in claim 1 is referring to all limitations (i.e., a transmitter comprising… and a receiver comprising) or just one of them (i.e., a transmitter comprising… or a receiver comprising). Hence, renders claim 1 and its dependent claims indefinite. Similar rejection applies to claim 9.
Claim 4 recites "one or more data frames" in line 1, "a logic high voltage" in line 2, "a first fixed duration" in lines 2-3, "a logic low voltage" in line 3 and "a variable duration" in lines 3-4. It is not clear whether said above limitations are different from or the same as "one or more data frames" as recited in line 11 of claim 1, "a logic high voltage" as recited in line 12 of claim 1, "a first fixed duration" as recited in line 13 of claim 1, "a subsequent logic low voltage" as recited in line 13 of claim 1 and "a variable duration" as recited in lines 13-14 of claim 1. Hence, renders claim 4 indefinite.
Claim 5 recites limitations “the four most significant bits” (lines 5-6) and “the four least significant bits” (line 9). There is insufficient antecedent basis for these limitations in the claim. Similar rejection applies to claim 11.
Claim 9 recites a limitation “the output” (line 10). There is insufficient antecedent basis for this limitation in the claim.
Claim 15 recites "rising edges" in line 7, "rising edges" in line 9 and "rising edges" in line 10. It is not clear whether said “rising edges (line 9 and line 10) are different from or the same as "rising edges" as recited in line 7. Hence, renders claim 15 and its dependent claims indefinite.
Claim 17 recites limitations “the decimal” (line 3) and “the four most significant bits” (line 3). There is insufficient antecedent basis for these limitations in the claim.
Claim 18 recites limitations “the decimal” (line 3) and “the four least significant bits” (line 3). There is insufficient antecedent basis for these limitations in the claim.
Claim 19 recites "rising edges into a detected data value" in line 2. It is not clear whether said "rising edges" and "detected data value" are different from or the same as "rising edges into a detected data value" as recited in lines 10-11 of claim 15.
Claim Rejections - 35 USC § 103
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1,148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
I. Determining the scope and contents of the prior art.
II. Ascertaining the differences between the prior art and the claims at issue.
III. Resolving the level of ordinary skill in the pertinent art.
IV. Considering objective evidence present in the application indicating obviousness or nonobviousness.
11. Claims 1, 3-4, 8, 9-10 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Banin (US 2020/0212943 A1), in view of Kotowski (US 2009/0140774 A1) and in further view of Nagase (US 2016/0254902 A1).
Regarding claims 1 & 9, Banin teaches a device (Figure 37e) comprising: a transmitter comprising a driver (Figure 37e: “TX Driver”), the driver to receive a data input (digital pulses shown in Figure 37e at the input of the driver) and the driver coupled to a transmit actuator (Figure 37e: “Link”); a receiver comprising (Figure 38b: 3806 “RX”; see also Section 9 above): a receive actuator to receive a signal generated by the transmit actuator (Figure 38b: 3802 “link”); an amplifier circuit coupled to the receive actuator (Figure 27c-2: 2730 “RF receiver” & 2731/2735 amplifer); a filter circuit coupled to an output of the amplifier circuit (Figure 27c-2: 2738 “LPF”), wherein the driver to drive one or more data frames to the transmit actuator (digital pulses shown in Figure 37e), the one or more data frames comprising a logic high voltage for a first fixed duration (Figure 37e: 1st & 3rd digital pulses; and Figure 40e: output of element 4058 1st & 3rd digital pulses) and a subsequent logic low voltage for a variable duration of time based on the data input (Figure 37e: 2nd & 4th digital pulses). The additional limitation with regard to claim 9, Banin also teaches a microcontroller (Figure 1b: 18 “Digital Processing”) coupled to a device (Figure 1b: 18 “DTC”, “TX Driver”, “Link”, “RX Driver” & “TDC”), the microcontroller to output a data value (Figure 1b: 18 “Digital Processing”). Although Banin discloses in Figure 1b a digital processing and in Figure 30d a demodulation circuit that includes one or more comparators. Banin does no explicitly disclose a comparator coupled to an output of the filter circuit; and a decoder coupled to an output of the comparator, the decoder to calculate a detected duration of time between rising edges in a comparator output and to decode the detected duration of time into a detected data value. In a related filed of endeavor, Kotowski discloses a comparator (Figure 6: 602 “Edge Detect”); and a decoder coupled to an output of the comparator (Figure 6: 604, 606 “Counter” & “Latch”), the decoder to calculate a detected duration of time between rising edges in a comparator output (Figure 2: 202, 204; Figure 6: 602 “Edge Detect” & “D1”) and to decode the detected duration of time into a detected data value (Figure 2: 202 and 204, Figure 6: 602 “Edge Detect”, “D1”, “Length” & Paragraph 39: the data bits are stored in the length of a pulse). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to utilize Banin’s digital processing/demodulation circuit to include a decoder coupled to an output of the comparator as in Kotowski. One of ordinary skill in the art would be motivated to do so to minimize voltage offsets, Paragraph 4. Although the combination of Banin and Kotowski discloses a comparator and a filter, the combination does not explicitly disclose a comparator coupled to an output of the filter circuit. In a related field of endeavor, Nagase discloses a comparator (Figure 1: 1102 “Edge Detection Unit”) coupled to an output of the filter circuit (Figure 1: 1101 “Digital Low Pass Filter Circuit”). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to utilize combination’s filter and comparator to include a comparator coupled to an output of the filter circuit as in Nagase. One of ordinary skill in the art would be motivated to do so to improve accuracy, Paragraph 11.
Regarding claims 3 & 10, the combination of Banin, Kotowski and Nagase teaches the device as claimed in claim 1 and the system as claimed in claim 9. In addition, Banin discloses the driver to drive a start frame, the start frame comprising driving a logic high voltage to the transmit actuator for a first fixed duration (Figure 40e: output of element 4058 1st digital pulse) and driving a logic low voltage to the transmit actuator for a second fixed duration (Figure 40e: output of element 4058 2nd digital pulse).
Regarding claim 4, Banin further teaches the driver to drive one or more data frames comprising driving a logic high voltage to the transmit actuator for a first fixed duration (Figure 40e: output of element 4058 1st & 3rd digital pulses), and driving a logic low voltage to the transmit actuator for a variable duration (Figure 37e: 2nd & 4th digital pulses), the variable duration comprising an integer multiple of a period of a clock signal, the integer multiple based on the data input (Figure 37e: “DTC” & Paragraph 1947: setting the first time period of the DTC to a second value derivable from the reference clock and transmitting a data signal).
Regarding claim 8, Banin also teaches the driver comprising a pulse-width modulation (PWM) circuit (Figure 37e: “DTC” & Paragraph 1681: the first converted data signal and the second converted data signal are pulse width modulated signals comprising signal edges at times corresponding to data contained by the first DTC input data signal and the second DTC input data signal).
Regarding claim 14. the combination of Banin, Kotowski and Nagase teaches the system as claimed in claim 9. In addition, Kotowski discloses the decoder to calculate a detected duration between a first rising edge and second rising edge and to convert the detected duration to a detected data value, the detected data value based on a multiple of a period of a clock signal (Figure 6: “ck”, “D1” & “Length” & Paragraph 26: the latched counter is counter clocked at a speed of approximately ten times the data rate of the signal).
12. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Banin, in view of Kotowski, in view of Nagase and in further view of Easton (US 6,985,516 B1).
Regarding claim 2, although the combination of Banin, Kotowski and Nagase teaches the device as claimed in claim 1, the combination does not explicitly disclose the decoder comprising a microcontroller. In a related field of endeavor, Easton discloses the decoder comprising a microcontroller (Figure 10: 232 micro-controller, 1014 “Counter”, 1016c “Latch” & Column 26: Lines 56-58: micro-controller 232 includes a counter 1014 and latches). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to utilize combination’s decoder to include a microcontroller as in Easton. One of ordinary skill in the art would be motivated to do so to allow efficient processing, Column 2, Lines 12-14.
13. Claims 15-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kotowski and in view of Banin.
Regarding claim 15, Kotowski discloses a method (Figures 1-2, 4 and 6) comprising: converting an input data value into a duration of time, the duration of time based on the input data value (Figure 1: Step 104 “Determining a state of the signal, based on the period of the signal”, Figure 2: 202, 204 & Figure 4: “Input Data”); driving an actuator (Figure 4: “IC1”), the actuator to be driven at a logic high voltage for a duration (Figure 2: 2nd & 4th digital pulses), and the actuator to be driven at a logic low voltage for the duration of time based on the input data value (Figure 2: 1st, 3rd & 5th digital pulses); receiving a signal at a receiver (Figure 4: “IC2”) and detecting rising edges in the received signal (Figure 6: 602 “Edge Detect”); and calculating, at the receiver, a detected duration of time between rising edges (Figure 2: 202, 204 & Figure 6: 602 “Edge Detect”) and converting the detected duration of time between rising edges into a detected data value (Figure 2: 202 and 204, Figure 6: 602 “Edge Detect”, “Length” & Paragraph 39: the data bits are stored in the length of a pulse). Although Kotowski teaches said logic high voltage, Kotowski does not explicitly disclose a logic high voltage for a first fixed duration. In a related field of endeavor, Banin discloses a logic high voltage for a first fixed duration (Figure 40e: output of element 4058 1st & 3rd digital pulses). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to utilize Kotowski’s logic high voltage to include a fixed duration as in Banin. One of ordinary skill in the art would be motivated to do so to enhance performance, Paragraph 4.
Regarding claim 16, the combination of Kotowski and Banin teaches the method as claimed in claim 15. In addition, Banin discloses transmitting a start frame comprising driving the actuator with a logic high voltage for a first fixed duration of time (Figure 40e: output of element 4058 1st digital pulse) and driving the actuator with a logic low voltage for a second fixed duration of time (Figure 40e: output of element 4058 2nd digital pulse).
Regarding claim 19, the combination of Kotowski and Banin teaches the method as claimed in claim 15. In addition, Kotowski discloses the converting the detected duration of time between rising edges into a detected data value comprising dividing the detected duration of time between rising edges by a period of a clock signal (Figure 6: “ck”, “D1” & “Length” & Paragraph 26: the latched counter is counter clocked at a speed of approximately ten times the data rate of the signal).
Allowable Subject Matter
14. Claims 5-7, 11-13 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and upon overcoming 112 rejections as set forth in section 9.
Conclusion
15. Any inquiry concerning this communication or earlier communications from the Examiner should be directed to SHAWKAT M. ALI whose telephone number is (571) 270-1639. The Examiner can normally be reached on Monday-Thursday 8:30AM-3:30PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO AIR at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, SAM K. AHN can be reached on (571) 272-3044. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWKAT M ALI/
Primary Examiner, Art Unit 2633
Prosecution Insights