Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. This communication is responsive to the amendment filed on August 24, 2026. Claims 2 and 19 have been canceled. Claims 1, 3-18 have been amended. Claims 20-22 have been newly added. Accordingly, claims 1, 3-18 and 20-22 are currently pending.
Information Disclosure Statement (IDS)
3. The IDS submitted on 02/27/25 has been reentered and reconsidered by the Examiner.
Response to Remarks/Arguments
4. The previous objections/rejections mailed on 04/23/26 have been withdrawn due to proper claim amendments and/or persuasive arguments filed on 08/24/26. However, upon further consideration, a new ground(s) of objections/rejections is made.
Claim Objections/Suggestions
5. Following claims are objected to because of the following informalities:
in claim 5, “data, wherein” (line 2) should be replaced with “data, and wherein”;
in claim 7, “a clock” (line 3) should be replaced with “the clock”; and
in claim 11, “data, wherein” (line 2) should be replaced with “data, and wherein”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1,148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
I. Determining the scope and contents of the prior art.
II. Ascertaining the differences between the prior art and the claims at issue.
III. Resolving the level of ordinary skill in the pertinent art.
IV. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 1, 3-4, 8, 9-10, 14 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Banin (US 2020/0212943 A1 –Previously Cited), in view of Huang (US 2010/0327195 A1), in view of Kotowski (US 2009/0140774 A1 –Previously Cited) and in further view of Nagase (US 2016/0254902 A1 –Previously Cited).
Regarding claims 1, 9 & 22, Banin teaches a device (Figure 37e) comprising: a transmitter comprising a driver (Figure 37e: “TX Driver”), the driver to receive a data input (digital pulses shown in Figure 37e at the input of the driver) and the driver coupled to a transmit actuator (Figure 37e: “Link”), wherein the driver drives one or more data frames to the transmit actuator (digital pulses shown in Figure 37e), the one or more data frames comprising a logic high voltage for a first duration (Figure 37e: 1st & 3rd digital pulses) and a subsequent logic low voltage for a variable duration of time based on the data input (Figure 37e: 2nd & 4th digital pulses). The additional limitation with regard to claims 1 and 9, Banin also teaches a microcontroller (Figure 1b: 18 “Digital Processing”) coupled to a device (Figure 1b: 18 “DTC”, “TX Driver”, “Link”, “RX Driver” & “TDC”), the microcontroller to output a data value (Figure 1b: 18 “Digital Processing”). Banin further teaches the limitations of claim 22, a receiver comprising: (Figure 38b: 3806 “RX”) a receive actuator to receive a signal generated by the transmit actuator (Figure 38b: 3802 “link”); an amplifier circuit coupled to the receive actuator (Figure 27c-2: 2730 “RF receiver” & 2731/2735 amplifer); a filter circuit coupled to an output of the amplifier circuit (Figure 27c-2: 2738 “LPF”). Although Banin discloses in Figure 37e a logic high voltage for a first duration, Banin does not explicitly disclose a logic high voltage for a first fixed duration. In a related field of endeavor, Huang discloses a logic high voltage for a first fixed duration (Figure 1: 105 “VIN”, 110 “Driver” & Figure 2: “VIN” from “t1-t2” to “t3-t4”). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to utilize Banin’s high voltage to include a fixed duration as in Huang. One of ordinary skill in the art would be motivated to do so to provide efficient power consumption, Paragraph 3. Although Banin discloses in Figure 1b a digital processing and in Figure 30d a demodulation circuit that includes one or more comparators, Banin does not explicitly disclose, with regard to claim 22, a comparator coupled to an output of the filter circuit; and a decoder coupled to an output of the comparator, wherein the decoder calculates a detected duration of time between rising edges and decodes the detected duration of time into a detected data value. In a related filed of endeavor, Kotowski discloses a comparator (Figure 6: 602 “Edge Detect”); and a decoder coupled to an output of the comparator (Figure 6: 604, 606 “Counter” & “Latch”), wherein the decoder calculates a detected duration of time between rising edges (Figure 2: 202, 204; Figure 6: 602 “Edge Detect” & “D1”) and decodes the detected duration of time into a detected data value (Figure 2: 202 and 204, Figure 6: 602 “Edge Detect”, “D1”, “Length” & Paragraph 39: the data bits are stored in the length of a pulse). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to utilize the combination’s digital processing/demodulation circuit to include a decoder coupled to an output of the comparator as in Kotowski. One of ordinary skill in the art would be motivated to do so to minimize voltage offsets, Paragraph 4. Although the combination of Banin, Huang and Kotowski discloses a comparator and a filter, the combination does not explicitly disclose a comparator coupled to an output of the filter circuit as recited in claim 22. In a related field of endeavor, Nagase discloses a comparator (Figure 1: 1102 “Edge Detection Unit”) coupled to an output of the filter circuit (Figure 1: 1101 “Digital Low Pass Filter Circuit”). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to utilize combination’s filter and comparator to include a comparator coupled to an output of the filter circuit as in Nagase. One of ordinary skill in the art would be motivated to do so to improve accuracy, Paragraph 11.
Regarding claims 3 & 10, the above combination teaches the device as claimed in claim 1 and the system as claimed in claim 9. In addition, Banin discloses wherein the driver drives a start frame, the start frame comprising driving the logic high voltage to the transmit actuator for the first duration (Figure 37e: 1st & 3rd digital pulses) and driving the logic low voltage to the transmit actuator for a second duration (Figure 37e: 2nd & 4th digital pulses). However, as stated above, Banin does not explicitly disclose the logic high voltage for the first fixed duration and the logic low voltage for a fixed second duration. Huang, on one hand, discloses the logic high voltage for the first fixed duration (Figure 1: 105 “VIN”, 110 “Driver” & Figure 2: “VIN” from “t1-t2” to “t3-t4”) and Kotowski, on the other hand, discloses the logic low voltage for a fixed second duration (Figure 2: 2nd & 4th digital pulses).
Regarding claim 4, Banin further teaches wherein the driver drives one or more data frames comprising driving the logic high voltage to the transmit actuator for the first duration (Figure 37e: 1st & 3rd digital pulses), and drives the logic low voltage to the transmit actuator for the variable duration (Figure 37e: 2nd & 4th digital pulses), the variable duration comprising an integer multiple of a period of a clock signal, the integer multiple based on the data input (Figure 37e: “DTC” & Paragraph 1947: setting the first time period of the DTC to a second value derivable from the reference clock and transmitting a data signal). However, as stated above, Banin does not explicitly disclose the logic high voltage for the first fixed duration. Huang, on the other hand, discloses the logic high voltage for the first fixed duration (Figure 1: 105 “VIN”, 110 “Driver” & Figure 2: “VIN” from “t1-t2” to “t3-t4”).
Regarding claim 8, Banin also teaches wherein the driver comprises a pulse-width modulation (PWM) circuit (Figure 37e: “DTC” & Paragraph 1681: the first converted data signal and the second converted data signal are pulse width modulated signals comprising signal edges at times corresponding to data contained by the first DTC input data signal and the second DTC input data signal).
Regarding claim 14, the above combination teaches the system as claimed in claim 22. In addition, Kotowski discloses wherein the decoder calculates a detected duration between a first rising edge and second rising edge and converts the detected duration to the detected data value, the detected data value based on a multiple of a period of a clock signal (Figure 6: “ck”, “D1” & “Length” & Paragraph 26: the latched counter is counter clocked at a speed of approximately ten times the data rate of the signal).
8. Claims 15-16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kotowski, in view of Banin and in Further view of Huang.
Regarding claims 15 & 20, Kotowski discloses a method (Figures 1-2, 4 and 6) comprising: converting an input data value into a variable duration of time, the variable duration of time based on the input data value (Figure 1: Step 104 “Determining a state of the signal, based on the period of the signal”, Figure 2: 202, 204 & Figure 4: “Input Data”); driving an actuator (Figure 4: “IC1”), the actuator to be driven at a logic high voltage for a first duration (Figure 2: 1st, 3rd & 5th digital pulses), and the actuator to be driven at a logic low voltage for the duration of time based on the input data value (Figure 2: 2nd & 4th digital pulses). The additional limitation with regard to claim 20, Kotowski also teaches receiving a signal at a receiver (Figure 4: “IC2”) and detecting rising edges in the signal (Figure 6: 602 “Edge Detect”); and calculating, at the receiver, a detected duration of time between the detected rising edges (Figure 2: 202, 204 & Figure 6: 602 “Edge Detect”) and converting the detected duration of time between the detected rising edges into a detected data value (Figure 2: 202 and 204, Figure 6: 602 “Edge Detect”, “Length” & Paragraph 39: the data bits are stored in the length of a pulse). Although Kotowski teaches said logic high voltage, Kotowski does not explicitly disclose a logic low voltage for the variable duration. In a related field of endeavor, Banin discloses a logic low voltage for the variable duration (Figure 37e: 2nd & 4th digital pulses). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to utilize Kotowski’s logic low voltage to include a variable duration as in Banin. One of ordinary skill in the art would be motivated to do so to enhance performance, Paragraph 4. Although the combination of Kotowski and Banin teaches a logic high voltage, the combination does not explicitly disclose a logic high voltage for a first fixed duration. In a related field of endeavor, Huang discloses a logic high voltage for a first fixed duration (Figure 1: 105 “VIN”, 110 “Driver” & Figure 2: “VIN” from “t1-t2” to “t3-t4”). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to utilize the combination’s high voltage to include a fixed duration as in Huang. One of ordinary skill in the art would be motivated to do so to provide efficient power consumption, Paragraph 3.
Regarding claim 16, the above combination teaches the method as claimed in claim 15. In addition, Banin discloses transmitting a start frame comprising driving the actuator with the logic high voltage for the first duration of time (Figure 37e: 1st & 3rd digital pulses) and driving the actuator with the logic low voltage for a second duration (Figure 37e: 2nd & 4th digital pulses). However, as stated above, Banin does not explicitly disclose the logic high voltage for the first fixed duration and the logic low voltage for a fixed second duration. Huang, on one hand, discloses the logic high voltage for the first fixed duration (Figure 1: 105 “VIN”, 110 “Driver” & Figure 2: “VIN” from “t1-t2” to “t3-t4”) and Kotowski, on the other hand, discloses the logic low voltage for a fixed second duration (Figure 2: 2nd & 4th digital pulses).
Allowable Subject Matter
9. Claims 5-7, 11-13, 17-18 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and upon overcoming 112 rejections as set forth in section 9.
Conclusion
10. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office Action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this Final Action is set to expire THREE MONTHS from the mailing date of this Action. In the event a first reply is filed within TWO MONTHS of the mailing date of this Final Action and the Advisory Action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the Advisory Action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the Advisory Action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this Final Action.
11. Any inquiry concerning this communication or earlier communications from the Examiner should be directed to SHAWKAT M. ALI whose telephone number is (571) 270-1639. The Examiner can normally be reached on Monday-Thursday 8:30AM-3:30PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO AIR at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, SAM K. AHN can be reached on (571) 272-3044. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWKAT M ALI/
Primary Examiner, Art Unit 2633
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