DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figures 9 and 10 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 5, 9, 12, 14, 15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. (US Pat. App. Pub. No. 2015/0014040) in view of JP2006-100708.
With respect to claim 1, Ahn teaches a three-terminal multilayer ceramic capacitor (see abstract) comprising: a multilayer body including a plurality of laminated dielectric layers and including a first main surface and a second main surface that face each other in a height direction (see paragraph [0031]), a first end surface and a second end surface that face each other in a length direction orthogonal or substantially orthogonal to the height direction, and a first side surface and a second side surface that face each other in a width direction orthogonal or substantially orthogonal to the height direction and the length direction (see FIG. 1 and paragraph [0032]); a plurality of first inner electrode layers on the plurality of dielectric layers and extending to the first end surface and the second end surface as well as the first main surface and the second main surface (see FIG. 2 and paragraph [0042]); a plurality of second inner electrode layers on the plurality of dielectric layers and extending to the first main surface and the second main surface (se FIG. 2 and paragraph [0042]); a first outer electrode on the first end surface, extending from the first end surface to a portion of the first main surface and a portion of the second main surface and on a portion of the first side surface and a portion of the second side surface, and being connected to the first inner electrode layers (see FIG. 1, element 131); a second outer electrode on the second end surface, extending from the second end surface to a portion of the first main surface and a portion of the second main surface and on a portion of the first side surface and a portion of the second side surface, and being connected to the first inner electrode layers (see FIG. 1, element 132); a third outer electrode on the first side surface, extending from the first side surface to a portion of the first main surface and a portion of the second main surface, and being connected to the second inner electrode layers (see FIG. 1, element 133); and a fourth outer electrode on the second side surface, extending from the second side surface to a portion of the first main surface and a portion of the second main surface, and being connected to the second inner electrode layers (see FIG. 1, element 134); wherein the first inner electrode layers each include: a first counter electrode portion facing the second inner electrode layers with the plurality of dielectric layers interposed therebetween (see FIG. 3A, element 121); a first extended electrode portion extending from the first counter electrode portion and to the first end surface and connected to the first outer electrode (see FIG. 3A, element 123b); a second extended electrode portion extending from the first counter electrode portion or the first extended electrode portion to the first main surface at a position spaced away from the first end surface on a first end surface side and connected to the first outer electrode (see FIG. 3A, element 123a); a third extended electrode portion extending from the first counter electrode portion or the first extended electrode portion to the second main surface at a position spaced away from the first end surface on the first end surface side and connected to the first outer electrode (see FIG. 3A, element 123a extending to the other surface); a fourth extended electrode portion extending from the first counter electrode portion to the second end surface and connected to the second outer electrode (see FIG. 3A, element 124b); a fifth extended electrode portion extending from the first counter electrode portion or the fourth extended electrode portion to the first main surface at a position spaced away from the second end surface on a second end surface side and connected to the second outer electrode (see FIG. 3A, element 124a); and a sixth extended electrode portion extending from the first counter electrode portion or the fourth extended electrode portion to the second main surface at a position spaced away from the second end surface on the second end surface side and connected to the second outer electrode (see FIG. 3A, element 124a, extending to the other surface).
Ahn fails to teach that the extended electrode portions extend to the first and second side surfaces; rather, Ahn teaches that he extended electrode portions extend to the first and second main surfaces.
JP ‘708, on the other hand, teaches that the extended electrode portions extend to the first and second side surfaces. See FIGS. 7A-7D, elements 54A-D. Such an arrangement results in the reduction of self-heating while maintaining a low ESL. See paragraph [0015].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify Ahn, as taught by JP ‘708, in order to reduce the self-heating of the capacitor while maintaining a low ESL.
With respect to claim 2, the combined teachings of Ahn and JP ‘708 teach that the second inner electrode layers each include: a second counter electrode portion facing the first counter electrode portion with the plurality of dielectric layers interposed therebetween; a seventh extended electrode portion extending from the second counter electrode portion to the first side surface; and an eighth extended electrode portion extending from the second counter electrode portion to the second side surface. See Ahn, FIG. 3B, elements 122, 125, 126 in view of JP ‘708, FIGS. 7A-7D.
With respect to claim 5, the combined teachings of Ahn and JP ‘708 teach that each of the plurality of dielectric layers includes BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component. See Ahn, paragraph [0035].
With respect to claim 9, the combined teachings of Ahn and JP ‘708 teach that a dimension of the second, third, fifth, and sixth extended electrode portions in the length direction are the same or substantially the same. See Ahn, FIG. 4, element A.
With respect to claim 12, the combined teachings of Ahn and JP ‘708 teach that each of the plurality of first and second inner electrode layers includes Ni, Cu, Ag, Pd, or Au, or an alloy including at least one of Ni, Cu, Ag, Pd, or Au. See Ahn, paragraph [0041].
With respect to claim 14, the combined teachings of Ahn and JP ‘708 teach that each of the first, second, third, and fourth outer electrodes includes an underlying electrode layer and a plating layer on a surface of the underlying electrode layer. See Ahn, paragraphs [0050]-[0051].
With respect to claim 15, the combined teachings of Ahn and JP ‘708 teach that the underlying electrode layer includes a baked layer including a glass component and a metal component. See Ahn, paragraph [0050].
With respect to claim 17, the combined teachings of Ahn and JP ‘708 teach that the metal component includes at least one of Cu, Ni, Ag, Pd, Ag-Pd alloy, or Au. See Ahn, paragraph [0050].
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. (US Pat. App. Pub. No. 2015/0014040) in view of JP2006-100708, and further, in view of Lee et al. (US Pat. App. Pub. No. 2015/0053471).
With respect to claim 3, the combined teachings of Ahn and JP ‘708 fail to explicitly teach that a dimension in the length direction from the first end surface to a side of the second extended electrode portion on the first end surface side and from the first end surface to a side of the third extended electrode portion on the first end surface side is more than or equal to about 25% and less than or equal to about 80% of a dimension in the length direction of a portion of the first outer electrode on a portion of the first main surface and a portion of the second main surface, and on a portion of the first side surface and a portion of the second side surface; and a dimension in the length direction from the second end surface to a side of the fifth extended electrode portion on the second end surface side and from the second end surface to a side of the sixth extended electrode portion on the second end surface side is more than or equal to about 25% and less than or equal to about 80% of a dimension in the length direction of a portion of the second outer electrode on a portion of the first main surface and a portion of the second main surface, and on a portion of the first side surface and a portion of the second side surface.
However, Lee teaches that the dimensions of the extended electrode portions are a result-oriented variable, which prevents delamination and improves reliability. See FIG. 3, dimensions BW, M, and G, and paragraph [0078]. See also, MPEP 2144.05(II)(A) and (B), citing In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) and In re Stepan, 868, F.3d 1342, 1346, 123 USPQ2d 1838, 1841 (Fed. Cir. 2017).
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify the combined teachings of Ahn and JP ‘708, as taught by Lee, in order to prevent delamination and improve reliability.
With respect to claim 4, the combined teachings of Ahn and JP ‘708 fail to explicitly teach a dimension in the length direction of the second extended electrode portion and the third extended electrode portion is more than or equal to about 20% and less than or equal to about 75% of a dimension in the length direction of a portion of the first outer electrode on a portion of the first main surface and a portion of the second main surface, and on a portion of the first side surface and a portion of the second side surface; and a dimension in the length direction of the fifth extended electrode portion and the sixth extended electrode portion is more than or equal to about 20% and less than or equal to about 75% of a dimension in the length direction of a portion of the second outer electrode on a portion of the first main surface and a portion of the second main surface, and on the first side surface and a portion of the second side surface.
However, Lee teaches that the dimensions of the extended electrode portions are a result-oriented variable, which prevents delamination and improves reliability. See FIG. 3, dimensions BW, M, and G, and paragraph [0078]. See also, MPEP 2144.05(II)(A) and (B), citing In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) and In re Stepan, 868, F.3d 1342, 1346, 123 USPQ2d 1838, 1841 (Fed. Cir. 2017).
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify the combined teachings of Ahn and JP ‘708, as taught by Lee, in order to prevent delamination and improve reliability.
Claims 6-8, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. (US Pat. App. Pub. No. 2015/0014040) in view of JP2006-100708, and further, in view of Nishimura (US Pat. App. Pub. No. 2021/0233713).
With respect to claim 6, the combined teachings of Ahn and JP ‘708 fail to teach that each of the plurality of dielectric layers includes a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound as a subcomponent.
Nishimura, on the other hand, teach that each of the plurality of dielectric layers includes a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound as a subcomponent. See paragraph [0031]. Such a modification is known for adjusting the characteristics of the dielectric layers.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify the combined teachings of Ahn and JP ‘708, as taught by Nishimura, in order to adjust the characteristics of the dielectric layers.
With respect to claim 7, the combined teachings of Ahn and JP ‘708 fail to teach that a thickness of each of the plurality of dielectric layers is about 0.5 μm and smaller than or equal to about 10.0 μm.
Nishimura, on the other hand, teaches that a thickness of each of the plurality of dielectric layers is about 0.5 μm and smaller than or equal to about 10.0 μm. See paragraph [0030]. Such an arrangement helps maintain the dimensions and miniaturization of the capacitor body.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify the combined teachings of Ahn and JP ‘708, as taught by Nishimura, in order to maintain the dimensions and miniaturization of the capacitor body.
With respect to claim 8, the combined teachings of Ahn and JP ‘708 fail to teach that a number of the plurality of dielectric layers is larger than or equal to 15 and smaller than or equal to 600.
Nishimura, on the other hand, teaches that a number of the plurality of dielectric layers is larger than or equal to 15 and smaller than or equal to 600. See paragraph [0030]. Such an arrangement helps maintain the dimensions and miniaturization of the capacitor body.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify the combined teachings of Ahn and JP ‘708, as taught by Nishimura, in order to maintain the dimensions and miniaturization of the capacitor body.
With respect to claim 11, the combined teachings of Ahn and JP ‘708 fails to teach that a total number of the plurality of first and second inner electrode layers is 15 to 500.
Nishimura, on the other hand, teaches that a total number of the plurality of first and second inner electrode layers is 15 to 500. See paragraph [0050]. Such an arrangement helps maintain the dimensions, capacitance, and miniaturization of the capacitor body.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify the combined teachings of Ahn and JP ‘708, as taught by Nishimura, in order to maintain the dimensions, capacitance, and miniaturization of the capacitor body.
With respect to claim 13, the combined teachings of Ahn and JP ‘708 teaches that a thickness of each of the plurality of first and second inner electrode layers is about 0.5 μm to about 1.0 μm.
Nishimura, on the other hand, teaches that a thickness of each of the plurality of first and second inner electrode layers is about 0.5 μm to about 1.0 μm. See paragraph [0050]. Such an arrangement helps maintain the dimensions, capacitance, and miniaturization of the capacitor body.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify the combined teachings of Ahn and JP ‘708, as taught by Nishimura, in order to maintain the dimensions, capacitance, and miniaturization of the capacitor body.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. (US Pat. App. Pub. No. 2015/0014040) in view of JP2006-100708, and further, in view of Fujii et al. (US Pat. App. Pub. No. 2018/0108480).
With respect to claim 10, the combined teachings of Ahn and JP ‘708 fail to explicitly teach that a dimension of the seventh and eighth extended electrode portions is about 100 μm to about 400 μm.
Fujii, on the other hand, teaches that a dimension of the seventh and eighth extended electrode portions is about 100 μm to about 400 μm. See Table 1, Examples 1-10, dimension “a”. Such an arrangement results in a reduced ESL. See paragraph [0007].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify the combined teachings of Ahn and JP ‘708, as taught by Fujii, in order to reduce the ESL of the capacitor.
Claims 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. (US Pat. App. Pub. No. 2015/0014040) in view of JP2006-100708, and further, in view of Kanzaki et al. (US Pat. App. Pub. No. 2021/0327648).
With respect to claim 16, the combined teachings of Ahn and JP ‘708 fails to teach that the glass component includes at least one of B, Si, Ba, Mg, Al, or Li.
Kanzaki, on the other hand, teaches that the glass component includes at least one of B, Si, Ba, Mg, Al, or Li. See paragraph [0074]. Such an arrangement is known for connecting internal electrodes to an external circuit.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify the combined teachings of Ahn and JP ‘708, as taught by Kanzaki, in order to connect the internal electrodes to an external circuit.
With respect to claim 18, the combined teachings of Ahn and JP ‘708 fail to teach that a thickness of the underlying electrode layer is about 3 μm to about 20 μm.
Kanzaki, on the other hand, teaches that a thickness of the underlying electrode layer is about 3 μm to about 20 μm. See paragraph [0073]. Such an arrangement results helps maintain the miniaturization of the capacitor.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify the combined teachings of Ahn and JP ‘708, as taught by Kanzaki, in order to maintain the miniaturization of the capacitor.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Shimada (US 10,361,032), Mukobata et al. (US 10,172,247), and Mukobata et al. (US 9,947,472) each disclose three-terminal capacitors, but fail to disclose the requirements of claim 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DION R FERGUSON whose telephone number is (571)270-7566. The examiner can normally be reached Monday-Friday, 5:30 a.m. - 4:00 p.m..
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/DION R. FERGUSON/Primary Examiner, Art Unit 2847
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