Office Action Predictor
Last updated: April 16, 2026
Application No. 18/943,119

CIRCUIT AND METHOD FOR TASK MONITORING

Non-Final OA §103
Filed
Nov 11, 2024
Examiner
PATEL, KAMINI B
Art Unit
2114
Tech Center
2100 — Computer Architecture & Software
Assignee
Stmicroelectronics International N.V.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
96%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
892 granted / 1041 resolved
+30.7% vs TC avg
Moderate +10% lift
Without
With
+9.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
15 currently pending
Career history
1056
Total Applications
across all art units

Statute-Specific Performance

§101
13.1%
-26.9% vs TC avg
§103
44.6%
+4.6% vs TC avg
§102
21.6%
-18.4% vs TC avg
§112
9.6%
-30.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1041 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This action is in response to the application filed on 11/11/2024, in which claims 1-21 are presented for the examination. Information Disclosure Statement The Information Disclosure Statement (IDS) submitted on 11/11/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS statement is being considered by the examiner. Drawings The drawings filed on 11/11/2024 are accepted by the examiner. Allowable Subject Matter Claims 4-18, 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-3, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ichard (US 2011/0239196) in view of Borlick et al. (US 9,753,773, referred herein after Borlick). As per claim 1, 19, Ichard discloses a monitoring circuit for performing logical and temporal task monitoring of a plurality of tasks executed in a processing system, the monitoring circuit comprising: a task recording circuit; and (Fig. 1, event trace module 112 records the occurrence of each event, [0035]); a task management circuit (Fig. 2, 110, [0028], generates trace events) communicatively coupled to the task recording circuit and configured to receive as input a plurality of task signals (Fig. 1, signal 117, [0038], [0035], These signals may indicate various operations being performed within the node, such as: start load, stop load, start compute, stop compute, start store, stop store, start next node, etc.), each task signal indicating an execution state of a respective task (Fig. 3, [0055], execution state of event are shown), wherein the task management circuit comprises a managing circuit configured to: operate in at least three modes depending on a respective event corresponding to either a detection of a rising edge (Fig. 3, rising edge) or a falling edge of a given task signal in the plurality of task signals being monitored (Fig. 3, falling edge), or an occurrence of a trigger signal (Fig. 3, [0055], Trigger logic 113 of FIG. 1 is coupled to various signals and busses that may be used to trigger the start and end of event tracing); and Ichard does not specifically disclose in each mode, check whether at least a variable representing an operation state of the task contains an expected value corresponding to an occurrence of the respective event enabling the respective mode, and output a result of the check in an error signal for the respective task being monitored; However, Borlick discloses in each mode (Fig. 3, mode selection logic), check whether at least a variable representing an operation state of the task contains an expected value (Threshold, Col. 1, lines 60-67, Col. 2, lines 1-10) corresponding to an occurrence of the respective event enabling the respective mode (Col. 12, lines 32-46, Col. 14, line 30-56), and output a result of the check in an error signal for the respective task being monitored (Col. 9, lines 6-19, output is signaled); Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Borlick’s performance based multi-mode task dispatching method into Ichard’s Task event monitoring system because one of the ordinary skill in the art would have been motivated to allow precise, event-driven actions (like counting, toggling, or triggering one-shot tasks) in digital systems (PLCs, microcontrollers) by reacting only at the signal's state transition (0-to-1 or 1-to-0), preventing false triggers from sustained high/low levels, ensuring accurate timing, and enabling efficient power management by only acting when needed, improving control and responsiveness. As per claim 2, 20, Ichard discloses the monitoring circuit according to claim 1, wherein the managing circuit is configured to check a first variable indicating whether the task is active or not active before of the occurrence of the respective event ([0031], [0035], nodes are activated and control signals are monitored). As per claim 3, Ichard discloses the monitoring circuit according to claim 2, wherein the managing circuit is further configured to check a second variable indicating the mode before of the occurrence of the respective event ([0052], internal register, (status register) stores a bit to determine the status). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form 892. Chou teaches the first programmable device is configured to detect event activities associated with the first subset and to store the event activities as stored first event data. The BMC includes a system event log. The BMC is communicatively coupled to the first programmable device. The BMC is configured to receive the stored first event data and to write the stored first event data in the system event log. Lobuono teaches the sequence of event recorder detects, records and time stamps changes in the input signal to create a database that can be analyzed to determine whether a sequence of event recorder is properly synchronized and functioning. The system performance and component useful life are enhanced cost effectively and reliably. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAMINI B PATEL whose telephone number is (571)270-3902. The examiner can normally be reached on M-F 8-4:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached on 571-272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KAMINI B PATEL/Primary Examiner, Art Unit 2114
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Prosecution Timeline

Nov 11, 2024
Application Filed
Dec 18, 2025
Non-Final Rejection — §103
Mar 31, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
96%
With Interview (+9.9%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 1041 resolved cases by this examiner. Grant probability derived from career allow rate.

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