DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is response to communication: response to preliminary amendment filed on 11/11/2024.
Claims 1-19 are currently pending in this application.
The IDS filed on 11/11/2024 has been accepted.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-16, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Aneja et al. US Patent Application Publication 2024/0134730 (Aneja), in view of Ellis et al. US Patent Application Publication 2022/0382850 (Ellis).
As per claim 1, Aneja teaches a power management integrated circuit PMIC configured to be coupled to a system on chip SoC the SoC comprising at least one of a plurality of SoC power domains and a plurality of SoC clock domains (abstract and throughout with SoC and a PMIC; see paragraph 31 with multiple domains including at least a main domain and safety domain; see paragraph 37 wherein each domain may have a separate clock); the PMIC is configured to: generate a challenge; output the challenge to the SoC; generate an expected-challenge-response determined from the challenge; receive a challenge-response form the SoC (paragraph 51, 63, 75, and throughout with challenge response from PMIC to SoC;) and depending on an operating state in response to the challenge-response being different to the expected-challenge response: i) apply a reset to the SoC, or ii) supply power to a subset of the plurality of SoC power domains and/or iii) enable clocks of a subset of the plurality of SoC clock domains (paragraph 58 multiple responses; see paragraph 74 and 84 with reboot).
Although Aneja teaches utilizing challenge/responses from the PMIC to the SOC, Aneja does not explicitly teach challenge/responses utilizing shared keys. However, this is notoriously well known in the art. For example, see Ellis (paragraph 68 and throughout with generating challenge, outputting challenge; generating a response using shared key; receiving the response; comparing the response and expected response).
At the time the invention was filed, it would have been obvious to one of ordinary skill in the art to combine the teachings of Aneja with Ellis. One of ordinary skills in the art would have been motivated to perform such an addition to provide authentication of security devices (paragraph 7 of Ellis).
As per claim 2, the Aneja combination teaches wherein the subset of the plurality SoC power domains and the subset of the plurality of SoC clock domains comprise at least one of a safety critical domain and a security domain (throughout Aneja; see paragraph 5 and 32 with safety domain and main domain).
As per claim 3, the Aneja combination teaches wherein the plurality of SoC power domains comprises a safety-critical power domain, the operating state is a safe operating state, and in response to the challenge-response being different to the expected challenge-response, the PMIC is further configured to supply power to the safety-critical power domain (Aneja paragraph 64 with main and safety domain; if error, main domain may be shut down while safety domain operates; see also paragraph 66)
As per claim 4, it would have been obvious over the Aneja combination wherein the plurality of SoC power domains comprises a security power domain, the operating state is a safe operating state, and in response to the challenge response being different to the expected-challenge-response, the PMIC is further configured to remove power from the security power domain (Aneja paragraph 64 and 66 with shutting down power from domain in response to error).
As per claim 5, it would have been obvious over the Aneja combination wherein the Soc comprises further circuitry, the operating state is a safe operating sate, and in response to the challenge-response being different to the expected challenge-response, the PMIC is further configured to control the SoC to apply a reset to the further circuitry (Aneja paragraph 74 with rebooting SoC and other PMICs).
As per claim 7, the Aneja combination teaches further comprising a bidirectional security operating state terminal configured to be coupled to the SoC and configured t at least one of: receive a secure operating state value from the SoC; output a secure operating mode status in response to the challenge-response being the same as expected-challenge-response; and output a non-secure operating mode status in response to the challenge-response being different to the expected-challenge-response (Aneja paragraph 6 and throughout with making comparison and if error found, indicate error; see paragraph 51 and throughout with challenge-response)
As per claim 8, it would have been obvious over the Aneja combination further configured after a predetermined time to: generate a further challenge; output the further challenge to the SoC; generate a further expected-challenge-resposne determined from the challenge and the shared key; receive a further challenge-response from the SoC; determine whether the further challenge-response is valid by comparing the further challenge response and the further expected-challenge-response; and depending on an operating state and in response to the further challenge-response being different to the further expected-challenge-response: i) apply a rest to the SoC, or ii) supply power to a subset of the plurality of SoC power domains and/or iii) enable the clocks of a subset of the plurality of SoC clock domains (obvious to one of ordinary skill in the art to repeat steps after a certain time and to make the system work continuously; see rejection of claim 1; further, see Aneja paragraph 74 wherein after a first test, system may be rebooted and tested again; obvious to one of ordinary skill in the art to perform the function again some time after the reboot).
As per claim 9, it would have been obvious over the Aneja combination further comprising a plurality of voltage regulators, each voltage regulator being configured to be coupled to a respective power domain of the plurality of SoC power domains (obvious to one of ordinary skill in the art to utilize voltage regulators; see Aneja paragraph 30, 36, 37).
As per claim 10, it would have been obvious over the Aneja combination further comprising a plurality of clock generators, each clock generator being configured to be coupled to a respective clock domain of the plurality of SoC clock domains (obvious to one of ordinary skill in the art; see Aneja paragraph 37 with clocks and wherein each domain may have a separate clock and power supply to facilitate independent operability).
Claim 11 is rejected using the same basis of arguments used to reject claim 1 above.
Claim 12 is rejected using the same basis of arguments used to reject claim 1 above.
Claim 13 is rejected using the same basis of arguments used to reject claim 1 above.
Claim 14 is rejected using the same basis of arguments used to reject claim 3 above.
Claim 15 is rejected using the same basis of arguments used to reject claim 4 above.
Claim 16 is rejected using the same basis of arguments used to reject claim 5 above.
Claim 18 is rejected using the same basis of arguments used to reject claim 7 above.
Claim 19 is rejected using the same basis of arguments used to reject claim 8 above.
Claim(s) 6 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over the Aneja combination as applied above, and further in view of Heo et al. US Patent Application Publication 2016/0066280 (Heo).
As per claim 6, although the Aneja combination teaches utilizing voltage regulators for domains (see paragraphs 36-37), the combination does not explicitly teach wherein the at least one of the plurality of SoC power domains comprises a SoC power domain sense output and the PMIC further comprises: a voltage monitor configured to be coupled to the SoC power domain sense output and configured to compare the SoC power domain sense output voltage with a PMIC voltage output of a PMIC and to indicate whether the operating state is at least oen of a safe operating state and secure operating state based on the comparison. However, comparing voltages and determining safe/secure operating states based on comparisons is well known in the art. For example, see Heo (abstract, paragraph 37, 58, claim 37, and throughout, wherein comparing a power supply voltage with a reference power supply and generates alarm if value is not expected).
At the time the invention was filed, it would have been obvious to one of ordinary skill in the art to combine the teachigns of the Aneja combination with Heo. One of ordinary skill in the art would have been motivated to perform such an addition to increase system security by improving system stability (paragraphs 4-5).
Claim 17 is rejected using the same basis of arguments used to reject claim 6 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON KAI YIN GEE whose telephone number is (571)272-6431. The examiner can normally be reached on Monday-Friday 8:30-5:00 PST Pacific.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Farid Homayounmehr can be reached on (571) 272-3739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/JASON K GEE/Primary Examiner, Art Unit 2495
Prosecution Insights