DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Response to Arguments
Applicant’s arguments with respect to claim(s) 19-36 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 19, 21, 22, 24, 28, 30, 31, 33 rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over CA 2974561 A1 Sato, and further in view of US 20120189052 A1 Karczewicz; Marta et al. (hereafter Karczewicz).
Regarding claim 19, Sato discloses A device comprising (Fig.1): a buffer; a memory configurable to store (Fig.1): a delta quantization parameter for a first block in a picture (Fig.1, [63], [124], differences of quantization parameters as one of quantization parameters for MBs are coded and provided to accumulation buffer); a skip flag for the first block ([224], a flag indicating whether or not the qp_delta presence is the skip flag, also is a quantization parameter coded/compressed that would be provided to accumulation buffer); and a chroma quantization parameter for the first bloc ([82], [99]-[100], QP for chroma included in compressed information is stored in accumulation buffer); and processing circuitry coupled to the memory and the buffer and configurable to (Fig.1): store the delta quantization parameter to the buffer (Fig.10, delta QP as one of QPs enters into quantization parameter buffer); store the skip flag to the buffer (Fig.10, skip flag as one of QPs enters into quantization parameter buffer ); and encode a second block in the picture using the delta quantization parameter and the skip flag and without using the chroma quantization parameter (Fig.1, [222],[263]-[269], a quantization parameter including submb_qp_delta and submb_qp_present_flag obtained from a previously coded MB are used for deriving current quantization parameter in a encoding process).
Sato fails to disclose wherein the skip flag indicates that the first block includes at least one non-zero coefficient;
However, Karczewicz teaches the skip flag indicates that the first block includes at least one non-zero coefficient ([81], coded block flag is the skip flag).
Therefore it would have been obvious to one of ordinary skill in the art at the time the claimed invention was made to modify the device disclosed by Sato to include the teaching in the same field of endeavor of Karczewicz, in order to provide video coding techniques consistent with the emerging high efficiency video coding (HEVC) standard, as taught by Karczewicz.
Regarding claims 21, 30, Sato discloses The device of claim 19, The device of wherein the first block is a left adjacent block of the second block, or wherein the first block is a top adjacent block of the second block ([268]-[275]).
Regarding claims 22, 31, Sato discloses The device of claim 19, The device of wherein the memory is configurable to store a total number of nonzero coefficients for the first block, and wherein the processing circuitry is configurable to: store the total number of nonzero coefficients to the buffer; and encode the second block using the total number of nonzero coefficients ([380]-[382]).
Regarding claims 24, 33, Sato discloses The device of claim 19, wherein the buffer is separate from the memory (Figs.1, 10).
Regarding claim 28, see the rejection for claim 19.
Claims 20, 23, 25, 29, 32, 34 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Sato, in view of Karczewicz, and further in view of CN 101653000 A PANDIT, PURVIN BIBHAS et al. (hereafter Pandit)
Regarding claims 20, 29, Pandit teaches The device of claim 19, The device of wherein the memory is configurable to store: an intra-prediction mode flag for the first block; and a reference index for the first block, and wherein the processing circuitry is configurable to: store the intra-prediction mode flag to the buffer; store the reference index to the buffer; and encode the second block using the intra-prediction mode flag and the reference index (P.8 para.2nd).
Therefore it would have been obvious to one of ordinary skill in the art at the time the claimed invention was made having all the references Sato, Karczewicz and Lavoie before him/her, to modify the device disclosed by Sato to include the teaching in the same field of endeavor of Karczewicz and Pandit, in order to provide video coding techniques consistent with the emerging high efficiency video coding (HEVC) standard, as taught by Karczewicz, and method and device to achieve efficient memory resource usage, as taught by Pandit.
Regarding claims 23, 32, Pandit teaches The device of claim 19, The device of wherein the memory is configurable to store an intra-prediction mode parameter for the first block, and wherein the processing circuitry is configurable to encode the second block without using the intra-prediction mode parameter (P.12 para,2nd).
Regarding claims 25, 34, Pandit teaches The device of claim 19, The device of wherein the memory is configurable to store a reference picture index for the first block, and wherein the processing circuitry is configurable to: store the reference picture index to the buffer; and encode the second block using the reference picture index (P.9 para.3rd, P.10 para.4th).
Claims 26, 35 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Sato, in view of Karczewicz, and further in view of US 20050265455 A1 Kawaharada.
Regarding claims 26, 35, Kawaharada teaches The device of The device of claim 19, wherein the memory is configurable to store a motion vector difference for the first block, and wherein the processing circuitry is configurable to: store the motion vector difference to the buffer; and encode the second block using the motion vector difference ([21]).
Therefore it would have been obvious to one of ordinary skill in the art at the time the claimed invention was made having all the references Sato, Karczewicz and Kawaharada before him/her, to modify the device disclosed by Sato to include the teaching in the same field of endeavor of Karczewicz and Kawaharada, in order to provide video coding techniques consistent with the emerging high efficiency video coding (HEVC) standard, as taught by Karczewicz, and MV encoding method capable of reducing an MV code length by way of utilizing past MV information, as taught by Kawaharada.
Claims 27, 36 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Sato, in view of Karczewicz, and further in view of US 20080285875 A1 EBIHARA; Masakazu et al. (hereafter EBIHARA).
Regarding claims 27, 36, EBIHARA teaches The device of claim 19, The device of wherein the memory is configurable to store a coded block pattern flag for the first block, and wherein the processing circuitry is configurable to: store the coded block pattern flag to the buffer; and encode the second block using the coded block pattern flag ([24], [64], [67]).
Therefore it would have been obvious to one of ordinary skill in the art at the time the claimed invention was made having all the references Sato, Karczewicz and EBIHARA before him/her, to modify the device disclosed by Sato to include the teaching in the same field of endeavor of Karczewicz and EBIHARA, in order to provide video coding techniques consistent with the emerging high efficiency video coding (HEVC) standard, as taught by Karczewicz, and realize highly efficient parallel processing in a plurality of processors, as taught by EBIHARA.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY Y. LI whose telephone number is (571)270-3671. The examiner can normally be reached Monday Friday (8:30 AM- 4:30 PM) EST.
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/TRACY Y. LI/Primary Examiner, Art Unit 2487
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