DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Examiner Remarks
English translation of prior reference for the rejection is attached to this Office Action.
Election/Restrictions
Applicant’s election without traverse of Group II in the reply filed on 03/18/2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(e) the invention was described in (1) an application for patent, published under section 122(b), by another filed in the United States before the invention by the applicant for patent or (2) a patent granted on an application for patent by another filed in the United States before the invention by the applicant for patent, except that an international application filed under the treaty defined in section 351(a) shall have the effects for purposes of this subsection of an application filed in the United States only if the international application designated the United States and was published under Article 21(2) of such treaty in the English language.
Claim(s) 19, 21, 22, 24, 28, 30, 31, 33 is/are rejected under pre-AIA 35 U.S.C. 102(e) as being anticipated by CA 2974561 A1 Sato.
Regarding claim 19, Sato disclose A device comprising (Fig.1): a buffer; a memory configurable to store (Fig.1): a delta quantization parameter for a first block in a picture (Fig.1, [63], [124], differences of quantization parameters as one of quantization parameters for MBs are coded and provided to accumulation buffer); a skip flag for the first block ([224], a flag indicating whether or not the qp_delta presence is the skip flag, also is a quantization parameter and coded/compressed that would be provided to accumulation buffer); and a chroma quantization parameter for the first bloc ([82], [99]-[100], QP for chroma included in compressed information is stored in accumulation buffer); and processing circuitry coupled to the memory and the buffer and configurable to (Fig.1): store the delta quantization parameter to the buffer (Fig.10, delta QP as one of QPs enters into quantization parameter buffer); store the skip flag to the buffer (Fig.10, skip flag as one of QPs enters into quantization parameter buffer ); and encode a second block in the picture using the delta quantization parameter and the skip flag and without using the chroma quantization parameter (Fig.1, [222],[263]-[269], a quantization parameter including submb_qp_delta and submb_qp_present_flag obtained from a previously coded MB are used for deriving current quantization parameter in a encoding process).
Regarding claims 21, 30, Sato discloses The device of claim 19, The device of wherein the first block is a left adjacent block of the second block, or wherein the first block is a top adjacent block of the second block ([268]-[275]).
Regarding claims 22, 31, Sato discloses The device of claim 19, The device of wherein the memory is configurable to store a total number of nonzero coefficients for the first block, and wherein the processing circuitry is configurable to: store the total number of nonzero coefficients to the buffer; and encode the second block using the total number of nonzero coefficients ([380]-[382]).
Regarding claims 24, 33, Sato discloses The device of claim 19, wherein the buffer is separate from the memory (Figs.1, 10).
Regarding claim 28, see the rejection for claim 19.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 20, 23, 25, 29, 32, 34 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Sato, and further in view of CN 101653000 A PANDIT, PURVIN BIBHAS et al. (hereafter Pandit)
Regarding claims 20, 29, Pandit teaches The device of claim 19, The device of wherein the memory is configurable to store: an intra-prediction mode flag for the first block; and a reference index for the first block, and wherein the processing circuitry is configurable to: store the intra-prediction mode flag to the buffer; store the reference index to the buffer; and encode the second block using the intra-prediction mode flag and the reference index (P.8 para.2nd).
Therefore it would have been obvious to one of ordinary skill in the art at the time the claimed invention was made to modify the device disclosed by Sato to include the teaching in the same field of endeavor of Pandit, in order to provide method and device to achieve efficient memory resource usage, as taught by Pandit.
Regarding claims 23, 32, Pandit teaches The device of claim 19, The device of wherein the memory is configurable to store an intra-prediction mode parameter for the first block, and wherein the processing circuitry is configurable to encode the second block without using the intra-prediction mode parameter (P.12 para,2nd).
Regarding claims 25, 34, Pandit teaches The device of claim 19, The device of wherein the memory is configurable to store a reference picture index for the first block, and wherein the processing circuitry is configurable to: store the reference picture index to the buffer; and encode the second block using the reference picture index (P.9 para.3rd, P.10 para.4th).
Claims 26, 35 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Sato, and further in view of US 20050265455 A1 Kawaharada.
Regarding claims 26, 35, Kawaharada teaches The device of The device of claim 19, wherein the memory is configurable to store a motion vector difference for the first block, and wherein the processing circuitry is configurable to: store the motion vector difference to the buffer; and encode the second block using the motion vector difference ([21]).
Therefore it would have been obvious to one of ordinary skill in the art at the time the claimed invention was made to modify the device disclosed by Sato to include the teaching in the same field of endeavor of Kawaharada, in order to provide an MV encoding method capable of reducing an MV code length by way of utilizing past MV information, as taught by Kawaharada.
Claims 27, 36 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Sato, and further in view of US 20080285875 A1 EBIHARA; Masakazu et al. (hereafter EBIHARA).
Regarding claims 27, 36, EBIHARA teaches The device of claim 19, The device of wherein the memory is configurable to store a coded block pattern flag for the first block, and wherein the processing circuitry is configurable to: store the coded block pattern flag to the buffer; and encode the second block using the coded block pattern flag ([24], [64], [67]).
Therefore it would have been obvious to one of ordinary skill in the art at the time the claimed invention was made to modify the device disclosed by Sato to include the teaching in the same field of endeavor of EBIHARA, in order to realize highly efficient parallel processing in a plurality of processors, as taught by EBIHARA.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. WO 2010146782 A1, AU 2011310239 A1, WO 2009049248 A2 .
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY Y. LI whose telephone number is (571)270-3671. The examiner can normally be reached Monday Friday (8:30 AM- 4:30 PM) EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, David Czekaj can be reached at (571) 272-7327. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TRACY Y. LI/Primary Examiner, Art Unit 2487
Prosecution Insights