DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 7, 10 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fukamachi et al. (US 20110133860).
As to claim 1, Fukamachi et al.’s figure 1a shows a filter, comprising: a plurality of dielectric layers (second to tenth layers, ¶0042) including an outer dielectric layer (second layer), the plurality of dielectric layers stacked in a Z-direction to form a substrate having a top and a bottom (figure 1b), the substrate defining a perimeter, the outer dielectric layer disposed at the top of the substrate; a plurality of conductive layers (not shown that connect the strip patterns 3-5 and/or capacitance electrodes 7, 9, 12 and 13 to the via conductors, further see figures 2 and 10), at least one conductive layer of the plurality of conductive layers formed over a respective one dielectric layer of the plurality of dielectric layers (see figure 10) and an outer conductive layer (that connected to 3 and 5 on the second layer) of the plurality of conductive layers formed over the outer dielectric layer; an outer layer (first layer) disposed over the outer conductive layer; and a plurality of vias defined along the perimeter of the substrate, the plurality of vias extending from the outer conductive layer to the bottom of the substrate (0042 teaches that “small squares with diagonal lines indicate via-conductors... Lines of via-conductors completely surround a region in which the bandpass filter is constituted, to suppress interference with the outside”).
As to claim 2, the figures show that the at least one conductive layer defines a signal path, and wherein the signal path comprises an input and an output (P1 and P2, see figure 2).
As to claim 3, the figures show that the plurality of vias are defined along the perimeter of the substrate such that the plurality of vias surrounds the signal path.
As to claim 7, the figures show that the perimeter has a generally rectangular shape including four sides, and wherein a portion of the plurality of vias are defined along each of the four sides of the perimeter.
As to claim 10, the figures show that the outer conductive layer is formed over the outer dielectric layer such that the outer conductive layer is formed over the perimeter of the substrate.
Claim 20 recite similar limitations in claims above. Therefore, it is rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-5 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fukamachi et al. (US 20110133860).
As to claim 4, the figures show that the signal path comprises a plurality of elements formed from a conductive material, wherein the plurality of elements includes at least one element having an element line width in an X-Y plane extending perpendicular to the Z-direction. The figures fail to teach that the element line width is about 500 μm or less and the at least one conductive layer defining the signal path is disposed at a location along the Z-direction that is about 200 mm or less from the bottom substrate. However, one skilled in the art would have able to set any dimension value for the shown strip patterns or capacitance electrodes by routine experimentation. The particular claimed relative dimension limitations do not distinguish over the prior art since applicant has not disclosed that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. Selecting the claimed dimension is seen as an obvious design preference to achieve desired space occupation, inductance or capacitance values, MPEP 2144.05.
As to claim 5, Fukamachi et al.’s figures fail to show that an input contact pad is defined on the bottom of the substrate and an output contact pad is defined on the bottom of the substrate, and wherein at least one input via electrically connects the input of the signal path with the input contact pad and at least one output via electrically connects the output of the signal path with the output contact pad. However, IC with input and output terminals arranged on its bottom surface is well known in the art, i.e., IC arranged on a circuit board and communicates with other circuits). It would have been obvious to one having ordinary skill in the art to arrange the terminals as claimed for the purpose of saving space.
As to claim 8, via plated or filled with conductive material is well known in the art. Selecting to plate or fill the vias with conductive material is seen as an obvious design preference to ensure optimum performance.
Claim(s) 11-17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fukamachi et al. (US 20110133860) in view of Lee et al. (US 20070182512).
As to claims 11, 13-17 and 19, Fukamachi et al.’s figures fail to show that its device is arranged on a substrate. However, Lee et al.’s figure 1 shows a stripline circuit 120 is arranged on substrate 110. Therefore, it would have been obvious to one having ordinary skill in the art to arrange Fukamachi et al.’s device on a substrate for the purpose of communicate with other devices securely. Thus, the modified Fukamachi et al.’s figure further shows that a ground defined on the device substrate (see Lee et al.’s figure 2).
As to claim 12, the modified Fukamachi et al.’s figures show that the device substrate defines a mounting surface, and wherein the filter is attached to the mounting surface of the device substrate such that the plurality of dielectric layers and the plurality of conductive layers extend parallel to the mounting surface.
Claim(s) 21 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fukamachi et al. (US 20110133860) in view of Lee et al. (US 20070182512) and Taniguchi (US 20070241839).
Fukamachi et al.’s figure fails to show a cover disposed over the outer layer. However, Taniguchi’s figure 29 shows a similar device that comprises a cover (105) disposed over output layer (top ground layer, ¶0211). Therefore, it would have been obvious to one having ordinary skill in the art to further include a cover disposed over Fukamachi et al.’s outer layer for the purpose of protecting the filter device.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fukamachi et al. (US 20110133860) in view of Lee et al. (US 20070182512) and Sasaki et al. (US 7880564).
The modified Fukamachi et al.’s figure fails to show a first plurality that is stacked along the Z-direction, defines the bottom of the substrate, has a first thickness, and is free of a conductive material. However, Sasaki et al.’s figure 19 shows a similar dielectric stack comprising: a first plurality of dielectric layers (insulating sheets 6) and a second plurality of dielectric layers (other sheets); the first plurality of dielectric layers (6) is stacked along the Z-direction, defines the bottom of the substrate, has a first thickness, and is free of a conductive material; the second plurality of dielectric layers is stacked along the Z-direction, defines the top of the substrate, and has a second thickness, the outer conductive layer positioned on the second plurality of dielectric layers; and the at least one conductive layer is disposed between the first plurality of dielectric layers and the second plurality of dielectric layers such that the at least one conductive layer is sandwiched by the plurality of dielectric layers. Therefore, it would have been obvious to one having ordinary skill in the art to further add plurality of insulating sheets to Fukamachi et al.’s device and arranged the sheets as claimed for the purpose of reducing noise.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/QUAN TRA/
Primary Examiner
Art Unit 28433
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