DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-9, 11-14, & 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa (US 12,278,610 B2) in view of Madan et al. (US 2016/0164481 A1), hereinafter Madan.
Regarding claim 1, Ogawa discloses, in figure 1, a filter, comprising:
a plurality of dielectric layers (1a to 1g), the plurality of dielectric layers stacked in a Z-direction to form a substrate having a top and a bottom (Col. 5, Lines 50-51, “multilayer body 1 has a height direction Z in which dielectric layers 1a to 1g to be described later are laminated”); and
at least one conductive layer formed over a dielectric layer of the plurality of dielectric layers (Col. 6, Lines 30-31, “capacitor conductor patterns 5a, 5b, and 5c are provided on the upper main surface of the dielectric layer 1c”),
wherein the at least one conductive layer is positioned at a location along the Z-direction between the top and the bottom of the substrate (conductor patterns 5a, 5b, and 5c are positioned at a location along the Z-direction between the top 1g and bottom 1a of the dielectric formed substrate), but fails to disclose wherein the location along the Z-direction is about 200 μm or less from the bottom of the substrate.
However, Madan discloses, in figure 5A, wherein the location (conductor layer 102b formed on dielectric layer 104a) along the Z-direction is about 200 μm or less from the bottom of the substrate (Para [0106], “a thickness t.sub.1 of the first dielectric region 104a is selected to be in the range of about 8 μm to about 50 μm…the conductors have a thickness t.sub.2 that is in the range of about 16 μm to about 32 μm”…dielectric layer 104a is the bottom of the dielectric formed substrate and thus the conductor layer 102b is about 200 μm or less from the bottom of the substrate).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the location of Madan in the multilayer filter of Ogawa, to achieve the benefit of adjacent conductors in the stacked dielectric body exhibit a high degree of mutual coupling (Madan, Para [0106]).
Regarding claim 2, Ogawa in view of Madan discloses the filter of claim 1, and Ogawa continues to disclose, in figure 1, wherein the at least one conductive layer defines a signal path (capacitor conductor patterns 5a, 5b, & 5c define signal paths), and wherein the signal path comprises an input and an output (Col. 6, Lines 32-35, “capacitor conductor pattern 5a is connected to the first input/output terminal T1 by the via conductor 2a. The capacitor conductor pattern 5c is connected to the second input/output terminal T2 by the via conductor 2d.”).
Regarding claim 5, Ogawa in view of Madan discloses the filter of claim 2, and Ogawa continues to disclose, in figure 1, wherein an input contact pad is defined on the bottom of the substrate and an output contact pad is defined on the bottom of the substrate (Col. 6, Lines 3-6, “A first input/output terminal T1, a second input/output terminal T2…are provided on a lower main surface of the dielectric layer 1a”), and wherein at least one input via electrically connects the input of the signal path with the input contact pad and at least one output via electrically connects the output of the signal path with the output contact pad (Col. 6, Lines 32-35, “capacitor conductor pattern 5a is connected to the first input/output terminal T1 by the via conductor 2a. The capacitor conductor pattern 5c is connected to the second input/output terminal T2 by the via conductor 2d”).
Regarding claim 6, Ogawa in view of Madan discloses the filter of claim 1, and Madan continues to disclose, in figure 5A, wherein the substrate has a substrate thickness from the bottom to the top of the substrate along the Z-direction, and wherein the substrate thickness is about 500 μm or less (Para [0106], “a thickness t.sub.1 of the first dielectric region 104a is selected to be in the range of about 8 μm to about 50 μm. In certain configurations, the dielectric regions between conductors have a thickness that is less a thickness of the conductors. For example, in one embodiment, the conductors have a thickness t.sub.2 that is in the range of about 16 μm to about 32 μm”…at the lowest thicknesses for each of the dielectric layers and conductor portions, the substrate thickness is about 500 μm or less).
Regarding claim 7, Ogawa in view of Madan discloses the filter of claim 1, and Madan continues to disclose, in figure 5A, a cover formed over the substrate (cover 102p formed over the dielectric formed substrate).
Regarding claim 8, Ogawa in view of Madan discloses the filter of claim 1, and Madan continues to disclose, in figure 5A, wherein the cover has a cover thickness over the top of the substrate along the Z-direction (cover 102p comprises a thickness in the Z-direction over the top of the dielectric formed substrate), wherein the substrate has a substrate thickness from the bottom to the top of the substrate along the Z-direction (dielectric formed substrate has a thickness from 104a to 104o), wherein a total thickness of the filter includes the substrate thickness and the cover thickness (thickness from each dielectric layer and each conductor layer, including cover layer 102p), and wherein the total thickness is about 600 μm or less (Para [0106], “a thickness t.sub.1 of the first dielectric region 104a is selected to be in the range of about 8 μm to about 50 μm. In certain configurations, the dielectric regions between conductors have a thickness that is less a thickness of the conductors. For example, in one embodiment, the conductors [each 102 layer] have a thickness t.sub.2 that is in the range of about 16 μm to about 32 μm”…at the lowest thicknesses for each of the dielectric layers and conductor portions, the substrate thickness is about 600 μm or less).
Regarding claim 9, Ogawa in view of Madan discloses the filter of claim 2, and Ogawa continues to disclose, in figure 1, wherein the plurality of dielectric layers includes a first plurality of dielectric layers and a second plurality of dielectric layers (first plurality of dielectric layers 1d-1g and second plurality of dielectric layers 1a-1c), and wherein the at least one conductive layer is disposed between the first plurality of dielectric layers and the second plurality of dielectric layers such that the at least one conductive layer is sandwiched by the plurality of dielectric layers (conductive layer patterns 5a, 5b, & 5c are sandwiched between dielectric layers 1c & 1d).
Regarding claim 11, Ogawa discloses, in figure 1, an assembly, comprising:
a device having a device substrate defining a mounting surface (Col. 6, Lines 7-8, “the multilayer LC filter 100 is mounted on a substrate”); and
a filter attached to the device substrate (Col. 6, Lines 7-8, “the multilayer LC filter 100 is mounted on a substrate”), the filter (100), comprising:
a plurality of dielectric layers (1a to 1g), the plurality of dielectric layers stacked in a Z-direction to form a substrate having a top and a bottom (Col. 5, Lines 50-51, “multilayer body 1 has a height direction Z in which dielectric layers 1a to 1g to be described later are laminated”); and
at least one conductive layer formed over a dielectric layer of the plurality of dielectric layers (Col. 6, Lines 30-31, “capacitor conductor patterns 5a, 5b, and 5c are provided on the upper main surface of the dielectric layer 1c”),
wherein the at least one conductive layer is positioned at a location along the Z-direction between the top and the bottom of the substrate (conductor patterns 5a, 5b, and 5c are positioned at a location along the Z-direction between the top 1g and bottom 1a of the dielectric formed substrate), but fails to disclose wherein the location along the Z-direction is about 200 μm or less from the bottom of the substrate.
However, Madan discloses, in figure 5A, wherein the location (conductor layer 102b formed on dielectric layer 104a) along the Z-direction is about 200 μm or less from the bottom of the substrate (Para [0106], “a thickness t.sub.1 of the first dielectric region 104a is selected to be in the range of about 8 μm to about 50 μm…the conductors have a thickness t.sub.2 that is in the range of about 16 μm to about 32 μm”…dielectric layer 104a is the bottom of the dielectric formed substrate and thus the conductor layer 102b is about 200 μm or less from the bottom of the substrate).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the location of Madan in the multilayer filter of Ogawa, to achieve the benefit of adjacent conductors in the stacked dielectric body exhibit a high degree of mutual coupling (Madan, Para [0106]).
Regarding claim 12, Ogawa in view of Madan discloses the assembly of claim 11, and Ogawa continues to disclose, in figure 1, wherein the filter is attached to the mounting surface of the device substrate such that the bottom of the substrate of the filter is adjacent the mounting surface of the device substrate (Col. 6, Lines 7-8, “the multilayer LC filter 100 is mounted on a substrate”…such that the bottom dielectric layer of the dielectric formed substrate is adjacent to the top mounting surface of the device substrate).
Regarding claim 13, Ogawa in view of Madan discloses the assembly of claim 11, and Ogawa continues to disclose, in figure 1, wherein the filter is attached to the mounting surface of the device substrate such that the plurality of dielectric layers and the at least one conductive layer extend parallel to the mounting surface (Col. 6, Lines 7-8, “the multilayer LC filter 100 is mounted on a substrate”…such that the plurality of dielectric layers 104 and at least one conductive layer 5a, 5b, 5c extend parallel to the mounting surface of the device substrate).
Regarding claim 14, Ogawa in view of Madan discloses the assembly of claim 11, and Ogawa continues to disclose, in figure 1, wherein the at least one conductive layer defines a signal path (capacitor conductor patterns 5a, 5b, & 5c define signal paths), wherein the signal path comprises a plurality of resonators formed from a conductive material (Col. 9, Lines 63-65, “capacitor conductor patterns 5a, 5b, and 5c of the first to third LC parallel resonators LC1, LC2, and LC3”), and wherein the plurality of resonators includes at least one resonator having an element line width in an X-Y plane extending perpendicular to the Z-direction (patterns 5a, 5b, 5c of the first to third LC parallel resonators LC1, LC2, and LC3 having an element line width in an X-Y plane perpendicular to the Z-direction, see figure 1).
Regarding claim 16, Ogawa in view of Madan discloses the assembly of claim 14, and Ogawa continues to disclose, in figure 1, wherein an input contact pad is defined on the bottom of the substrate and an output contact pad is defined on the bottom of the substrate (Col. 6, Lines 3-6, “A first input/output terminal T1, a second input/output terminal T2…are provided on a lower main surface of the dielectric layer 1a”), and wherein at least one input via electrically connects an input of the signal path with the input contact pad and at least one output via electrically connects an output of the signal path with the output contact pad (Col. 6, Lines 32-35, “capacitor conductor pattern 5a is connected to the first input/output terminal T1 by the via conductor 2a. The capacitor conductor pattern 5c is connected to the second input/output terminal T2 by the via conductor 2d”).
Regarding claim 17, Ogawa in view of Madan discloses the assembly of claim 11, and Madan continues to disclose, in figure 5A, wherein the substrate of the filter has a substrate thickness from the bottom to the top of the substrate along the Z-direction, and wherein the substrate thickness is about 500 μm or less (Para [0106], “a thickness t.sub.1 of the first dielectric region 104a is selected to be in the range of about 8 μm to about 50 μm. In certain configurations, the dielectric regions between conductors have a thickness that is less a thickness of the conductors. For example, in one embodiment, the conductors have a thickness t.sub.2 that is in the range of about 16 μm to about 32 μm”…at the lowest thicknesses for each of the dielectric layers and conductor portions, the substrate thickness is about 500 μm or less).
Regarding claim 18, Ogawa in view of Madan discloses the assembly of claim 11, and Madan continues to disclose, in figure 5A, a cover formed over the substrate of the filter (cover 102p formed over the dielectric formed substrate), wherein the cover has a cover thickness over the top of the substrate along the Z-direction (cover 102p comprises a thickness in the Z-direction over the top of the dielectric formed substrate), wherein the substrate has a substrate thickness from the bottom to the top of the substrate along the Z-direction (dielectric formed substrate has a thickness from 104a to 104o), wherein a total thickness of the filter includes the substrate thickness and the cover thickness (thickness from each dielectric layer and each conductor layer, including cover layer 102p), and wherein the total thickness is about 600 μm or less (Para [0106], “a thickness t.sub.1 of the first dielectric region 104a is selected to be in the range of about 8 μm to about 50 μm. In certain configurations, the dielectric regions between conductors have a thickness that is less a thickness of the conductors. For example, in one embodiment, the conductors [each 102 layer] have a thickness t.sub.2 that is in the range of about 16 μm to about 32 μm”…at the lowest thicknesses for each of the dielectric layers and conductor portions, the substrate thickness is about 600 μm or less).
Regarding claim 19, Ogawa in view of Madan discloses the assembly of claim 11, and Ogawa continues to disclose, in figure 1, wherein the plurality of dielectric layers of the filter includes a first plurality of dielectric layers and a second plurality of dielectric layers (first plurality of dielectric layers 1d-1g and second plurality of dielectric layers 1a-1c), and wherein the at least one conductive layer of the filter is disposed between the first plurality of dielectric layers and the second plurality of dielectric layers such that the at least one conductive layer is sandwiched by the plurality of dielectric layers (conductive layer patterns 5a, 5b, & 5c are sandwiched between dielectric layers 1c & 1d).
Regarding claim 20, Ogawa discloses, in figure 1, a method of forming a filter, the method comprising:
forming a plurality of dielectric layers (Col. 5, Line 51, “dielectric layers 1a to 1g”);
forming at least one conductive layer over a dielectric layer of the plurality of dielectric layers (Col. 6, Lines 30-31, “capacitor conductor patterns 5a, 5b, and 5c are provided on the upper main surface of the dielectric layer 1c”); and
stacking the plurality of dielectric layers in a Z-direction to form a substrate having a top and a bottom (Col. 5, Lines 50-51, “multilayer body 1 has a height direction Z in which dielectric layers 1a to 1g to be described later are laminated”); and
wherein the at least one conductive layer is positioned at a location along the Z-direction between the top and the bottom of the substrate (conductor patterns 5a, 5b, and 5c are positioned at a location along the Z-direction between the top 1g and bottom 1a of the dielectric formed substrate), but fails to disclose wherein the location along the Z-direction is about 200 μm or less from the bottom of the substrate.
However, Madan discloses, in figure 5A, wherein the location (conductor layer 102b formed on dielectric layer 104a) along the Z-direction is about 200 μm or less from the bottom of the substrate (Para [0106], “a thickness t.sub.1 of the first dielectric region 104a is selected to be in the range of about 8 μm to about 50 μm…the conductors have a thickness t.sub.2 that is in the range of about 16 μm to about 32 μm”…dielectric layer 104a is the bottom of the dielectric formed substrate and thus the conductor layer 102b is about 200 μm or less from the bottom of the substrate).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the location of Madan in the multilayer filter of Ogawa, to achieve the benefit of adjacent conductors in the stacked dielectric body exhibit a high degree of mutual coupling (Madan, Para [0106]).
Claims 3-4 & 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa in view of Madan as applied to claims 1-2, 5-9, 11-14, & 16-20 above, and further in view of Budyakov et al. ("Prospects for design and construction development of integral circuits of LC–filters based on the modern dielectric materials", IOP Conf. Ser.: Mater. Sci. Eng., 1029 012098, 2021), hereinafter Budyakov.
Regarding claim 3, Ogawa in view of Madan disclose the filter of claim 2, and Ogawa continues to disclose, in figure 1, wherein the signal path comprises a plurality of elements formed from a conductive material (conductive patterns 5a, 5b, & 5c), wherein the plurality of elements includes at least one element having an element line width in an X-Y plane extending perpendicular to the Z-direction (the conductive patterns 5a, 5b, & 5c have a line width in the X-Y plane extending perpendicular to the Z-direction, see figure 1), but fails to disclose wherein the element line width decreases as the location along the Z-direction of the at least one conductive layer decreases such that the conductive layer is closer to the bottom of the substrate.
However, Budyakov discloses, in figure 1, wherein the element line width decreases as the location along the Z-direction of the at least one conductive layer decreases such that the conductive layer is closer to the bottom of the substrate (pg. 3, “production of multilayer printed circuit board provides for changing the width of the conducting pattern (picture) during etching process, and the interval of spread of the measurements raises with the increase in the foil thickness. The greatest spread in the values of the conductor width will be observed in dielectrics with standard foil thickness of 35 μm (microns), at which the spread will be more than 50 μm. When using dielectrics with ultra–thin foil in this process, it is possible to achieve the accuracy of reproducing the current–conducting pattern (picture) [Symbol font/0xB1] (5–10) μm”…i.e., the line width of the conducting patterns decrease as the thickness of the dielectric formed substrate decreases and thus the conducting patterns get closer to the bottom of the dielectric formed substrate)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the decreased line width of Budyakov in the filter of Ogawa and Madan, to achieve the benefit of creating a narrow-band filter intended for operation in a higher frequency range of microwave filters (Budyakov, Abstract).
Regarding claim 4, the combination of Ogawa, Madan, and Budyakov disclose the filter of claim 3, and Ogawa continues to disclose, in figure 1, wherein the plurality of elements is a plurality of resonators (Col. 9, Lines 63-65, “capacitor conductor patterns 5a, 5b, and 5c of the first to third LC parallel resonators LC1, LC2, and LC3”).
Regarding claim 15, Ogawa in view of Madan disclose the assembly of claim 14, but fail to disclose wherein the element line width decreases as the location along the Z-direction of the at least one conductive layer decreases such that the conductive layer is closer to the bottom of the substrate.
However, Budyakov discloses, in figure 1, wherein the element line width decreases as the location along the Z-direction of the at least one conductive layer decreases such that the conductive layer is closer to the bottom of the substrate (pg. 3, “production of multilayer printed circuit board provides for changing the width of the conducting pattern (picture) during etching process, and the interval of spread of the measurements raises with the increase in the foil thickness. The greatest spread in the values of the conductor width will be observed in dielectrics with standard foil thickness of 35 μm (microns), at which the spread will be more than 50 μm. When using dielectrics with ultra–thin foil in this process, it is possible to achieve the accuracy of reproducing the current–conducting pattern (picture) [Symbol font/0xB1] (5–10) μm”…i.e., the line width of the conducting patterns decrease as the thickness of the dielectric formed substrate decreases and thus the conducting patterns get closer to the bottom of the dielectric formed substrate)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the decreased line width of Budyakov in the filter of Ogawa and Madan, to achieve the benefit of creating a narrow-band filter intended for operation in a higher frequency range of microwave filters (Budyakov, Abstract).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ogawa in view of Madan as applied to claims 1-2, 5-9, 11-14, & 16-20 above, and further in view of Taniguchi (US 2007/0241839 A1).
Regarding claim 10, Ogawa in view of Madan disclose the filter of claim 1, but fail to disclose wherein the plurality of dielectric layers is formed from a dielectric material having a dielectric constant less than about 20.
However, Taniguchi discloses, in figure 2A, wherein the plurality of dielectric layers is formed from a dielectric material having a dielectric constant less than about 20 (Para [0134], “dielectric layers are preferably made of low temperature co-fired ceramic (LTCC) with a relative dielectric constant in the range of about 6 to about 80”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the dielectric constant of Taniguchi in the dielectric layers of Ogawa and Madan, to achieve the benefit of implementing dielectric layers with achieved high capacitance per unit area from the capacitor patterns formed thereon and thus reducing the overall size of the filter (Taniguchi, Para [0067]).
Conclusion
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/TYLER J PERENY/ Examiner, Art Unit 2842