DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 to 21 are presented for examination. The preliminary amendment filed 12-30-2024 cancelled claim 3 and added new claims 4 to 21.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119, which papers have been placed of record in the file.
Information Disclosure Statement
The references listed in the information disclosure statement submitted on 11-12-2024 have been considered by the examiner (see attached PTO-1449).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,164,376. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of the instant application is anticipated by the patent claim in that the patent claim contains all the limitations of claim 1 of the instant application. Claim 1 of the instant application is broader than claim 1 of the patent and a patent of the current application would, necessarily extend the rights of the patent should the current application issues as a patent. Claim 1 of the instant application therefore is not patently distinct from the earlier patent claim and as such is unpatentable for obvious-type double patenting. The table below shows the similarities and differences between the claims.
US 12, 164, 376
Application 18/944,088
1. A storage device comprising:
1.(Currently Amended) A storage device comprising:
a memory device configured to store original data; and
A memory device; and
a controller configured to control the memory device,
A controller configured to control the memory device,
the controller including a first error correction circuit configured to correct an error of the original data;
Wherein the controller comprises an error correction circuit configured to correct an error of data;
a second error correction circuit configured to correct an error of the original data, a maximum number of correctable error bits of the second error correction circuit being greater than a maximum number of correctable error bits of the first error correction circuit;
a mapping memory configured to store at least some of parity bits generated by the second error correction circuit and store an address of the memory device at which the original data is stored;
A mapping memory configured to store at least some of parity bits generated by the error correction circuit and store an address of the memory device at which the data is stored; and
a control block configured to control the first error correction circuit, the second error correction circuit, and the mapping memory; wherein, based on a write request or a read request being received from outside of the storage device,
A control block configured to write original data in the memory device in response to a write request, read data stored in the memory device, and control the error correction circuit based on a result of comparing the read data with the original.
the control block is further configured to check whether a write address or a read address is identical to an address of the memory device stored in the mapping memory and select one of the first error correction circuit and the second error correction circuit to perform error correction encoding or error correction decoding.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11 and 19 are rejected under 35 U.S.C. 102(a0(1) as being anticipated by Kim et al. (USPAP 2021/0320673).
Claim 11 and 19:
Kim teaches a method and an apparatus for correct errors in a memory system, the method comprising: a host (1000) external to a memory system (2000) with a memory device (2200) configured to store data and a memory controller (2100) configured to control the memory system according to a request of the host (see fig. 8 and par. 0099). Kim teaches that the host is a device which stores data in the memory system or retrieves data from the memory system and the host interface (2110) in the controller communicates with the host by using at least one interface protocol (see par. 0101 to 0103).
Kim teaches that the data programmed (“writing”) into the memory device is new data (“original”) (see par. 0105). Kim teaches that program data received from the host is temporarily stored in a buffer memory (2140) of the controller (see par. 0108). Kim teaches that data read from the memory device is based on a command and an address received from the host (see par. 0104).
Kim teaches that the controller includes an error correction circuit (2150) for performing error correction encoding on program data and perform error correction decoding on read data (see par. 0109). Kim teaches that the central processing unit (2120) (“control block”) may perform various operations or generate a command and an address so as to control the memory device (see par. 0104). Kim teaches that the data provided from the host may be a message, and the data read from the memory device may be a codeword (see par. 0005).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Jung (USPAP 2023/0140746).
Claims 1, 7 and 8:
Jung substantially teaches the claimed invention. Jung teaches a method and an apparatus for recovering data in a memory system, the memory system comprising a controller (130) coupled to a memory device (150) through a NAND interface (142) (see fig. 1 and par. 0050). Jung teaches that the memory controller comprises a error correction circuitry (138) that checks whether an error is included in the read data items (RD) transmitted from the memory device and cure or recover a detected error included in the read data items (RD) (see par. 0057). Jung teaches that the controller stores repaired read data in another area of the memory device (see par. 0059). Jung teaches that the controller can check whether an error is included in the data transmitted to the memory device and then repair and recover the error when the error is detected (see par. 0060).
Jung teaches that detecting errors in the read data includes an additional read operation reading a data group that includes a parity and a plurality of data item (see par. 0061). Jung teaches that the controller includes a parity generator (512) for performing an exclusive-OR (XOR) operations on data items to generate a parity (see par. 0055). Jung teaches that the controller includes a write data configuration unit (514) that can configure a data group based on the plural data items and the parity to be programmed in the memory device (see par. 0056).
Jung teaches that the controller comprises multiple circuitries including a processor (134) and a memory (144) wherein the processor controls the memory device (see fig. 2 and par. 0090). Jung teaches that the memory of the controller temporary stores the data read from memory and information used for programming (see par. 0103). Jung teaches that the controller includes a flash translation layer (FTL) (240) and the FTL includes a map manager (44) wherein the map manager determines a physical address corresponding to a logical address based on a request received from a host manager (see fig. 3 and par. 0119 et seq.). Jung teaches that the map manager stores the entire map table in the memory device and cache mapping entries according to the storage capacity of the memory (144) (see par. 0130).
Jung teaches that the controller performs a read operation based on a read request and a write operation to store data input from the host (see par. 0080). Jung teaches that the controller includes a processor (“control block”) for controlling the memory device; however, Jung fails to specifically teach the limitation of: a control block configured to control the error correction circuit based on a result of comparing the read data with the original data. This teaching is obvious to the teachings of Jung since Jung teaches that in another embodiment for recovering the read data includes a memory device being configured to store an original data group that includes plural data bits and an original parity bit corresponding to the plural data bits. Jung teaches that the memory device generates a revised parity bit when the original data group has a second error-data bit and replacing the second error-data bit (see par. 0047).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Jung to include the claimed limitation of “a control block configured to control the error correction circuit based on a result of comparing the read data with the original data” because Jung teaches that a memory system having a memory controller and a memory device performs a data recovery operation based on an original data and the detection of a second error data bit. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a memory system for recovering read data by evaluating the original data group and the error data bit and thus improving the input/output operation as taught by Jung (see par. 0048 et seq.).
Claims 2, 4 and 5 to 6 are rejected under 35 U.S.C. 103 as being unpatentable over Jung in view of Kim.
As per claims 2 and 5 to 6, Jung teaches a method and an apparatus for error recovery in a memory system as detailed with the rejection of claim 1; however, Jung fails to teach the claimed limitation of: “generating a codeword by encoding the original data based on a result of comparing the read data with the original data. Kim in an analogous art teaches an improved method for detecting and correcting errors in a memory system comprising a memory controller (2100) coupled to a memory device (2200) wherein the memory controller comprises an error correction an error correction circuit (2150) for performing error correction encoding on program data and perform error correction decoding on read data (see par. 0109). Kim teaches that the central processing unit (2120) (“control block”) may perform various operations or generate a command and an address so as to control the memory device (see par. 0104). Kim teaches that program data received from the host is temporarily stored in a buffer memory (2140) (“mapping memory”) of the controller (see par. 0108). Kim teaches that the data provided from the host may be a message, and the data read from the memory device may be a codeword (see par. 0005).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the error recovery of a memory system of Jung to include the improved error correction of a memory system of Kim that comprises an error correction circuit for performing an encoding operation. Kim teaches that an improved error correction capability for correcting errors in a memory system includes performing error correction encoding operation. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ an improved error correction operation for a memory system as taught by Kim (see par. 0026 et seq.).
As claim 4, Jung teaches that the memory controller includes a parity generator (512) and a parity data associated with the plurality of data items (see par. 0027).
Claims 12 to 13, 17, 18, 20 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al..
As per claims 12, 20 and 21, Kim teaches that the internal memory (2160) of the controller may store an address mapping table in which logical and physical addresses are mapped to each other (see par. 0110). Kim teaches that program data received from the host is temporarily stored in a buffer memory (2140) (“mapping memory”) of the controller (see par. 0108). Kim teaches that the central processing unit of the controller generates various addresses and commands and transmit the generated commands and addresses to the memory device (see par. 0104). Kim fails to specifically teach the limitations of: “storing at least a portion of the codeword in the mapping memory and storing the remaining of the codeword in the memory device; however, this teaching is obvious to the teachings of Kim because Kim teaches that the error correction circuit outputs a codeword group to the channel and an error correction is performed on a target read data (see ar. 0030 et seq.).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim to include the claimed limitation of “store at least a portion of the codeword in the mapping memory; and store the remaining of the codeword in the memory device” because Kim teaches that an improved error correction capability for correcting errors in a memory system includes performing error correction on a target codeword read from among a plurality of codewords. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ an improved error correction operation for a memory system as taught by Kim (see par. 0026 et seq.).
As per claim 13, Kim teaches that encoding and decoding the codeword includes a plurality of data symbols and multiple parity symbols (see par. 0009).
As per claims 17 and 18, Kim teaches that a buffer memory of the controller temporarily store data to be programmed as well as data read from the memory device (see par. 0108). Kim teaches that memory device comprises at least one storage area for storing data (see par. 0111). Kim teaches that the control logic performs a verification operation determining whether a pass or fail has occurred (see par. 0116).
Allowable Subject Matter
Claims 9 to 10 and 14 to 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (2020/0401479) teaches a memory controller and method of operating the same.
Meir et al. (2009/0319843) teaches a data error correction handling method for a memory device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHELLY A CHASE whose telephone number is (571)272-3816. The examiner can normally be reached Mon-Thu 8:00-5:30, 2nd Friday 8:00-4:30.
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/Shelly A Chase/ Primary Examiner, Art Unit 2112