DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 – 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 20 of U.S. Patent No. 12,176,908. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Re claim 1,
Claim 1 of U.S. Patent No. 12,176,908 recites of a multiple stage pipelined phase rotator, comprising: a first stage of phase rotators comprising a first number of bits based on a total number of bits dedicated to phase selection, wherein each phase rotator in the first stage comprises a first number of phase interpolator unit cells determined according to the first number of bits; and a second stage comprising a second number of phase rotators receiving outputs from the first stage, the second stage outputting a first weighted sum of respective clock phases generated by the second number of phase rotators, wherein the second stage has a second number of bits based on the total number of bits dedicated to phase selection, and wherein each phase rotator in the second stage comprises a second number of phase interpolator unit cells determined according to the second number of bits dedicated to phase selection, wherein the total number of bits dedicated to phase selection is split across the first stage and the second stage.
Furthermore, because omission element(s) in the claim would make the claim in the instant application broader, it would have been obvious to one of ordinary skill in the art at the time of the invention that the claim in the instant application is merely an obvious variation of the claim in the copending application. It is well settled that omission of an element and it function is an obvious expedient if the remaining elements perform the same function as before. In re Karlson, 163 USPQ 184 (CCPA 1963). Also note Ex parte Rainu, 168 USPQ 184 (CCPA 1969). In light of the foregoing discussion, the broad claim of the instant application is rejected as obvious double patenting over the narrower copending claim.
Re claim 2,
Claim 2 of U.S. Patent No. 12,176,908 recites of wherein the first stage and the second stage further comprise a first plurality of summation nodes and a second plurality of summation nodes, respectively, receiving outputs of phase interpolator unit cells of respective phase rotators.
Re claim 3,
Claim 3 of U.S. Patent No. 12,176,908 recites of further comprising a third stage comprising a third number of phase rotators receiving outputs from the second number of phase rotators of the second stage, the third stage outputting a second weighted sum of respective clock phases generated by the third number of phase rotators, wherein the third number of phase rotators is less than the second number of phase rotators.
Re claim 4,
Claim 4 of U.S. Patent No. 12,176,908 recites of wherein the second number of bits dedicated to phase selection used in the second stage is greater than the first number of bits dedicated to phase selection used in the first stage.
Re claim 5,
Claim 5 of U.S. Patent No. 12,176,908 recites of wherein the first number of phase interpolator unit cells and the second number of phase interpolator unit cells comprise inverters with controllable variable drive strength or common source amplifiers.
Re claim 6,
Claim 6 of U.S. Patent No. 12,176,908 recites of further comprising an intermediate stage between the first stage and the second stage, the intermediate stage comprising a third plurality of summation nodes receiving outputs of the first plurality of summation nodes.
Re claim 7,
Claim 7 of U.S. Patent No. 12,176,908 recites of the total number of bits dedicated to phase selection across the first stage and the second stage is nine.
Re claim 8,
Claim 8 of U.S. Patent No. 12,176,908 recites of a method for pipelining phase rotators, comprising: implementing a first stage of phase rotators comprising a first number of bits based on a total number of bits dedicated to phase selection, and wherein each phase rotator in the first stage comprises a first number of phase interpolator unit cells determined according to the first number of bits; and implementing a second stage comprising a second number of phase rotators receiving outputs from the first stage, the second stage outputting a first weighted sum of respective clock phases generated by the second number of phase rotators, wherein the second stage has a second number of bits based on the total number of bits dedicated to phase selection, and wherein each phase rotator in the second stage comprises a second number of phase interpolator unit cells determined according to the second number of bits dedicated to phase selection, wherein the total number of bits dedicated to phase selection is split across the first stage and the second stage.
Furthermore, because omission element(s) in the claim would make the claim in the instant application broader, it would have been obvious to one of ordinary skill in the art at the time of the invention that the claim in the instant application is merely an obvious variation of the claim in the copending application. It is well settled that omission of an element and it function is an obvious expedient if the remaining elements perform the same function as before. In re Karlson, 163 USPQ 184 (CCPA 1963). Also note Ex parte Rainu, 168 USPQ 184 (CCPA 1969). In light of the foregoing discussion, the broad claim of the instant application is rejected as obvious double patenting over the narrower copending claim.
Re claim 9,
Claim 9 of U.S. Patent No. 12,176,908 recites of the first stage and the second stage further comprise a first plurality of summation nodes and a second plurality of summation nodes, respectively, receiving outputs of phase interpolator unit cells of respective phase rotators.
Re claim 10,
Claim 10 of U.S. Patent No. 12,176,908 recites of further comprising implementing a third stage comprising a third number of phase rotators receiving outputs from the second number of phase rotators of the second stage, the third stage outputting a second weighted sum of respective clock phases generated by the third number of phase rotators, wherein the third number of phase rotators is less than the second number of phase rotators.
Re claim 11,
Claim 11 of U.S. Patent No. 12,176,908 recites of wherein the second number of bits dedicated to phase selection used in the second stage is greater than the first number of bits dedicated to phase selection used in the first stage.
Re claim 12,
Claim 12 of U.S. Patent No. 12,176,908 recites of wherein the first number of phase interpolator unit cells and the second number of phase interpolator unit cells comprise inverters with controllable variable drive strength or common source amplifiers.
Re claim 13,
Claim 13 of U.S. Patent No. 12,176,908 recites of further comprising implementing an intermediate stage between the first stage and the second stage, the intermediate stage comprising a third plurality of summation nodes receiving outputs of the first plurality of summation nodes.
Re claim 14,
Claim 14 of U.S. Patent No. 12,176,908 recites of wherein the total number of bits dedicated to phase selection across the first stage and the second stage is nine.
Re claim 15,
Claim 15 of U.S. Patent No. 12,176,908 recites of a Clock-and-Data Recovery (CDR) loop, comprising: a data sampler that samples incoming data; and a phase rotator that receives a code from a loop filter and instructs the data sampler to sample the incoming data, wherein a Finite Impulse Response (FIR) filter is interposed between an output of the phase rotator and an input of the data sampler to reduce phase noise introduced by the phase rotator.
Furthermore, because omission element(s) in the claim would make the claim in the instant application broader, it would have been obvious to one of ordinary skill in the art at the time of the invention that the claim in the instant application is merely an obvious variation of the claim in the copending application. It is well settled that omission of an element and it function is an obvious expedient if the remaining elements perform the same function as before. In re Karlson, 163 USPQ 184 (CCPA 1963). Also note Ex parte Rainu, 168 USPQ 184 (CCPA 1969). In light of the foregoing discussion, the broad claim of the instant application is rejected as obvious double patenting over the narrower copending claim.
Re claim 16,
Claim 16 of U.S. Patent No. 12,176,908 recites of wherein the FIR filter comprises a Kaiser-Bessel FIR.
Re claim 17,
Claim 1 of U.S. Patent No. 12,176,908 recites of wherein the phase rotator comprises: a first stage comprising a first number of phase rotators in parallel generating respective clock phases offset by a fixed amount; and a second stage comprising a second number of phase rotators receiving outputs from the first number of phase rotators of the first stage, the second stage outputting a first weighted sum of respective clock phases generated by the second number of phase rotators, wherein the second number of phase rotators is less than the first number of phase rotators, and wherein a total number of bits dedicated to phase selection is split across the first stage and the second stage.
Re claim 18,
Claim 18 of U.S. Patent No. 12,176,908 recites of wherein the data sampler is part of an Analog-to-Digital Converter (ADC) and is implemented along with the phase rotator in an analog macro and the loop filter are implemented in a Digital Signal Processing (DSP) engine.
Re claim 19,
Claim 19 of U.S. Patent No. 12,176,908 recites of wherein the FIR filter comprises an analog FIR using voltage mode summation.
Re claim 20,
Claim 20 of U.S. Patent No. 12,176,908 recites of wherein a total number of unit devices is equal to six times two raised to a power of half of the total number of bits.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Sun et al (US 10,992,501) in view of Gotman et al (US 2014/0254644).
Re claim 15, Sun teaches of a Clock-and-Data Recovery (CDR) loop (Fig.6), comprising: a data sampler that samples incoming data (ADC, Fig.6); and a phase rotator (phase interpolator, #620, Fig.6) that receives a code from a loop filter (loop filter, #612, Fig.6, Col 5, Lines 35 – 48 and Col 8, Lines 20 – 30) and instructs the data sampler to sample the incoming data (INPUT, Fig.6), wherein a delay line with an adjuster (DL, Adjust, Fig.6 and Col 8, Lines 25 – 35) is interposed between an output of the phase rotator (phase interpolator, #620, Fig.6) and an input of the data sampler (ADC, Fig.6) to reduce phase noise introduced by the phase rotator (the clock skew adjustment circuit controls at least one phase offset of a phase interpolator, Col 2, Lines 54 – 59). However, Sun does not specifically teach of a Finite Impulse Response (FIR) filter to be interposed between an output of the phase rotator and an input of the data sampler to reduce the phase noise introduced by the phase rotator.
Gotman teaches of a Finite Impulse Response (FIR) filter that comprises a delay line and plurality of taps that are adjusted so as to reduce phase noise (Paragraphs 0114 – 0115 and Fig.3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have formed a FIR filter that comprises a delay line and a plurality of taps to allow precise control over phase distortion.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Sun and Gotman in view of Schuck et al (US 2018/0106889).
Re claim 16, Sun and Gotman teach all the limitations of claim 15 except of wherein the FIR filter comprises a Kaiser-Bessel FIR.
Schuck teaches of a FIR filter comprises a Kaiser-Bessel FIR (Paragraph 0040).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the FIR filter comprise a Kaiser-Bessel FIR to help prevent the spectral characteristics of signals to not be masked by sidebands.
Claims 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sun and Gotman in view of Agrawal (US 2013/0207707).
Re claim 17, Sun and Gotman teach all the limitations of claim 15 except of wherein the phase rotator comprises: a first stage comprising a first number of phase rotators in parallel generating respective clock phases offset by a fixed amount; a second stage comprising a second number of phase rotators receiving outputs from the first number of phase rotators of the first stage, the second stage outputting a first weighted sum of respective clock phases generated by the second number of phase rotators; wherein the second number of phase rotators is less than the first number of phase rotators, and wherein a total number of bits dedicated to phase selection is split across the first stage and the second stage.
Agrawal teaches of a multiple stage pipelined phase rotator (Fig.11), comprising: a first stage comprising a first number of phase rotators in parallel (#802, #804, Fig.11) generating respective clock phases offset by a fixed amount (quarter clock cycle, Paragraphs 0059 – 0060); a second stage comprising a second number of phase rotators receiving outputs from the first number of phase rotators of the first stage (#806, Fig.11), the second stage outputting a first weighted sum of respective clock phases generated by the second number of phase rotators (weighted sum, Paragraph 0003); wherein the second number of phase rotators (second number = 1, Fig.11) is less than the first number of phase rotators (first number = 2, Fig.11), and wherein a total number of bits (n-bit digital control signal, Paragraphs 0036 and 0046, 2-bit select signal, Paragraph 0098) dedicated to phase selection is split across the first stage and the second stage (Paragraph 0060).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the PR of Sun have the structure of the PR of Agrawal for higher phase resolution.
Re claim 20, Sun teaches of wherein a total number of unit devices is equal to six times two raised to the power of half of the total number of bits (Examiner has not given patentable weight on the wherein clause, since there is no functional relationship between the unit devices of the wherein clause and the phase rotator of claim 17, See MPEP 2111.04 and 2111.05).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Sun and Gotman in view of Ganesan et al (US 2022/0070031).
Re claim 18, Sun and Gotman teach all the limitations of claim 15 except of wherein the data sampler is part of an Analog-to-Digital Converter (ADC) and is implemented along with the phase rotator in an analog macro and the loop filter are implemented in a Digital Signal Processing (DSP) engine.
Ganesan teaches of a data sampler being part of an Analog-to-Digital Converter (ADC) and is implemented along with the phase rotator in an analog macro (#108 and #110, Fig.1) and the loop filter are implemented in a Digital Signal Processing (DSP) engine (#138 in DSP, #102, Fig.1).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the ADC implemented along with the phase rotator for accurately aligning the clock signal with the data signal in the analog macro and have the loop filter implemented in a Digital Signal Processing for fast computation.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Sun and Gotman in view of Clark (US 9,900,017).
Re claim 19, Sun and Gotman teach all the limitations of claim 15 except of wherein the FIR filter comprises an analog FIR using voltage mode summation.
Clark teaches of wherein the FIR filter comprises an analog FIR using voltage mode summation (Col 2, Lines 56 – 67 to Col 3, Lines 1 – 7, Figures 1 and 5).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the FIR filter comprise an analog FIR use a voltage mode summation for high-speed operation by removing the need for complex and high-speed multipliers.
Allowable Subject Matter
Claims 1 – 14 would be allowable if rewritten or amended or a timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome the non-statutory double patenting rejection, set forth in this Office action.
Conclusion
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/ARISTOCRATIS FOTAKIS/
Primary Examiner, Art Unit 2633