DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-5, 14-15 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Inoue (USPN 2007/0120193).
Regarding claim 1, Inoue discloses a transient voltage suppressor (TVS) circuit (the transient protection circuit shown in figures 6, 7) comprising:
a semiconductor substrate (a substrate 201, see figure 7) comprising a first TVS device (a Zener diode 101) and a second TVS device (a TVS device 103, see figures 6 7) electrically connected in series; and a resistor (a resistor 102), wherein the resistor (102) and at least one of the first TVS device (101) and the second TVS device (103) are electrically connected in parallel (see figure 6).
Regarding claim 2, Inoue discloses wherein the TVS circuit is a discrete device (see figure 6).
Regarding claim 3, Inoue discloses wherein the semiconductor substrate (201) comprises the resistor (the resistor 102 is equivalent to a resistor 207 shown in figures 7).
Regarding claim 4, Inoue discloses wherein the resistor (201) is a resistive current path formed by a continuously p-doped (212 or 231, 233) or n-doped part (211, 213 or 232, 235) of the semiconductor substrate. (see figures 7, 11).
Regarding claim 5, Inoue discloses wherein the resistive current path includes a part of the semiconductor substrate in an active area of the at least one of the first TVS device and the second TVS device (a top surface of the substrate 201 or 256 wherein the TVS device 103 or 230 formed).
Regarding claim 14, Inoue discloses a method of manufacturing a transient voltage suppressor (TVS) circuit (see figure 6, 7), the method comprising:
forming a first TVS device (a first TVS device 101 includes a layout structure 220) and a second TVS device (a second TVS device 103 includes a layout 221) in a semiconductor substrate (201),
the first TVS device and the second TVS device being electrically connected in series (see figure 6); and
providing a resistor (102), wherein the resistor and at least one of the first TVS device (101) and the second TVS device (103) are electrically connected in parallel .
Regarding claim 15, Inoue discloses Regarding claim 3, Inoue discloses wherein the semiconductor substrate (201) comprises the resistor (the resistor 102 is equivalent to a resistor 207 shown in figures 7).
2. Claims 1-2, 6-7 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chow et al (USPN 2014/0327048).
Regarding claim 1, Chow discloses a transient voltage suppressor (TVS) circuit (the transient protection circuit 702 shown in figures 7, ), comprising:
a semiconductor substrate (a substrate shown in figure 8 ) comprising a first TVS device (a diode 314) and a second TVS device (a TVS device 316, see figure 7) electrically connected in series; and a resistor (a resistor 312), wherein the resistor (312) and at least one of the first TVS device (314) and the second TVS device (316) are electrically connected in parallel (see figure 7).
Regarding claim 2, Chow discloses wherein the TVS circuit (702) is a discrete device (see figure 7).
Regarding claim 6, Chow discloses wherein the semiconductor substrate further comprises a third TVS device (716) and a fourth TVS device (714) electrically connected in series, and a second resistor (712), wherein the second resistor (712) and at least one of the third TVS device (716) and the fourth TVS device (714) are electrically connected in parallel (see figure 7).
Regarding claim 7, Chow discloses wherein cross-section designs of the first TVS device (314) and the third TVS device (716) correspond to each other (see figure 8).
Allowable Subject Matter
3. Claims 8-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANNY NGUYEN whose telephone number is (571)272-2054. The examiner can normally be reached M-F 8:00AM-4:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-271-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANNY NGUYEN/Primary Examiner, Art Unit 2838
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