Memory Usage Configurations for Integrated Circuit Devices having Analog Inference Capability

Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Rejections - 35 USC § 102 1. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 2. Claim(s) 1-2, 13-14, 19, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ng et al (Pub. No.: US 2019/0114529). 3. Regarding independent claim 1, Ng et al teaches a device (Fig. 5), comprising: memory cells (Fig. 5, #226), each programmable in a first mode (Fig. 5, #520, paragraph [0044], lines 1-5) to perform operations of multiplication and accumulation (Fig. 5, #520, paragraph [0044], lines 1-5) and in a second mode (Fig. 5, #516, #518 for example, where #516 stores the data of pre-layer instruction, and #518 writes the output data, paragraph [0051]-[0052]) to store data (Fig. 5, paragraph [0044], lines 19-21); and a register (Fig. 5, #408) configured to store a parameter (Fig. 5, #408, paragraph [0049]) identifying, among a plurality of configurations (see paragraph [0049], lines 3-9), a current configuration of usages (Fig. 5, paragraph [0053]) of the memory cells (Fig. 5, #226). 4. Regarding claim 2, Ng et al teaches the memory cells (Fig. 5, #226) are configured in a plurality of layers (Fig. 5, #516, #518, #520); wherein access to the memory cells (Fig. 5, #226) is limited at least in part by the parameter (Fig. 5, #408, paragraph [0049]) identifying the current configuration (see paragraph [0049], where each parameter is used for specific layer of memory, for example the weight data in #520 is used for multiplication matrix operation); and wherein the parameter (Fig. 5, #408, paragraph [0049]) is configured to identify a first subset of the layers (Fig. 5, #520) being programmed in the first mode (Fig. 5, #520, paragraph [0044], lines 1-5) and a second subset of the layers (Fig. 5, #518) being programmed in the second mode (Fig. 5, #516, #518 for example, where #516 stores the data of pre-layer instruction, and #518 writes the output data, paragraph [0051]-[0052]). 5. Regarding independent claim 13, Ng et al teaches storing (see paragraph [0049]), in a register (Fig. 5, #408) of a memory device, a parameter (Fig. 5, #408, paragraph [0049]); programming (paragraph [0044], lines 1-15), according to the parameter (Fig. 5, #408, paragraph [0049]) in the register (Fig. 5, #408), a first portion of memory cells (Fig. 5, #226) in the memory device in a first mode (Fig. 5, #520, paragraph [0044], lines 1-5) to perform operations of multiplication and accumulation (Fig. 5, #520, paragraph [0044], lines 1-5); and programming (paragraph [0044], lines 19-21), according to the parameter (Fig. 5, #408, paragraph [0049]) in the register (Fig. 5, #408), a second portion of the memory cells (Fig. 5, #226) in the memory device in a second mode (Fig. 5, #516, #518 for example, where #516 stores the data of pre-layer instruction, and #518 writes the output data, paragraph [0051]-[0052]) to store data (Fig. 5, paragraph [0044], lines 19-20) 6. Regarding claim 14, Ng et al teaches the method further comprising: limiting, at least in part (see paragraph [0049], where each parameter is used for specific layer of memory, for example the weight data in #520 is used for multiplication matrix operation) by the parameter (Fig. 5, #408, paragraph [0049]) in the register (Fig. 5, #408), access to the memory cells (Fig. 5, #226); wherein the memory cells (Fig. 5, #226) are configured in a plurality of layers (Fig. 5, #516, #518, #520); and wherein the parameter (Fig. 5, #408, paragraph [0049]) is configured to identify a first subset of the layers (Fig. 5, #520) being programmed in the first mode (Fig. 5, #520, paragraph [0044], lines 1-5) and a second subset of the layers (Fig. 5, #518) being programmed in the second mode (Fig. 5, #516, #518 for example, where #516 stores the data of pre-layer instruction, and #518 writes the output data, paragraph [0051]-[0052]). 7. Regarding independent claim 19, Ng et al teaches an integrated circuit die having memory cells (Fig. 5, #226), each programmable (paragraph [0044], lines 1-15) in a first mode (Fig. 5, #520, paragraph [0044], lines 1-5) to perform operations of multiplication and accumulation (Fig. 5, #520, paragraph [0044], lines 1-5) and in a second mode (Fig. 5, #516, #518 for example, where #516 stores the data of pre-layer instruction, and #518 writes the output data, paragraph [0051]-[0052]) to store data (Fig. 5, paragraph [0044], lines 19-20); and a register (Fig. 5, #408) configured to store a parameter (Fig. 5, #408, paragraph [0049]) identifying, among a plurality of configurations (see paragraph [0049], lines 3-9), a current configuration of usages (Fig. 5, paragraph [0053]) of the memory cells (Fig. 5, #226) Allowable Subject Matter 8. Claims 3-12, 15-18, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 9. With respect to claim 3, there is no teaching, suggestion, or motivation for combination in the prior art to the first subset is configured to have each respective pair of layers in the first subset being separated by at least one layer not in the first subset. 10. With respect to dependent claims 4-12, since these claims are depending on claim 3, therefore claims 4-12 are allowable subject matter. 11. With respect to claim 15, there is no teaching, suggestion, or motivation for combination in the prior art to wherein the first subset is configured to have each respective pair of layers in the first subset being separated by at least one layer not in the first subset. 12. With respect to dependent claims 16-18, since these claims are depending on claim 15, therefore claims 16-18 are allowable subject matter. 13. With respect to claim 20, there is no teaching, suggestion, or motivation for combination in the prior art to wherein the first subset is configured to have each respective pair of layers in the first subset being separated by at least one layer not in the first subset. Conclusion 14. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure, Hoang et al (Pub. No.: US 2021/0406672). Hoang et al (Pub. No.: US 2021/0406672) shows memory system for performing compute in memory. 15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Han Yang whose telephone is (571) 270-3048. The examiner can normally be reached on Monday-Friday 8am-5pm with alternate Friday off. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. HY 10/12/2026 /HAN YANG/ Primary Examiner, Art Unit 2824