Prosecution Insights
Last updated: September 17, 2026
Application No. 18/944,777

Amplifier With Second Harmonic Termination

Non-Final OA §102§103
Filed
Nov 12, 2024
Priority
Nov 14, 2023 — NL 2036264
Examiner
POOS, JOHN W
Art Unit
Tech Center
Assignee
Ampleon Netherlands B V
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
1311 granted / 1402 resolved
+33.5% vs TC avg
Minimal +5% lift
Without
With
+4.6%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
27 currently pending
Career history
1421
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
30.8%
-9.2% vs TC avg
§102
54.5%
+14.5% vs TC avg
§112
5.3%
-34.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1402 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 6, 15, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (US 2021/0175866). In regard to Claim 1: Li discloses, in Figure 1, an amplifier (100) configured to amplify signals within a given operational frequency band f0 ± BW/2 that has a center frequency f0 and a bandwidth BW, (¶ 0017) wherein the amplifier includes a transistor (140) having an input terminal (142), and at least one resonance network (110, 190) arranged in between the input terminal (142) and ground (GND), wherein each resonance network comprises: a first inductor (116) arranged in between the input terminal (142) and an intermediate node (118); a first capacitor (114) arranged in between the intermediate node (118) and ground (GND); a series network (190) arranged in between the intermediate node (118) and ground (GND) that comprises a second inductor (192) and a second capacitor (196); wherein a susceptance presented by the at least one resonance network at the input terminal equals -BFET at a frequency f1 that lies in the operational frequency band, wherein BFET is the input susceptance of the transistor at the frequency f1; (¶ 0044) wherein, for the n - th resonance network among the at least one resonance network (110, 190): the series network (190) displays a series resonance at a frequency that is smaller than f1 (¶ 0061); an RF short is presented by the resonance network at the input terminal at a frequency 2 × f2n, wherein the frequency f2n lies in the operational frequency band (¶ 0047); wherein n represents an integer between 1 and N with N being the total number of resonance networks (n = 1 as 190 is a single resonance network). In regard to Claim 6: Li discloses, in Figure 6, the amplifier according to claim 1, comprising: a substrate (406, ¶ 0080); a semiconductor die on which the transistor is integrated (Figure 4: 440, 441), wherein the transistor comprises a first bond assembly (512, 516) that is electrically connected to the input terminal of the transistor (¶ 0099); wherein the first inductor of each resonance network is at least partially formed by one or more bondwires (512, 516) that are physically connected to the first bond assembly (¶ 0100). In regard to Claim 15: Li discloses, in Figure 1, the amplifier according to claim 1, wherein the transistor is a Gallium Nitride-based field-effect transistor, GaN FET, and wherein the input terminal of the transistor is a gate of the GaN FET (¶ 0026). In regard to Claim 20: Li discloses, in Figure 1, a Doherty amplifier, comprising: a Doherty splitter (Figure 3: 306) configured for splitting a signal (Figure 3: 302) to be amplified into a main signal (Figure 3: 308) and a peak signal (Figure 3: 309); a main amplifier (Figure 3: 340) configured to amplify the main signal (Figure 3: 308); a peak amplifier (Figure 3: 341) configured to amplify the peak signal (Figure 3: 309); and a Doherty combiner (Figure 3: 380) for combining the amplified main signal (Figure 3: 340 output) and the amplified peak signal (Figure 3: 341 output); wherein at least one of the main amplifier (Figure 3: 340) and peak amplifier (Figure 3: 341) comprise the amplifier configured to amplify signals within a given operational frequency band f0 ± BW/2 that has a center frequency f0 and a bandwidth, (¶ 0017), wherein the amplifier (¶ 0085) includes a transistor (140) having an input terminal (142), and at least one resonance network arranged in between the input terminal (142) and ground (GND), wherein each resonance network comprises: a first inductor (116) arranged in between the input terminal (142) and an intermediate node (118); a first capacitor (114) arranged in between the intermediate node (118) and ground (GND); a series network (190) arranged in between the intermediate node (118) and ground (GND) that comprises a second inductor (192) and a second capacitor (196); wherein a susceptance presented by the at least one resonance network at the input terminal equals -BFET at a frequency f1 that lies in the operational frequency band, wherein BFET is the input susceptance of the transistor at the frequency f1; (¶ 0044) wherein, for the n - th resonance network among the at least one resonance network (110, 190): the series network (190) displays a series resonance at a frequency that is smaller than f1 (¶ 0061); an RF short is presented by the resonance network at the input terminal at a frequency 2 × f2n, wherein the frequency f2n lies in the operational frequency band (¶ 0047); wherein n represents an integer between 1 and N with N being the total number of resonance networks (n = 2 as 310 and 311 each contain a resonance network). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 2-3 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2021/0175866). In regard to Claim 2: Li discloses the claimed invention as discussed with respect to Claim 1 above, except for wherein 0.8 < f2n/f1 < 1.2 or 0.9 < f2n /f1 < 1.1. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to have 0.8 < f2n/f1 < 1.2 or 0.9 < f2n /f1 < 1.1, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In regard to Claim 3: Li discloses the claimed invention as discussed with respect to Claims 1 and 2 above, except for wherein each resonance network is designed such that at a respective frequency f3n, the series network is inductive and resonates with the first capacitor, wherein 2 × f2n > f3n > f1. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to have each resonance network be designed such that at a respective frequency f3n, the series network is inductive and resonates with the first capacitor, wherein 2 × f2n > f3n > f1., since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). In regard to Claim 16: Li discloses the claimed invention as discussed with respect to Claim 1 above, except for wherein f0 lies in a range between 0.9 and 6.0 GHz, and wherein BW/f0 lies in a range between 0.01 and 0.15. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to have f0 lie in a range between 0.9 and 6.0 GHz, and wherein BW/f0 lie in a range between 0.01 and 0.15, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Allowable Subject Matter Claims 4-5 and 7-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. In regard to Claim 4: None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims: further comprising at least one biasing network for providing a biasing voltage to the input terminal of the transistor, wherein each respective biasing network is connected to a node in between the second inductor and the second capacitor of a respective resonance network. In regard to Claim 5: None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims: further comprising a driver transistor of which an output is connected to the input terminal of the transistor through an impedance matching network. In regard to Claim 7: None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims: further comprising a further die on which at least the first capacitor of each resonance network is arranged, wherein a first terminal of the first capacitor is electrically connected to a second bond assembly that is arranged on the further die, wherein another end of the one or more bondwires is physically connected to the second bond assembly, and wherein a second terminal of the first capacitor is configured to be grounded during operation. Claims 17-19 are allowed. In regard to Claim 17: None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims: wherein output terminals of the transistors of the first and second amplifiers are mutually shorted, and wherein the input terminals of the transistors of the first and second amplifiers are electrically connected to each other through a resistive connection. However, Li et al. (US 2021/0175866) discloses, in Figure 1, a first amplifier (Figure 3: 340) and second amplifier (Figure 3: 341); wherein both first amplifier (Figure 3: 340) and second amplifier (Figure 3: 341) comprise the amplifier configured to amplify signals within a given operational frequency band f0 ± BW/2 that has a center frequency f0 and a bandwidth, (¶ 0017), wherein the amplifier (¶ 0085) includes a transistor (140) having an input terminal (142), and at least one resonance network arranged in between the input terminal (142) and ground (GND), wherein each resonance network comprises: a first inductor (116) arranged in between the input terminal (142) and an intermediate node (118); a first capacitor (114) arranged in between the intermediate node (118) and ground (GND); a series network (190) arranged in between the intermediate node (118) and ground (GND) that comprises a second inductor (192) and a second capacitor (196); wherein a susceptance presented by the at least one resonance network at the input terminal equals -BFET at a frequency f1 that lies in the operational frequency band, wherein BFET is the input susceptance of the transistor at the frequency f1; (¶ 0044): wherein, for the n - th resonance network among the at least one resonance network (110, 190): the series network (190) displays a series resonance at a frequency that is smaller than f1 (¶ 0061); an RF short is presented by the resonance network at the input terminal at a frequency 2 × f2n, wherein the frequency f2n lies in the operational frequency band (¶ 0047); wherein n represents an integer between 1 and N with N being the total number of resonance networks (n = 2 as 310 and 311 each contain a resonance network). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chang et al. (US 2006/0001492) discloses a bandpass amplifier having gain and bandpass performance. The bandpass amplifier includes an input match unit for matching the gain of the amplifier and having a first filter response; a first bias unit electrically connected to the input match unit for driving the first terminal of the amplifier and having a first high pass filter response; a gain stage electrically connected to the first bias unit for providing the flat gain of the amplifier; a second bias unit electrically connected to the gain stage for driving the second terminal of the amplifier and having a second high pass filter response; and an output match unit electrically connected to the second bias unit for matching the gain of the amplifier and having a second filter response. Gorbachov et al. (US 2016/0336907) discloses a radio frequency (RF) power amplifier circuit includes an input and an output. A power amplifier transistor has a first terminal connected to the input, a second terminal connected to the output, and a third terminal defined by a degeneration inductance. A first capacitor is connected to the third terminal of the power amplifier transistor, along with a negative capacitance circuit connected in series with the first capacitor. Chidurala et al. (US 2021/0399692) discloses an electronic package houses one or more RF amplifier circuits. At least one of an input or output impedance matching network integrated on the package and electrically coupled to the gate or drain bias voltage connection, respectively, of an amplifier circuit, includes a multi-stage decoupling network. Each multi-stage decoupling network includes two or more decoupling stages. Each decoupling stage of the multi-stage decoupling network includes a resistance, inductance, and capacitance, and is configured to reduce impedance seen by the amplifier circuit at a different frequency below an operating band of the amplifier circuit. Bias voltage connections to the impedance matching circuits may be shared, and may be connected anywhere along the multi-stage decoupling network. Holmes et al. (US 2022/0085772) discloses a packaged RF amplifier device includes input and output leads and a transistor die. The transistor die includes a transistor with a drain-source capacitance below 0.1 picofarads per watt. The device also includes a conductive connection between the transistor output terminal and the output lead, and a baseband termination circuit between the transistor output terminal and a ground reference node. The baseband termination circuit presents a low impedance to signal energy at envelope frequencies and a high impedance to signal energy at RF frequencies. Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOHN W POOS/Primary Examiner, Art Unit 2843
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Prosecution Timeline

Nov 12, 2024
Application Filed
Sep 09, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
98%
With Interview (+4.6%)
1y 10m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1402 resolved cases by this examiner. Grant probability derived from career allowance rate.

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