Prosecution Insights
Last updated: October 22, 2026
Application No. 18/944,884

INTEGRATED CIRCUIT ARRANGEMENT SUPPORTING AGGREGATED TRANSDUCERS

Non-Final OA §102§103
Filed
Nov 12, 2024
Priority
Jul 29, 2022 — provisional 63/393,343 +2 more
Examiner
MEI, XU
Art Unit
2695
Tech Center
2600 — Communications
Assignee
Cirrus Logic International Semiconductor Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
1y 3m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
726 granted / 850 resolved
+23.4% vs TC avg
Moderate +6% lift
Without
With
+6.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
17 currently pending
Career history
869
Total Applications
across all art units

Statute-Specific Performance

§101
5.7%
-34.3% vs TC avg
§103
40.2%
+0.2% vs TC avg
§102
26.9%
-13.1% vs TC avg
§112
17.4%
-22.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 850 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of Application This communication is responsive to the applicant's preliminary amendment filed 11/12/2024. Claims 36-56 are pending. Claims 1-35 have been cancelled. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 36-39, 41-49; and 50-56 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Price et al (US-2020/0034109, hereinafter, Price). Regarding claim 36, Price discloses an apparatus comprising an audio system (Figs. 1, 3, 5), the audio system comprising one or more audio output transducers (38, 10 60, 72) of a first type (subwoofer or mid and high speaker) and one or more audio output transducers of a second type (subwoofer or mid and high speaker, see para [0027]), the audio system comprising: a host processor integrated circuit (signal processor 14); a first audio amplifier (32) integrated circuit configured to drive at least one of the one or more audio output transducers (38) of the first type; and an audio codec integrated circuit (50) configured to drive the one or more audio output transducers of the second type (60, 72); wherein the first audio amplifier integrated circuit is configured to: receive a first audio input signal from the host processor integrated circuit; split said first audio input signal into first and second component signals in respective first and second frequency bands (see para [0026]); drive at least a first one of the one or more audio output transducers of the first type using the first component signal (low frequencies signal); and transmit the second component signal to the audio codec integrated circuit (50); and wherein the audio codec integrated circuit is configured to: receive the second component signal and drive at least a first one of the one or more audio output transducers of the second type using the second component signal (mid and high frequencies signals). Regarding claims 37-39, see Figs. 1, 3, and para [0026], [0027], [0039]. Regarding claims 41-42, see Figs. 1, 3, 5, and para [0025], [0028], [0034], [0035], [0030], and [0043]. Regarding claims 45-47, see Bluetooth transmitter 18, Fig. 3, para [0027], [0039]-[0041]. Regarding claims 48-49, see Fig. 1, microphone 24, and para [0028], [0052]. Regarding claim 50, Price discloses an apparatus (Figs. 1, 3, 5) comprising an audio system, the audio system comprising: a host processor integrated circuit (10); a first integrated circuit of a first type being configured to drive at least a first audio output transducer (38); and a second integrated circuit of a second type, the second integrated circuit (IC of 50) being configured to drive at least a second audio output transducer (60, 72); wherein the first integrated circuit comprises a first interface (22) connected to the host processor integrated circuit and a second interface (18) connected to the second integrated circuit (50) and is configured to: receive a first audio input signal (16) from the host processor integrated circuit via the first interface (23); drive the at least a first audio output transducer based on at least part of the respective first audio input signal (36); and transmit at least part of the first audio input signal to the second integrated circuit via the second interface as a forwarded audio signal (20, 49); and wherein the second integrated circuit is configured to: receive the forwarded audio signal from the first integrated circuit; and drive the at least a second audio output transducer (60, 72) using the forwarded audio signal (see Figs. 3, 5, and para [0039], [0043]). Regarding claim 51, see Fig. 1, audio amplifier 32, and audio codec for second IC of mobile phone 50 for receiving audio signal. Regarding claims 52-53, see Figs. 1, 3, 5, and para [0026], [0027], [0039], [0043]. Regarding claim 54, see microphone 24, and para [0028], [0052]. Regarding claim 55, Price discloses an audio amplifier integrated circuit (see Figs. 1, 3, 5) comprising: at least one output node for driving at least a first audio output transducer (38); a first interface (12) configured to connect to an external host processor integrated circuit (50); a second interface (18) configured to connect to an external audio driver circuit (see para [0034]); wherein the audio amplifier integrated circuit is configured to: receive an audio input signal (16) from the external host processor integrated circuit via the first interface (12); split the audio input signal into a first component signal in a first frequency band and a second component signal in a second frequency band (see para [0027]); drive the at least a first audio output transducer (28) based on the first component signal (36); and transmit the second component signal (20) to the external audio driver circuit via the second interface (18). Regarding claim 56, Price discloses an audio codec integrated circuit (see Figs. 1, 3, 5) comprising: first and second output nodes for driving first and second audio output transducers (38, 82, 87) with respective drive signals in a first frequency band (subwoofer low frequency); a first interface (12) configured to connect to an external host processor integrated circuit (14); one or more second interfaces (80, 85) configured to connect, respectively, to one or more external audio amplifier integrated circuits (22); and wherein the audio codec integrated circuit is configured to receive audio data (36, audio data to 80 and 85) in said first frequency band (subwoofer low frequency) from the one or more external audio amplifier integrated circuits (22) via the one or more second interfaces (80, 85) and to drive the first and second audio output transducers based on the received audio data (see [0027], [0034], [0035]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Price in view of Kotera (US-2017/0229138). Regarding claim 40, Price discloses the audio system with each of the first and second audio amplifier integrated circuit discussed in claim 37 above. However, Price does not disclose is configured to transmit an echo cancellation signal to the host processor IC. Kotera discloses an echo canceller is configured to transmit an echo cancellation signal to an external processor (see Figs. 1, 2, and para [0023]-[0024]) for removing echo in a communication system (see para [0009]). It would have been obvious to one of ordinary skill in the art before the effect filing date of the claimed invention to modify the first integrated circuit or the arrangement of Price with an echo canceller that is configured to transmit an echo cancellation signal, as taught by Kotera, to the host processor IC in order to removing echo presented in the communication system of Price. Allowable Subject Matter Claims 43-44 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Issued patent(s) 12,652,493 of parent application(s) 18/210,790 is/ are made of record here as pertinent art to the claimed invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to XU MEI whose telephone number is (571)272-7523. The examiner can normally be reached on Monday-Friday 10-6:30 est. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Vivian Chin can be reached on 571-272-7848. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /XU MEI/ Primary Examiner, Art Unit 2695 09/03/2026
Read full office action

Prosecution Timeline

Nov 12, 2024
Application Filed
Sep 08, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
91%
With Interview (+6.0%)
3y 3m (~1y 3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 850 resolved cases by this examiner. Grant probability derived from career allowance rate.

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