DETAILED ACTION
This office action is responsive to application 18/944,915 filed on November 12, 2024. Claims 1-25 are pending in the application and have been examined by the Examiner.
Information Disclosure Statement
The Information Disclosure Statement (IDS) filed on May 13, 2025 was received and has been considered by the Examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 4, 6, 13, 15, 17, 18, 23 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Takamiya et al. (US 2012/0119063) in view of Liu et al. (US 10,764,526).
Consider claim 1, Takamiya et al. teaches:
A circuit (see figure 4), the circuit comprising:
a plurality of signal lines (vertical signal lines, VSL, paragraph 0094);
a plurality of input portions respectively connected to the plurality of signal lines (The Examiner interprets the portions of the vertical signal lines (VSL) coupled to the pixel array unit (1) in figure 4 to be the plurality of input portions.), and each configured to receive a signal from an outside of the circuit (i.e. to receive a signal from the pixel array unit (1), paragraph 0094, see figure 4);
a plurality of signal processing circuits (e.g. comprising comparators (5) and counters (6), paragraph 0095) respectively connected to the plurality of input portions via the plurality of signal lines (VSL, see figure 4, paragraph 0095); and
a plurality of transistors (dummy pixels, 2, selection transistors, 3, paragraphs 0095 and 0097) configured to supply a predetermined voltage (i.e. a test voltage, Vt) to the plurality of signal lines (VSL, see paragraphs 0097-0100) in a state where no signal is input to the plurality of input portions from the outside (As shown in figure 4, the transistors (2, 3) are always configured to supply the test voltage (Vt) to the vertical signal lines (VSL), including in a state where no signal is input to the plurality of input portions from the pixels array unit (1).), wherein
a part (2) of the plurality of transistors (2, 3) is connected to a first control line (i.e. to receive a “control voltage” from the test voltage switching circuit (11), figure 4, paragraph 0097), and another part (3) of the plurality of transistors (2, 3) is connected to a second control line different from the first control line (i.e. to receive a “dummy selecting signal”, figure 4, paragraph 0099),
wherein a number of all transistors connected to the first control line is smaller than a number of the plurality of transistors (As shown in figure 4, there are four transistors (2) connected to the first control line and eight transistors (2, 3) in total.), and
wherein a number of all transistors connected to the second control line is smaller than a number of the plurality of transistors (As shown in figure 4, there are four transistors (3) connected to the second control line and eight transistors (2, 3) in total.).
Takamiya et al. teaches that an analog circuit and a logic circuit can be manufactured inside a same chip (see paragraph 0002).
However, Takamiya et al. does not explicitly teach that the circuit is comprised in a circuit substrate to be laminated on another substrate.
Liu et al. similarly teaches a circuit (figure 3) including vertical signal lines coupling an outside pixel array (i.e. containing pixel blocks 310A-310I) to ADCs (350A-350C, see column 5, lines 41-48, column 6, lines 4-23). Liu et al. likewise teaches (see figure 5) that the circuit includes a predetermined voltage (reference voltage, 515) selectively applied to signal processing circuitry (340, 350) via a transistor (reference voltage switch, 534, see column 6, lines 41-52).
However, Liu et al. additionally teaches that the circuit is comprised in a circuit substrate to be laminated on another substrate (As shown in figure 7, and detailed in column 11, lines 40-50, switches, amplifiers, ADCs and a reference voltage source are provided in a second substrate (740). The second substrate (740) is laminated on a first substrate (710), figure 7, column 10, lines 42-49.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to implement the circuit taught by Takamiya et al. in a circuit substrate that is to be laminated on another substrate as taught by Liu et al. for the benefit of reducing an area occupied by components in the another substrate and increasing fill factor (Liu et al., column 11, lines 44-50).
Consider claim 2, and as applied to claim 1 above, Takamiya et al. further teaches that each of the plurality of signal processing circuits includes an analog-to-digital (AD) conversion unit configured to convert the predetermined voltage supplied from a corresponding one of the plurality of transistors into a digital signal (e.g. comprising comparators (5) and counters (6), paragraph 0095).
Consider claim 4, and as applied to claim 2 above, Takamiya et al. further teaches a circuit (calculation circuit, 25) configured to compare the digital signal with an expected value (i.e. to calculate a linearity error, as detailed in paragraph 0124).
Consider claim 6, and as applied to claim 1 above, Takamiya et al. further teaches that a power supply voltage (source voltage, AVD) is supplied to one of main nodes of each of the plurality of transistors (2, 3, see figure 4, paragraph 0097), and the plurality of transistors (2, 3) serves as switches configured to switch between supplying and not supplying, to the plurality of signal lines (VSL), the predetermined voltage (Vt) based on the power supply voltage (AVD, see paragraphs 0097-0100).
Consider claim 13, and as applied to claim 1 above, Takamiya et al. further teaches that signals output from a plurality of pixels each including a photoelectric conversion unit are input to the plurality of input portions (i.e. in pixel array unit, 101, paragraph 0094), the plurality of pixels being arranged in a plurality of rows and a plurality of columns (i.e. in a “matrix pattern”, paragraph 0094), and wherein at least two of the plurality of input portions are provided corresponding to pixels in one of the plurality of columns (“the present disclosure can be applied to a solid-state imaging device having a configuration in which one vertical signal line VSL is shared by a plurality of pixel rows”, paragraph 0281).
Takamiya et al. does not explicitly teach that the plurality of pixels are arranged on the other substrate.
Liu et al. teaches that the plurality of pixels are arranged on the other substrate (See “photodiode” (714) and first substrate (710) in figure 7).
Consider claim 15, and as applied to claim 1 above, Takamiya et al. does not explicitly teach the two substrates.
Liu et al. teaches that the circuit substrate is manufactured by a manufacturing apparatus different from a manufacturing apparatus for the other substrate (i.e. such that the manufactured circuit substrate is different from the manufactured other substrate, column 10, lines 42-49, column 11, lines 40-50).
Consider claim 17, Takamiya et al. teaches a semiconductor apparatus (solid-state imaging device, paragraph 0001) comprising the circuit according to claim 1 (see claim 1 rationale).
The combination of Takamiya et al. and Liu et al. teaches the circuit substrate of claim 1, wherein the circuit substrate and the other substrate are laminated (see claim 1 rationale).
Consider claim 18, the combination of Takamiya et al. and Liu et al. teaches the semiconductor apparatus according to claim 17 (see claim 17 rationale).
Takamiya et al. teaches equipment comprising at least one of a control apparatus (logic circuit, 8, figures 4 and 5) configured to control the semiconductor apparatus (“The logic circuit 8 is a control device that controls the overall operation of the solid-state imaging device 100 and a calculation processing device.” paragraph 0107).
Consider claim 23, Takamiya et al. teaches:
A method for driving a circuit, wherein the circuit (see figure 4) includes:
a plurality of signal lines (vertical signal lines, VSL, paragraph 0094);
a plurality of input portions respectively connected to the plurality of signal lines (The Examiner interprets the portions of the vertical signal lines (VSL) coupled to the pixel array unit (1) in figure 4 to be the plurality of input portions.), and each configured to receive a signal from an outside of the circuit (i.e. to receive a signal from the pixel array unit (1), paragraph 0094, see figure 4);
a plurality of signal processing circuits (e.g. comprising comparators (5) and counters (6), paragraph 0095) respectively connected to the plurality of input portions via the plurality of signal lines (VSL, see figure 4, paragraph 0095); and
a plurality of transistors (dummy pixels, 2, selection transistors, 3, paragraphs 0095 and 0097) wherein a part (2) of the plurality of transistors (2, 3) is connected to a first control line (i.e. to receive a “control voltage” from the test voltage switching circuit (11), figure 4, paragraph 0097), and another part (3) of the plurality of transistors (2, 3) is connected to a second control line different from the first control line (i.e. to receive a “dummy selecting signal”, figure 4, paragraph 0099),
wherein a number of all transistors connected to the first control line is smaller than a number of the plurality of transistors (As shown in figure 4, there are four transistors (2) connected to the first control line and eight transistors (2, 3) in total.), and
wherein a number of all transistors connected to the second control line is smaller than a number of the plurality of transistors (As shown in figure 4, there are four transistors (3) connected to the second control line and eight transistors (2, 3) in total.), and
wherein the method comprising supplying, by the plurality of transistors (2, 3), a predetermined voltage (i.e. a test voltage, Vt) to the plurality of signal lines (VSL, see paragraphs 0097-0100) in a state where no signal is input to the plurality of input portions from the outside (As shown in figure 4, the transistors (2, 3) are always configured to supply the test voltage (Vt) to the vertical signal lines (VSL), including in a state where no signal is input to the plurality of input portions from the pixels array unit (1). As detailed in paragraph 0104, a signal from a pixel “or” a signal from a dummy pixel (2) is output to the vertical signal lines (VSL). See also paragraphs 0113 and 0114.).
Takamiya et al. teaches that an analog circuit and a logic circuit can be manufactured inside a same chip (see paragraph 0002).
However, Takamiya et al. does not explicitly teach that the circuit is comprised in a circuit substrate to be laminated on another substrate.
Liu et al. similarly teaches a circuit (figure 3) including vertical signal lines coupling an outside pixel array (i.e. containing pixel blocks 310A-310I) to ADCs (350A-350C, see column 5, lines 41-48, column 6, lines 4-23). Liu et al. likewise teaches (see figure 5) that the circuit includes a predetermined voltage (reference voltage, 515) selectively applied to signal processing circuitry (340, 350) via a transistor (reference voltage switch, 534, see column 6, lines 41-52).
However, Liu et al. additionally teaches that the circuit is comprised in a circuit substrate to be laminated on another substrate (As shown in figure 7, and detailed in column 11, lines 40-50, switches, amplifiers, ADCs and a reference voltage source are provided in a second substrate (740). The second substrate (740) is laminated on a first substrate (710), figure 7, column 10, lines 42-49.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to implement the circuit taught by Takamiya et al. in a circuit substrate that is to be laminated on another substrate as taught by Liu et al. for the benefit of reducing an area occupied by components in the another substrate and increasing fill factor (Liu et al., column 11, lines 44-50.).
Consider claim 24, and as applied to claim 23 above, Takamiya et al. further teaches that the circuit substrate is evaluated based on a signal obtained by processing the predetermined voltage (Vt) in each of the plurality of signal processing circuits (The circuit substrate is evaluated by detecting a collapse of a waveform of a reference voltage RAMP by a logic circuit (8), as detailed in paragraphs 0107 and 0108. The evaluation is based on a signal obtained by processing the predetermined voltage in each of the plurality of signal processing circuits (5, 6), as detailed in paragraphs 0104-0106.).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Takamiya et al. (US 2012/0119063) in view of Liu et al. (US 10,764,526) and Suto (US 2022/0094907).
Consider claim 25, Takamiya et al. teaches:
A method for manufacturing a semiconductor apparatus (solid-state imaging device, paragraph 0001) including a circuit (see figure 4), wherein the circuit includes:
a plurality of signal lines (vertical signal lines, VSL, paragraph 0094);
a plurality of input portions respectively connected to the plurality of signal lines (The Examiner interprets the portions of the vertical signal lines (VSL) coupled to the pixel array unit (1) in figure 4 to be the plurality of input portions.), and each configured to receive a signal from an outside of the circuit (i.e. to receive a signal from the pixel array unit (1), paragraph 0094, see figure 4);
a plurality of signal processing circuits (e.g. comprising comparators (5) and counters (6), paragraph 0095) respectively connected to the plurality of input portions via the plurality of signal lines (VSL, see figure 4, paragraph 0095); and
a plurality of transistors (dummy pixels, 2, selection transistors, 3, paragraphs 0095 and 0097) wherein a part (2) of the plurality of transistors (2, 3) is connected to a first control line (i.e. to receive a “control voltage” from the test voltage switching circuit (11), figure 4, paragraph 0097), and another part (3) of the plurality of transistors (2, 3) is connected to a second control line different from the first control line (i.e. to receive a “dummy selecting signal”, figure 4, paragraph 0099);
wherein a number of all transistors connected to the first control line is smaller than a number of the plurality of transistors (As shown in figure 4, there are four transistors (2) connected to the first control line and eight transistors (2, 3) in total.), and
wherein a number of all transistors connected to the second control line is smaller than a number of the plurality of transistors (As shown in figure 4, there are four transistors (3) connected to the second control line and eight transistors (2, 3) in total.)
and the method comprising:
supplying, by the plurality of transistors (2, 3), a predetermined voltage (i.e. a test voltage, Vt) to the plurality of signal lines (VSL, see paragraphs 0097-0100) in a state where no signal is input to the plurality of input portions from the outside (As shown in figure 4, the transistors (2, 3) are always configured to supply the test voltage (Vt) to the vertical signal lines (VSL), including in a state where no signal is input to the plurality of input portions from the pixels array unit (1). As detailed in paragraph 0104, a signal from a pixel “or” a signal from a dummy pixel (2) is output to the vertical signal lines (VSL). See also paragraphs 0113 and 0114.), and
processing, using the plurality of signal processing circuits (5, 6), the predetermined voltage (Vt, see paragraphs 0104-0106).
Takamiya et al. teaches that an analog circuit and a logic circuit can be manufactured inside a same chip (see paragraph 0002).
However, Takamiya et al. does not explicitly teach that the circuit is comprised in a circuit substrate to be laminated on another substrate.
Liu et al. similarly teaches a circuit (figure 3) including vertical signal lines coupling an outside pixel array (i.e. containing pixel blocks 310A-310I) to ADCs (350A-350C, see column 5, lines 41-48, column 6, lines 4-23). Liu et al. likewise teaches (see figure 5) that the circuit includes a predetermined voltage (reference voltage, 515) selectively applied to signal processing circuitry (340, 350) via a transistor (reference voltage switch, 534, see column 6, lines 41-52).
However, Liu et al. additionally teaches that the circuit is comprised in a circuit substrate to be laminated on another substrate (As shown in figure 7, and detailed in column 11, lines 40-50, switches, amplifiers, ADCs and a reference voltage source are provided in a second substrate (740). The second substrate (740) is laminated on a first substrate (710), figure 7, column 10, lines 42-49.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to implement the circuit taught by Takamiya et al. in a circuit substrate that is to be laminated on another substrate as taught by Liu et al. for the benefit of reducing an area occupied by components in the another substrate and increasing fill factor (Liu et al., column 11, lines 44-50.).
However, the combination of Takamiya et al. and Liu et al. does not explicitly teach laminating the circuit substrate and the other substrate after the processing.
Suto similarly teaches an imaging device (figure 1) including a circuit substrate (second semiconductor chip, 12, paragraphs 0076 and 0077) laminated to another substrate (first semiconductor chip, 11, see figure 1, paragraph 0076).
However, Suto additionally teaches laminating the circuit substrate and the other substrate after the processing (“In addition, although the imaging device according to the present disclosure has a stacked chip structure, and the operation is not completed unless the pixel chip (first semiconductor chip 11) and the circuit chip (second semiconductor chip 12) are bonded together, the failure detection (BIST) can be completed only in the circuit chip, and thus, it is possible to sort out defective chips before bonding.” Paragraph 0159).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the laminating of the circuit substrate and the other substrate taught by the combination of Takamiya et al. and Liu et al. be performed after the processing as taught by Suto for the benefit of making it possible to sort out defective chips before bonding which enables the yield to be improved whereby the cost of the imaging device is reduced (Suto, paragraph 0159).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Takamiya et al. (US 2012/0119063) in view of Liu et al. (US 10,764,526), as applied to claim 2 above, and further in view of Shimizu et al. (US 2020/0059620).
Consider claim 3, and as applied to claim 2 above, the combination of Takamiya et al. and Liu et al. does not explicitly teach that the digital signal generated by each of the plurality of signal processing circuits is output to the outside of the circuit substrate.
Shimizu et al. similarly teaches an imaging device (figure 1) with a substate (second semiconductor substrate, 20) including an ADC (AD converter, 22, paragraph 0084).
However, Shimizu et al. additionally teaches that the digital signal generated by the ADC (22) is output to the outside of the circuit substrate (20, i.e. via the output buffer (26), paragraph 0126).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the digital signal generated by each of the plurality of signal processing circuits taught by the combination of Takamiya et al. and Liu et al. be output to the outside of the circuit substrate as taught by Shimizu et al. for the benefit that the output image data may be used by external devices (Shimizu et al., paragraph 0126).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Takamiya et al. (US 2012/0119063) in view of Liu et al. (US 10,764,526), as applied to claim 4 above, and further in view of Suto (US 2022/0094907).
Consider claim 5, and as applied to claim 4 above, the combination of Takamiya et al. and Liu et al. does not explicitly teach that the circuit outputs, to the outside of the circuit substrate, a signal indicating that a difference between the digital signal and the expected value is detected as being greater than a predetermined amount.
Suto similarly teaches an imaging device (figure 1) including a circuit substrate (12, paragraphs 0076 and 0077), wherein the circuit substrate (12) includes an expected value detection unit (48, paragraphs 0082 and 0083).
However, Suto additionally teaches that the circuit outputs, to the outside of the circuit substrate (12), a signal indicating that a difference between the digital signal and the expected value is detected as being greater than a predetermined amount (“The expected value comparison unit 48 having the above configuration compares the BIST output value [11:0] of the failure detection circuit with the expected value [11:0], and outputs the comparison result as an assessment result of non-defective product/defective product based on the failure detection.” paragraph 0144).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the circuit taught by the combination of Takamiya et al. and Liu et al. output a signal indicating that a difference between the digital signal and the expected value is detected as being greater than a predetermined amount as taught by Suto for the benefit of making it possible to sort out defective chips before bonding which enables the yield to be improved whereby the cost of the imaging device is reduced (Suto, paragraph 0159).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Takamiya et al. (US 2012/0119063) in view of Liu et al. (US 10,764,526), as applied to claim 1 above, and further in view of Shishido (US 2020/0366860).
Consider claim 7, and as applied to claim 1 above, Takamiya et al. additionally teaches that each of the transistors (2, 3) is configured to perform a source follower operation (see figure 4).
However, the combination of Takamiya et al. and Liu et al. does not explicitly teach a plurality of current sources respectively connected to the plurality of signal lines.
Shishido similarly teaches an imaging device (figures 1 and 4) with a circuit substrate (second substrate, 102, figure 4) having a plurality of signal lines (314, figures 1 and 4, paragraphs 0135 and 0142).
However, Shishido additionally teaches a plurality of current sources (constant current sources, 433, 434) respectively connected to the plurality of signal lines (314, see figure 4).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of signal lines taught by the combination of Takamiya et al. and Liu et al. be respectively connected to a plurality of current sources as taught by Shishido for the benefit of enhancing the degree of freedom of an element layout (Shishido, paragraph 0006).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Takamiya et al. (US 2012/0119063) in view of Liu et al. (US 10,764,526), as applied to claim 1 above, and further in view of Shinohara (US 2020/0091205).
Consider claim 14, and as applied to claim 1 above, the combination of Takamiya et al. and Liu et al. does not explicitly teach that each of the plurality of signal processing circuits includes a waveform shaping circuit and a counter that are configured to process a signal output from an avalanche photodiode provided on the other substrate.
Shinohara similarly teaches a laminated imaging device (figure 5) comprising first and second substrates (100, 110, paragraph 0066), wherein signal processing circuit is located on the second substrate (110, see figure 7, paragraphs 0066 and 0070).
However, Shinohara additionally teaches that each of the plurality of signal processing circuits (see figure 7) includes a waveform shaping circuit (“an inverter circuit 7 functioning as a wave shaping unit”, paragraph 0070) and a counter (counter circuit, 8) that are configured to process a signal output from an avalanche photodiode (“The P-type semiconductor region 2, the N-type semiconductor region 3, and the N-type semiconductor region 12 constitute an avalanche diode (AD).” See figure 7) provided on the other substrate (“a substrate 100 including the plurality of photoelectric conversion units 70”, paragraph 0066).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have each of the plurality of signal processing circuits taught by the combination of Takamiya et al. and Liu et al. include a waveform shaping circuit and a counter as taught by Shinohara as this only involves combining prior art elements according to known methods to yield predictable results such as enabling photon counting (Shinohara, paragraph 0002).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 9, 12, 16, 19, 20, 21 and 22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 12, 13, 14, 23, 25 and 26 of U.S. Patent No. 12,167,156. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 9, 12, 16, 19, 20, 21 and 22 are anticipated by claims 1, 12, 13, 14, 23, 25 and 26 of US 12,167,156 as follows:
Consider claim 9, claim 1 of US 12,167,156 teaches (in parentheses):
A circuit substrate to be laminated on another substrate, the circuit substrate comprising: (circuit substrate to be laminated on another substrate, the circuit substrate comprising:)
a plurality of signal lines (a plurality of signal lines);
a plurality of input portions respectively connected to the plurality of signal lines, and each configured to receive a signal from an outside of the circuit substrate (a plurality of input portions respectively connected to the plurality of signal lines, and each configured to receive a signal from an outside of the circuit substrate);
a plurality of signal processing circuits respectively connected to the plurality of input portions via the plurality of signal lines (a plurality of signal processing circuits respectively connected to the plurality of input portions via the plurality of signal lines); and
a plurality of transistors configured to supply a predetermined voltage to the plurality of signal lines in a state where no signal is input to the plurality of input portions from the outside (a plurality of transistors configured to supply a predetermined voltage to the plurality of signal lines in a state where no signal is input to the plurality of input portions from the outside),
a plurality of current sources respectively connected to the plurality of signal lines (a plurality of current sources respectively connected to the plurality of signal lines); and
a plurality of second transistors each configured to switch a conductive state and a non-conductive state of an electrical path between a corresponding one of the plurality of input portions and a corresponding one of the plurality of signal processing circuits (a plurality of second transistors each configured to switch a conductive state and a non-conductive state of an electrical path between a corresponding one of the plurality of input portions and a corresponding one of the plurality of signal processing circuits),
the plurality of second transistors being respectively connected to the plurality of signals lines, wherein one node of each of the plurality of second transistors is connected to a corresponding one of the plurality of transistors and a corresponding one of the plurality of current sources, and wherein another node of each of the plurality of second transistors is connected to the corresponding one of the plurality of signal processing circuits (the plurality of second transistors being respectively connected to the plurality of signals lines, wherein a part of the plurality of transistors is connected to a first control line, and another part of the plurality of transistors is connected to a second control line different from the first control line, wherein one node of each of the plurality of second transistors is connected to a corresponding one of the plurality of transistors and a corresponding one of the plurality of current sources, and wherein another node of each of the plurality of second transistors is connected to the corresponding one of the plurality of signal processing circuits).
Consider claim 19, claim 12 of US 12,167,156 teaches (in parentheses):
A semiconductor apparatus comprising: the circuit substrate according to claim 9, wherein the circuit substrate and the other substrate are laminated (A semiconductor apparatus comprising: the circuit substrate according to claim 1, wherein the circuit substrate and the other substrate are laminated).
Consider claim 20, claim 13 of US 12,167,156 teaches (in parentheses):
Equipment comprising: the semiconductor apparatus according to claim 19, wherein the equipment further comprises at least one of: an optical apparatus corresponding to the semiconductor apparatus; a control apparatus configured to control the semiconductor apparatus; a processing apparatus configured to process a signal output from the semiconductor apparatus; a display apparatus configured to display information obtained by the semiconductor apparatus; a storage apparatus configured to store the information obtained by the semiconductor apparatus; or a mechanical apparatus configured to operate based on the information obtained by the semiconductor apparatus (Equipment comprising: the semiconductor apparatus according to claim 12, wherein the equipment further comprises at least one of: an optical apparatus corresponding to the semiconductor apparatus; a control apparatus configured to control the semiconductor apparatus; a processing apparatus configured to process a signal output from the semiconductor apparatus; a display apparatus configured to display information obtained by the semiconductor apparatus; a storage apparatus configured to store the information obtained by the semiconductor apparatus; or a mechanical apparatus configured to operate based on the information obtained by the semiconductor apparatus).
Consider claim 12, claim 14 of US 12,167,156 teaches (in parentheses):
A circuit substrate to be laminated on another substrate, the circuit substrate comprising: (A circuit substrate to be laminated on another substrate, the circuit substrate comprising:)
a plurality of signal lines (a plurality of signal lines);
a plurality of input portions respectively connected to the plurality of signal lines, and each configured to receive a signal from an outside of the circuit substrate (a plurality of input portions respectively connected to the plurality of signal lines, and each configured to receive a signal from an outside of the circuit substrate);
a plurality of signal processing circuits respectively connected to the plurality of input portions via the plurality of signal lines (a plurality of signal processing circuits respectively connected to the plurality of input portions via the plurality of signal lines);
a plurality of transistors configured to supply a predetermined voltage to the plurality of signal lines in a state where no signal is input to the plurality of input portions from the outside (a plurality of transistors configured to supply a predetermined voltage to the plurality of signal lines in a state where no signal is input to the plurality of input portions from the outside), and
a plurality of third transistors respectively connected to the plurality of signal lines, and each configured to switch between supplying and not supplying a second voltage different from the predetermined voltage, wherein each of the plurality of transistors is a transistor of a first conductivity type, and wherein each of the plurality of third transistors is a transistor of a second conductivity type different from the first conductivity type (a plurality of third transistors respectively connected to the plurality of signal lines, and each configured to switch between supplying and not supplying a second voltage different from the predetermined voltage, wherein a part of the plurality of transistors is connected to a first control line, and another part of the plurality of transistors is connected to a second control line different from the first control line, wherein each of the plurality of transistors is a transistor of a first conductivity type, and wherein each of the plurality of third transistors is a transistor of a second conductivity type different from the first conductivity type).
Consider claim 16, claim 23 of US 12,167,156 teaches (in parentheses):
the circuit substrate is manufactured by the manufacturing apparatus with a finer process rule than a process rule of the manufacturing apparatus for the other substrate (the circuit substrate is manufactured by a manufacturing apparatus different from a manufacturing apparatus for the other substrate).
Consider claim 21, claim 25 of US 12,167,156 teaches (in parentheses):
A semiconductor apparatus comprising: the circuit substrate according to claim 12, wherein the circuit substrate and the other substrate are laminated (A semiconductor apparatus comprising: the circuit substrate according to claim 14, wherein the circuit substrate and the other substrate are laminated).
Consider claim 22, claim 26 of US 12,167,156 teaches (in parentheses):
Equipment comprising: the semiconductor apparatus according to claim 21, wherein the equipment further comprises at least one of: an optical apparatus corresponding to the semiconductor apparatus; a control apparatus configured to control the semiconductor apparatus; a processing apparatus configured to process a signal output from the semiconductor apparatus; a display apparatus configured to display information obtained by the semiconductor apparatus; a storage apparatus configured to store the information obtained by the semiconductor apparatus; or a mechanical apparatus configured to operate based on the information obtained by the semiconductor apparatus (Equipment comprising: the semiconductor apparatus according to claim 25, wherein the equipment further comprises at least one of: an optical apparatus corresponding to the semiconductor apparatus; a control apparatus configured to control the semiconductor apparatus; a processing apparatus configured to process a signal output from the semiconductor apparatus; a display apparatus configured to display information obtained by the semiconductor apparatus; a storage apparatus configured to store the information obtained by the semiconductor apparatus; or a mechanical apparatus configured to operate based on the information obtained by the semiconductor apparatus).
Claims 1-8, 10, 11, 13-15, 17 and 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7, 8-10 and 12-14 of U.S. Patent No. 12,167,156 in view of Takamiya et al. (US 2012/0119063).
Consider claim 1, claim 1 of US 12,167,156 teaches (in parentheses):
A circuit substrate to be laminated on another substrate, the circuit substrate comprising: (A circuit substrate to be laminated on another substrate, the circuit substrate comprising:)
a plurality of signal lines; (a plurality of signal lines)
a plurality of input portions respectively connected to the plurality of signal lines, and each configured to receive a signal from an outside of the circuit substrate; (a plurality of input portions respectively connected to the plurality of signal lines, and each configured to receive a signal from an outside of the circuit substrate)
a plurality of signal processing circuits respectively connected to the plurality of input portions via the plurality of signal lines (a plurality of signal processing circuits respectively connected to the plurality of input portions via the plurality of signal lines); and
a plurality of transistors configured to supply a predetermined voltage to the plurality of signal lines in a state where no signal is input to the plurality of input portions from the outside (a plurality of transistors configured to supply a predetermined voltage to the plurality of signal lines in a state where no signal is input to the plurality of input portions from the outside);
wherein part of the plurality of transistors is connected to a first control line, and another part of the plurality of transistors is connected to a second control line different from the first control line (a part of the plurality of transistors is connected to a first control line, and another part of the plurality of transistors is connected to a second control line different from the first control line).
Claim 1 of US 12,167,156 does not explicitly teach wherein a number of all transistors connected to the first control line is smaller than a number of the plurality of transistors, and wherein a number of all transistors connected to the second control line is smaller than a number of the plurality of transistors.
Takamiya et al. similarly teaches:
A circuit (see figure 4), the circuit comprising:
a plurality of signal lines (vertical signal lines, VSL, paragraph 0094);
a plurality of input portions respectively connected to the plurality of signal lines (The Examiner interprets the portions of the vertical signal lines (VSL) coupled to the pixel array unit (1) in figure 4 to be the plurality of input portions.), and each configured to receive a signal from an outside of the circuit (i.e. to receive a signal from the pixel array unit (1), paragraph 0094, see figure 4);
a plurality of signal processing circuits (e.g. comprising comparators (5) and counters (6), paragraph 0095) respectively connected to the plurality of input portions via the plurality of signal lines (VSL, see figure 4, paragraph 0095); and
a plurality of transistors (dummy pixels, 2, selection transistors, 3, paragraphs 0095 and 0097) configured to supply a predetermined voltage (i.e. a test voltage, Vt) to the plurality of signal lines (VSL, see paragraphs 0097-0100) in a state where no signal is input to the plurality of input portions from the outside (As shown in figure 4, the transistors (2, 3) are always configured to supply the test voltage (Vt) to the vertical signal lines (VSL), including in a state where no signal is input to the plurality of input portions from the pixels array unit (1).), wherein
a part (2) of the plurality of transistors (2, 3) is connected to a first control line (i.e. to receive a “control voltage” from the test voltage switching circuit (11), figure 4, paragraph 0097), and another part (3) of the plurality of transistors (2, 3) is connected to a second control line different from the first control line (i.e. to receive a “dummy selecting signal”, figure 4, paragraph 0099).
However, Takamiya et al. additionally teaches that a number of all transistors connected to the first control line is smaller than a number of the plurality of transistors (As shown in figure 4, there are four transistors (2) connected to the first control line and eight transistors (2, 3) in total.), and
wherein a number of all transistors connected to the second control line is smaller than a number of the plurality of transistors (As shown in figure 4, there are four transistors (3) connected to the second control line and eight transistors (2, 3) in total.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have a number of first and second transistors respectively connected to the first and second control lines taught by claim 1 of US 12,167,156 be smaller than a number of the plurality of transistors as taught by Tamamiya et al. for the benefit of enabling adjustment of a reference voltage even in a case where a low-voltage implementation of a source voltage is made (Tamamiya et al., paragraph 0011).
Consider claim 2, claim 2 of US 12,167,156 teaches (in parentheses):
each of the plurality of signal processing circuits includes an analog-to-digital (AD) conversion unit configured to convert the predetermined voltage supplied from a corresponding one of the plurality of transistors into a digital signal (each of the plurality of signal processing circuits includes an analog-to-digital (AD) conversion unit configured to convert the predetermined voltage supplied from a corresponding one of the plurality of transistors into a digital signal).
Consider claim 3, claim 3 of US 12,167,156 teaches (in parentheses):
the digital signal generated by each of the plurality of signal processing circuits is output to the outside of the circuit substrate (the digital signal generated by each of the plurality of signal processing circuits is output to the outside of the circuit substrate).
Consider claim 4, claim 4 of US 12,167,156 teaches (in parentheses):
a circuit configured to compare the digital signal with an expected value (a circuit configured to compare the digital signal with an expected value).
Consider claim 5, claim 5 of US 12,167,156 teaches (in parentheses):
the circuit outputs, to the outside of the circuit substrate, a signal indicating that a difference between the digital signal and the expected value is detected as being greater than a predetermined amount (the circuit outputs, to the outside of the circuit substrate, a signal indicating that a difference between the digital signal and the expected value is detected as being greater than a predetermined amount).
Consider claim 6, claim 6 of US 12,167,156 teaches (in parentheses):
a power supply voltage is supplied to one of main nodes of each of the plurality of transistors, and the plurality of transistors serves as switches configured to switch between supplying and not supplying, to the plurality of signal lines, the predetermined voltage based on the power supply voltage (a power supply voltage is supplied to one of main nodes of each of the plurality of transistors, and the plurality of transistors serves as switches configured to switch between supplying and not supplying, to the plurality of signal lines, the predetermined voltage based on the power supply voltage).
Consider claim 7, claim 7 of US 12,167,156 teaches (in parentheses):
a plurality of current sources respectively connected to the plurality of signal lines (a plurality of current sources respectively connected to the plurality of signal lines), wherein each of the plurality of transistors is configured to perform a source follower operation with a corresponding one of the plurality of current sources (each of the plurality of transistors is configured to perform a source follower operation with a corresponding one of the plurality of current sources).
Consider claim 8, claim 1 of US 12,167,156 teaches (in parentheses):
a plurality of current sources respectively connected to the plurality of signal lines; and a plurality of second transistors each configured to switch a conductive state and a non-conductive state of an electrical path between a corresponding one of the plurality of input portions and a corresponding one of the plurality of signal processing circuits, the plurality of second transistors being respectively connected to the plurality of signals lines, wherein one node of each of the plurality of second transistors is connected to a corresponding one of the plurality of transistors and a corresponding one of the plurality of current sources, and wherein another node of each of the plurality of second transistors is connected to the corresponding one of the plurality of signal processing circuits (a plurality of current sources respectively connected to the plurality of signal lines; and a plurality of second transistors each configured to switch a conductive state and a non-conductive state of an electrical path between a corresponding one of the plurality of input portions and a corresponding one of the plurality of signal processing circuits, the plurality of second transistors being respectively connected to the plurality of signals lines, wherein a part of the plurality of transistors is connected to a first control line, and another part of the plurality of transistors is connected to a second control line different from the first control line, wherein one node of each of the plurality of second transistors is connected to a corresponding one of the plurality of transistors and a corresponding one of the plurality of current sources, and wherein another node of each of the plurality of second transistors is connected to the corresponding one of the plurality of signal processing circuits).
Consider claim 10, claim 1 of US 12,167,156 teaches (in parentheses):
a plurality of second transistors each configured to switch a conductive state and a non-conductive state of an electrical path between a corresponding one of the plurality of input portions and a corresponding one of the plurality of signal processing circuits, the plurality of second transistors being respectively connected to the plurality of signals lines, wherein one node of each of the plurality of second transistors is connected to a corresponding one of the plurality of transistors and a corresponding one of the plurality of current sources, and wherein another node of each of the plurality of second transistors is connected to the corresponding one of the plurality of signal processing circuits (a plurality of second transistors each configured to switch a conductive state and a non-conductive state of an electrical path between a corresponding one of the plurality of input portions and a corresponding one of the plurality of signal processing circuits, the plurality of second transistors being respectively connected to the plurality of signals lines, wherein a part of the plurality of transistors is connected to a first control line, and another part of the plurality of transistors is connected to a second control line different from the first control line, wherein one node of each of the plurality of second transistors is connected to a corresponding one of the plurality of transistors and a corresponding one of the plurality of current sources, and wherein another node of each of the plurality of second transistors is connected to the corresponding one of the plurality of signal processing circuits).
Consider claim 13, claim 8 of US 12,167,156 teaches (in parentheses):
signals output from a plurality of pixels each including a photoelectric conversion unit are input to the plurality of input portions, the plurality of pixels being arranged in a plurality of rows and a plurality of columns on the other substrate, and wherein at least two of the plurality of input portions are provided corresponding to pixels in one of the plurality of columns (signals output from a plurality of pixels each including a photoelectric conversion unit are input to the plurality of input portions, the plurality of pixels being arranged in a plurality of rows and a plurality of columns on the other substrate, and wherein at least two of the plurality of input portions are provided corresponding to pixels in one of the plurality of columns).
Consider claim 14, claim 9 of US 12,167,156 teaches (in parentheses):
each of the plurality of signal processing circuits includes a waveform shaping circuit and a counter that are configured to process a signal output from an avalanche photodiode provided on the other substrate (each of the plurality of signal processing circuits includes a waveform shaping circuit and a counter that are configured to process a signal output from an avalanche photodiode provided on the other substrate).
Consider claim 15, claim 10 of US 12,167,156 teaches (in parentheses):
the circuit substrate is manufactured by a manufacturing apparatus different from a manufacturing apparatus for the other substrate (the circuit substrate is manufactured by a manufacturing apparatus different from a manufacturing apparatus for the other substrate).
Consider claim 17, claim 12 of US 12,167,156 teaches (in parentheses):
the circuit substrate and the other substrate are laminated (the circuit substrate and the other substrate are laminated).
Consider claim 18, claim 13 of US 12,167,156 teaches (in parentheses):
Equipment comprising: the semiconductor apparatus according to claim 17, wherein the equipment further comprises at least one of: an optical apparatus corresponding to the semiconductor apparatus; a control apparatus configured to control the semiconductor apparatus; a processing apparatus configured to process a signal output from the semiconductor apparatus; a display apparatus configured to display information obtained by the semiconductor apparatus; a storage apparatus configured to store the information obtained by the semiconductor apparatus; or a mechanical apparatus configured to operate based on the information obtained by the semiconductor apparatus ( Equipment comprising: the semiconductor apparatus according to claim 12, wherein the equipment further comprises at least one of: an optical apparatus corresponding to the semiconductor apparatus; a control apparatus configured to control the semiconductor apparatus; a processing apparatus configured to process a signal output from the semiconductor apparatus; a display apparatus configured to display information obtained by the semiconductor apparatus; a storage apparatus configured to store the information obtained by the semiconductor apparatus; or a mechanical apparatus configured to operate based on the information obtained by the semiconductor apparatus).
Consider claim 11, claim 14 of US 12,167,156 teaches (in parentheses):
A circuit substrate to be laminated on another substrate, the circuit substrate comprising: (A circuit substrate to be laminated on another substrate, the circuit substrate comprising:)
a plurality of signal lines; (a plurality of signal lines)
a plurality of input portions respectively connected to the plurality of signal lines, and each configured to receive a signal from an outside of the circuit substrate; (a plurality of input portions respectively connected to the plurality of signal lines, and each configured to receive a signal from an outside of the circuit substrate)
a plurality of signal processing circuits respectively connected to the plurality of input portions via the plurality of signal lines (a plurality of signal processing circuits respectively connected to the plurality of input portions via the plurality of signal lines); and
a plurality of transistors configured to supply a predetermined voltage to the plurality of signal lines in a state where no signal is input to the plurality of input portions from the outside (a plurality of transistors configured to supply a predetermined voltage to the plurality of signal lines in a state where no signal is input to the plurality of input portions from the outside); and
a plurality of third transistors respectively connected to the plurality of signal lines, and each configured to switch between supplying and not supplying a second voltage different from the predetermined voltage, wherein each of the plurality of transistors is a transistor of a first conductivity type, and wherein each of the plurality of third transistors is a transistor of a second conductivity type different from the first conductivity type (“a plurality of third transistors respectively connected to the plurality of signal lines, and each configured to switch between supplying and not supplying a second voltage different from the predetermined voltage, wherein a part of the plurality of transistors is connected to a first control line, and another part of the plurality of transistors is connected to a second control line different from the first control line, wherein each of the plurality of transistors is a transistor of a first conductivity type, and wherein each of the plurality of third transistors is a transistor of a second conductivity type different from the first conductivity type”).
Claim 14 of US 12,167,156 does not explicitly teach wherein a number of all transistors connected to the first control line is smaller than a number of the plurality of transistors, and wherein a number of all transistors connected to the second control line is smaller than a number of the plurality of transistors.
Takamiya et al. similarly teaches:
A circuit (see figure 4), the circuit comprising:
a plurality of signal lines (vertical signal lines, VSL, paragraph 0094);
a plurality of input portions respectively connected to the plurality of signal lines (The Examiner interprets the portions of the vertical signal lines (VSL) coupled to the pixel array unit (1) in figure 4 to be the plurality of input portions.), and each configured to receive a signal from an outside of the circuit (i.e. to receive a signal from the pixel array unit (1), paragraph 0094, see figure 4);
a plurality of signal processing circuits (e.g. comprising comparators (5) and counters (6), paragraph 0095) respectively connected to the plurality of input portions via the plurality of signal lines (VSL, see figure 4, paragraph 0095); and
a plurality of transistors (dummy pixels, 2, selection transistors, 3, paragraphs 0095 and 0097) configured to supply a predetermined voltage (i.e. a test voltage, Vt) to the plurality of signal lines (VSL, see paragraphs 0097-0100) in a state where no signal is input to the plurality of input portions from the outside (As shown in figure 4, the transistors (2, 3) are always configured to supply the test voltage (Vt) to the vertical signal lines (VSL), including in a state where no signal is input to the plurality of input portions from the pixels array unit (1).), wherein
a part (2) of the plurality of transistors (2, 3) is connected to a first control line (i.e. to receive a “control voltage” from the test voltage switching circuit (11), figure 4, paragraph 0097), and another part (3) of the plurality of transistors (2, 3) is connected to a second control line different from the first control line (i.e. to receive a “dummy selecting signal”, figure 4, paragraph 0099).
However, Takamiya et al. additionally teaches that a number of all transistors connected to the first control line is smaller than a number of the plurality of transistors (As shown in figure 4, there are four transistors (2) connected to the first control line and eight transistors (2, 3) in total.), and
wherein a number of all transistors connected to the second control line is smaller than a number of the plurality of transistors (As shown in figure 4, there are four transistors (3) connected to the second control line and eight transistors (2, 3) in total.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have a number of first and second transistors respectively connected to the first and second control lines taught by claim 14 of US 12,167,156 be smaller than a number of the plurality of transistors as taught by Tamamiya et al. for the benefit of enabling adjustment of a reference voltage even in a case where a low-voltage implementation of a source voltage is made (Tamamiya et al., paragraph 0011).
Allowable Subject Matter
Claims 9, 12, 16 and 19-22 would be allowable upon submission of a proper Terminal Disclaimer overcoming the double patenting rejection thereof.
Claims 8, 10, 11 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and upon submission of a proper Terminal Disclaimer overcoming the double patenting rejection thereof.
The following is a statement of reasons for the indication of allowable subject matter:
Consider claim 9, the closest prior art, Takamiya et al. (US 2012/0119063) teaches:
A circuit (see figure 4), the circuit comprising:
a plurality of signal lines (vertical signal lines, VSL, paragraph 0094);
a plurality of input portions respectively connected to the plurality of signal lines (The Examiner interprets the portions of the vertical signal lines (VSL) coupled to the pixel array unit (1) in figure 4 to be the plurality of input portions.), and each configured to receive a signal from an outside of the circuit (i.e. to receive a signal from the pixel array unit (1), paragraph 0094, see figure 4);
a plurality of signal processing circuits (e.g. comprising comparators (5) and counters (6), paragraph 0095) respectively connected to the plurality of input portions via the plurality of signal lines (VSL, see figure 4, paragraph 0095); and
a plurality of transistors (dummy pixels, 2, selection transistors, 3, paragraphs 0095 and 0097) configured to supply a predetermined voltage (i.e. a test voltage, Vt) to the plurality of signal lines (VSL, see paragraphs 0097-0100) in a state where no signal is input to the plurality of input portions from the outside (As shown in figure 4, the transistors (2, 3) are always configured to supply the test voltage (Vt) to the vertical signal lines (VSL), including in a state where no signal is input to the plurality of input portions from the pixels array unit (1).).
However, the prior art of record does not teach nor reasonably suggest that the circuit substrate comprises a plurality of current sources respectively connected to the plurality of signal lines; and a plurality of second transistors each configured to switch a conductive state and a non-conductive state of an electrical path between a corresponding one of the plurality of input portions and a corresponding one of the plurality of signal processing circuits, the plurality of second transistors being respectively connected to the plurality of signals lines, wherein one node of each of the plurality of second transistors is connected to a corresponding one of the plurality of transistors and a corresponding one of the plurality of current sources, and wherein another node of each of the plurality of second transistors is connected to the corresponding one of the plurality of signal processing circuits, in combination with the other elements recited in claim 9.
Claims 19 and 20 are allowed as depending from or otherwise requiring all of the limitations of an allowed claim 9.
Consider claim 12, the closest prior art, Takamiya et al. (US 2012/0119063) teaches:
A circuit (see figure 4), the circuit comprising:
a plurality of signal lines (vertical signal lines, VSL, paragraph 0094);
a plurality of input portions respectively connected to the plurality of signal lines (The Examiner interprets the portions of the vertical signal lines (VSL) coupled to the pixel array unit (1) in figure 4 to be the plurality of input portions.), and each configured to receive a signal from an outside of the circuit (i.e. to receive a signal from the pixel array unit (1), paragraph 0094, see figure 4);
a plurality of signal processing circuits (e.g. comprising comparators (5) and counters (6), paragraph 0095) respectively connected to the plurality of input portions via the plurality of signal lines (VSL, see figure 4, paragraph 0095); and
a plurality of transistors (dummy pixels, 2, selection transistors, 3, paragraphs 0095 and 0097) configured to supply a predetermined voltage (i.e. a test voltage, Vt) to the plurality of signal lines (VSL, see paragraphs 0097-0100) in a state where no signal is input to the plurality of input portions from the outside (As shown in figure 4, the transistors (2, 3) are always configured to supply the test voltage (Vt) to the vertical signal lines (VSL), including in a state where no signal is input to the plurality of input portions from the pixels array unit (1).).
However, the prior art of record does not teach nor reasonably suggest that the circuit substrate comprises a plurality of third transistors respectively connected to the plurality of signal lines, and each configured to switch between supplying and not supplying a second voltage different from the predetermined voltage, wherein each of the plurality of transistors is a transistor of a first conductivity type, and wherein each of the plurality of third transistors is a transistor of a second conductivity type different from the first conductivity type, in combination with the other elements recited in claim 12.
Claims 16, 21 and 22 are allowed as depending from or otherwise requiring all of the limitations of an allowed claim 12.
Consider claim 8, the prior art of record does not teach nor reasonably suggest a plurality of current sources respectively connected to the plurality of signal lines; and a plurality of second transistors each configured to switch a conductive state and a non-conductive state of an electrical path between a corresponding one of the plurality of input portions and a corresponding one of the plurality of signal processing circuits, the plurality of second transistors being respectively connected to the plurality of signals lines, wherein one node of each of the plurality of second transistors is connected to a corresponding one of the plurality of transistors and a corresponding one of the plurality of current sources, and wherein another node of each of the plurality of second transistors is connected to the corresponding one of the plurality of signal processing circuits, in combination with the other elements recited in parent claim 1.
Consider claim 10, the prior art of record does not teach nor reasonably suggest a plurality of second transistors each configured to switch a conductive state and a non-conductive state of an electrical path between a corresponding one of the plurality of input portions and a corresponding one of the plurality of signal processing circuits, the plurality of second transistors being respectively connected to the plurality of signals lines, wherein one node of each of the plurality of second transistors is connected to a corresponding one of the plurality of transistors and a corresponding one of the plurality of current sources, and wherein another node of each of the plurality of second transistors is connected to the corresponding one of the plurality of signal processing circuits, in combination with the other elements recited in parent claims 1 and 7.
Consider claim 11, the prior art of record does not teach nor reasonably suggest a plurality of third transistors respectively connected to the plurality of signal lines, and each configured to switch between supplying and not supplying a second voltage different from the predetermined voltage, wherein each of the plurality of transistors is a transistor of a first conductivity type, and wherein each of the plurality of third transistors is a transistor of a second conductivity type different from the first conductivity type, in combination with the other elements recited in parent claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kawata (US 2012/0033121) teaches an imaging device with a test signal generation unit (see figure 2).
Lee et al. (US 6,903,670) teaches an imaging device with a test signal generation unit (see figures 2 and 3).
Okura et al. (US 2016/0373673) teaches an imaging device with a test signal generation unit (see figures 5 and 12).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT H CUTLER whose telephone number is (571)270-1460. The examiner can normally be reached approximately Mon - Fri 8:00-4:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at (571)272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637