DETAILED ACTION
This action is responsive to the following communications: the Application filed November 12, 2024.
Claims 1-20 are pending. Claim 1 and claim 13 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statements (IDS) filed on November 12, 2024. This IDS has been considered.
Specification
The disclosure is objected to because of the following informalities:
Specification, paragraph 8’s last sentence (“The plurality of bit lines may be perpendicular to surface of the substrate”) is already stated in paragraph 8’s first sentence (“. . . a plurality of bit lines extending perpendicular to the surface of the substrate.”); and
Specification, paragraph 44’s first sentence (definition of “a,” “an,” “the,”) is already stated in paragraph 43’s second sentence (definition of “a,” “an,” “the”).
Appropriate correction is required.
Claim Objections
Claims 8 and 20 are objected to because of the following informalities: use of “and” when the intent is “or.”
Both Claims 8 and 20 recite, “at least one of Ge, As, and Sb” and “at least one of Se, Te, and S.” The use of “and” in this context would require at least one of Ge, at least one of As, and at least one of Sb, as well as at least one of Se, at least one of Te and at least one of S, consistent with the interpretation of these elements being recited in the conjunctive. However, as is clear from applicant’s originally filed disclosure, the intent is at least one of Ge, As, or Sb, and at least one of Se, Te, or S.
It is suggested to change the “and” to --or--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites “in each of the plurality of memory cells, a gate electrode of the transistor . . . .” The new recitation to “a gate electrode” is redundant with limitations already presented in antecedent claims 1 and 2. Claim 1 recites “each of the plurality of memory cells includes a transistor” and claim 2 further limits “the transistor” by indicate it further comprises “a gate electrode.” It seems applicant intended claim 6’s “a gate electrode” to be --the gate electrode-- to make clear that claim 6’s gate electrode has antecedent basis in claim 2’s “gate electrode.”
For purposes of compact prosecution, the claim will be interpreted consistent with the suggested correction. MPEP 2173.06.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 8, 9, 11, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kurotsuchi et al. (US 7859896 B2; hereinafter ‘Kurotsuchi”).
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Regarding independent claim 1, Kurotsuchi teaches a three-dimensional (3D) memory device comprising:
a plurality of memory cells arranged in three dimensions on a substrate (see Examiner’s Markup of Kurotsuchi Figs. 11 and 13),
wherein each of the plurality of memory cells includes a transistor (Fig. 1: 109) and a self-selecting memory layer (e.g., chalcogenide memory element Fig. 2: 102 of information memory section Fig. 1: 103) connected in series,
the transistor includes a channel extending parallel to a surface of the substrate (see Fig. 2),
the self-selecting memory layer (Fig. 2: 102) includes a chalcogenide-based material (see col. 6, ll. 65) having Ovonic threshold switching characteristics (Figs. 5 and 6; col. 7, ll. 57–67; col. 8, ll. 1-30), and
the self-selecting memory layer is configured to have a threshold voltage change according to a polarity and an intensity of an applied voltage (Figs. 5 and 6; col. 7, ll. 57–67; col. 8, ll. 1-30).
Regarding claim 2, Kurotsuchi teaches the limitations of claim 1.
Kurotsuchi further teaches that the transistor further comprises: a gate electrode (Fig. 13: 314) on the channel layer; and a gate insulating layer (Fig. 13: 312) between the channel layer and the gate electrode (col. 9, ll. 53-57).
Regarding claim 8, Kurotsuchi teaches the limitations of claim 1.
Kurotsuchi also teaches that, under the broadest reasonable interpretation, the claimed self-selecting memory layer corresponds to the chalcogenide memory element (Fig. 2: 102) of the information memory section (Fig. 1: 103).
Kurotsuchi further teaches a chalcogenide comprising germanium, antimony, and tellurium (Ge2Sb2Te5) (col. 1, ll. 46-48; col. 7, ll. 49–50), thereby teaching that the self-selecting memory layer comprises a chalcogen element and at least one of Ge, As, and Sb, and the chalcogen element includes at least one of Se, Te, and S.
Regarding claim 9, Kurotsuchi teaches the limitations of claim 1. Kurotsuchi also teaches that each of the plurality of memory cells (e.g., Fig. 2) further comprises a metal layer (Fig. 2: 105; see col. 7, ll. 50-51; see also col. 8, ll. 21-30) on one side of the self-selecting memory layer (Fig. 2: 102).
Regarding claim 11, Kurotsuchi teaches the limitations of claim 1.
Kurotsuchi further teaches a plurality of bit lines (Fig. 33: BL0-BLm) on the substrate;
a plurality of select lines (Fig. 33: SL0-SLm; col. 12, ll. 31-42) on the substrate,
wherein the plurality of select lines (Fig. 33: SL0-SLm) are configured to select a selected bit line (e.g., Fig. 33: BL0) of the plurality of bit lines (the Y-system address decoder Y-DEC selects a set of a bit line BL and a source line SL as indicated col. 12, ll. 61-65, meaning the selection of the source line will also result in the selection of a designated bit line through the column decoder Y-DEC).
Regarding claim 12, Kurotsuchi teaches the limitations of claim 1.
Kurotsuchi further teaches an electronic apparatus comprising the claimed 3D memory device (Figs. 33).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 8, 11-13, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bai (US 10839897 B1) in view of Ma et al. (US 20110116301 A1; hereinafter “Ma”), as supported by Conte et al. (US 20220044099 A1; hereinafter “Conte”).
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Regarding independent claim 1, Bai teaches a three-dimensional (3D) memory device comprising:
a plurality of memory cells (Fig. 2: 200, col. 8, ll. 50-51; see also Fig. 4A: M111 . . . M236) arranged in three dimensions on a substrate (Fig. 2: 201, 220, 218; see also Fig. 3 and col. 4, ll. 10-14; col. 8, ll. 37-40);
each of the plurality of memory cells (Fig. 4A: M111 . . . M236) include a self-selecting memory layer (see column 11, lines 3-4, as related to column 3, lines 35-56);
the self-selecting memory layer includes a chalcogenide-based material (col. 20, ll. 53-56) having Ovonic threshold switching characteristics (col. 8, ll. 59-61; col. 8, ll. 67 to col. 9, ll. 1), and the self-selecting memory layer is configured to have a threshold voltage change according to a polarity and an intensity of an applied voltage (col. 7, ll. 22-40).
However, Bai is silent with respect to “each of the plurality of memory cells includes a transistor and [the] self-selecting memory layer connected in series, the transistor includes a channel layer and the channel layer is parallel to a surface of the substrate”.
Ma teaches wherein each of the plurality of memory cells includes a transistor (Fig. 4B: 428) and a self-selecting memory layer (Fig. 4B: unlabeled memory element 423 connected to 428) connected in series (see also, para. 3, 12, 35), the transistor includes a channel layer and the channel layer is parallel to a surface of the substrate (Fig. 4B illustrates a MOSFET, which has a channel parallel to the surface of the substrate).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply Ma’s teachings to Bai such that each phase-change memory cell includes a MOSFET access transistor connected in series with the phase-change memory material, for the purpose of enabling selective access and sensing of the memory cell (Ma; para. 35; Fig. 4B), consistent with Bai's teaching of using a series-connected selector “in order to reduce leakage currents” (Bai; col. 3, ll. 63-67). Furthermore, Conte supports motivation to include an access transistor for resistance memory because it is a classical technique for selecting resistive memory point and a MOS transistor would permit bidirectional flow of current (see Conte para. 6), which is required by Bai’s programming (Bai; column 7, lines 22-28).
Regarding claim 2, Bai and Ma, as combined and as supported by Conte, teach the limitations of claim 1.
Ma also teaches the transistor further comprises: a gate electrode on the channel layer; and a gate insulating layer between the channel layer and the gate electrode (Fig. 4B: 428 is a MOSFET; para. 35).
Regarding claim 3, Bai and Ma, as combined and as supported by Conte, teach the limitations of claim 2.
Bai further teaches a plurality of bit lines (Fig. 4A: LBL11-LBL33) extending perpendicular to the surface of the substrate (column 10, line 63), wherein the plurality of memory cells are arranged along the plurality of bit lines (see Fig. 4A).
Regarding claim 4, Bai and Ma, as combined and as supported by Conte, teach the limitations of claim 3.
Ma further teaches that in each memory cell (Fig. 4B), the channel layer of the transistor is connected to a corresponding one of the plurality of bit lines (Fig. 4B: 428 is connected to BL0)
Regarding claim 5, Bai and Ma, as combined and as supported by Conte, teach the limitations of claim 4.
Bai further teaches a plurality of word lines (Fig. 4A: WL10-WL23), wherein the plurality of word lines extend parallel to the surface of the substrate (see Fig. 4A) and intersect the plurality of bit lines (see Fig. 4A: WLxx with respect to BLxx).
Regarding claim 6, Bai and Ma, as combined and as supported by Conte, teach the limitations of claim 5.
Ma further teaches that in each memory cell (Fig. 4B), a gate electrode of the transistor (see Fig. 4B: 428’s gate) is connected to a corresponding one of the plurality of word lines (Fig. 4B: WL0).
Regarding claim 8, Bai and Ma, as combined and as supported by Conte, teach the limitations of claim 1.
Bai further teaches the self-selecting memory layer comprises a chalcogen element and at least one of Ge, As, and Sb (see column 3, lines 35-40), and
the chalcogen element includes at least one of Se, Te, and S (see column 3, lines 35-40).
Regarding claim 11, Bai and Ma, as combined and as supported by Conte, teach the limitations of claim 1.
Bai further teaches a plurality of bit lines (Fig. 4A: LBL11-LBL33) on the substrate,
a plurality of select lines (Fig. 4A: SG1-SG3) on the substrate, wherein
the plurality of select lines (Fig. 4A: SG1-SG3) are configured to select a selected bit line of the plurality of bit lines (see Fig. 4A: SG1-SG3 and interaction with Q11-Q33 to select a selected bit line LBL11-LBL33).
Regarding claim 12, Bai and Ma, as combined and as supported by Conte, teach the limitations of claim 1.
Bai further teaches a 3D memory device (Fig. 4A).
Regarding independent method claim 13, Bai teaches an operation method of a three-dimensional (3D) memory device (see Fig. 4A), the operation method comprising:
selecting a desired memory cell (see e.g., Fig. 4A: M211) by applying a signal to a selected bit line (see Fig. 4A: LBL11) among a plurality of bit lines (Fig. 4A: LBL11-LBL33) and a selected word line (see Fig. 4A: WL20) among a plurality of word lines (Fig. 4A: WL10-WL23),wherein the 3D memory device (Fig. 4A) includes a plurality of memory cells (Fig. 4A: M111 . . . M236) on a substrate at positions where the plurality of bit lines (Fig. 4A: LBL11-LBL33) intersects the plurality of word lines (Fig. 4A: WL10-WL23),
the plurality of bit lines (Fig. 4A: LBL11-LBL33) extend perpendicular to a surface of the substrate (column 10, line 63),
the plurality of word lines (Fig. 4A: WL10-WL23) extend parallel to the surface of the substrate and intersect the plurality of bit lines (Fig. 4A: LBL11-LBL33),
each of the plurality of memory cells (e.g., Fig. 4A: M211) includes a self-selecting memory layer (see column 11, lines 3-4),
the self-selecting memory layer includes a chalcogenide-based material having Ovonic threshold switching characteristics (colulmn 3, lines 35-37),
the self-selecting memory layer is configured to have a threshold voltage change according to a polarity and an intensity of an applied voltage (col. 7, ll. 22-24, ll. 33-34 and ll. 36-38).
Bai states “In one embodiment, each memory cell includes a selector element (e.g., a diode or a threshold switch) and a memory element (i.e., a state change element); however, the only examples Bai provides of their selector element is a “diode” or a “threshold switch,” not a “transistor” (see column 8, lines 58-61). Thus, Bai is silent with respect to “each memory cell includes a transistor and [the] self-selecting memory layer connected in series, the transistor includes a channel layer parallel to the surface of the substrate, and a gate electrode on the channel layer”.
Ma teaches each memory cell (see Fig. 4B) includes a transistor (Fig. 4B: 428) and a self-selecting memory layer (Fig. 4B: unlabeled memory element 423 connected to 428) connected in series (see also para. 3), the transistor includes a channel layer parallel to the surface of the substrate and a gate electrode on the channel layer (Fig. 4B illustrates a MOSFET, which has a channel parallel to the surface of the substrate).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply Ma’s teachings to Bai such that each phase-change memory cell includes a MOSFET access transistor connected in series with the phase-change memory material, for the purpose of enabling selective access and sensing of the memory cell (Ma; para. 35; Fig. 4B), consistent with Bai's teaching of using a series-connected selector “in order to reduce leakage currents” (Bai; col. 3, ll. 63-67). Furthermore, Conte supports motivation to include an access transistor for resistance memory because it is a classical technique for selecting resistive memory point and a MOS transistor would permit bidirectional flow of current (see Conte para. 6), which is required by Bai’s programming (Bai column 7, lines 22-28).
Regarding claim 18, Bai and Ma, as combined and as supported by Conte, teach the limitations of claim 13.
Bai teaches wherein the 3D memory device further includes a plurality of select lines (Fig. 4A: SG1-SG3) on the substrate, and the plurality of select lines (Fig. 4A: SG1-SG3) are configured to select the selected bit line among the plurality of bit lines (see Fig. 4A: SG1-SG3 and interaction with Q11-Q33 to select a selected bit line LBL11-LBL33).
Regarding claim 19, Bai and Ma, as combined and as supported by Conte, teach the limitations of claim 13.
Ma teaches in each of the plurality of memory cells (see Fig. 4B), the channel layer is connected to a corresponding one of the plurality of bit lines (see Fig. 4B: 428 connects to bit line BL0) and the gate electrode (Fig. 4B: unlabled gate of 428) is connected to a corresponding one of the plurality of word lines (Fig. 4B: WL0).
Regarding claim 20, Bai and Ma, as combined and as supported by Conte, teach the limitations of claim 13.
Bai teaches wherein the self-selecting memory layer comprises a chalcogen element and at least one of Ge, As, and Sb (see column 3, lines 35-40), and the chalcogen element comprises at least one of Se, Te, and S (see column 3, lines 35-40).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kurotsuchi (US 7859896 B2) in view of Resta et al. (US 20090080242 A1; hereinafter “Resta”).
Regarding claim 7, Kurotsuchi teaches the limitations of claim 1.
However, Kurotsuchi is silent with respect to “the 3D memory device is configured to implement a multi-level memory based on changing an intensity of a reset pulse voltage applied to the self-selecting memory layer”.
Resta teaches the 3D memory device is configured to implement a multi-level memory (see para. 32-33) based on changing an intensity of a reset pulse voltage applied to the self-selecting memory layer (see also para. 45-46).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply Resta’s teaching of multi-level memory to Kurotsuchi’s memory such that the memory cells are multilevel based on intensity of the reset pulse, for the purpose of providing multiple resistance states within a memory cell, thereby increasing memory density.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kurotsuchi (US 7859896 B2) in view of Gealy et al. (US 20150123066 A1; hereinafter “Gealy”).
Regarding claim 10, Kurotsuchi teaches the limitations of claim 9.
However, Kurotsuchi is silent with respect to “wherein each of the plurality of memory cells further comprises an interlayer on both end portions of the self-selecting memory layer”.
Gealy teaches each of the plurality of memory cells (see Fig. 1: 101) further comprises an interlayer (Fig. 1: 111 and 109) on both end portions of the self-selecting memory layer (Fig. 1: 110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kurotsuchi according to Gealy’s teaching to provide interface layers on both end portions of the phase-change memory layer to “provide a reduced resistance between the chalcogenide-based phase-change memory layer and the respective electrode layer” (Gealy, para. 13).
Claims 14, 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Bai (US 10839897 B1) in view of Ma et al. (US 20110116301 A1; hereinafter “Ma”), as supported by Conte et al. (US 20220044099 A1; hereinafter “Conte”), and further in view of Kamalanathan et al. (US 11017856 B1; hereinafter “Kamalanathan”).
Regarding claim 14, Bai and Ma, as combined and as supported by Conte, teach the limitations of claim 13.
Bai teaches performing a set operation (see Fig. 6C) or a reset operation (see Fig. 6E) on a desired memory cell, which requires applied voltage through a selected bit line (e.g. Fig. 4A: M211 requiring use of LBL11).
Ma also teaches performing a set operation or a reset operation on a desired memory cell (see para. 27).
Bai and Ma, however, are silent with respect to the express provision that the set/reset operation is performed “by applying a voltage greater than or equal to a threshold voltage of the self-selecting memory layer to the transistor of the desired memory cell through the selected bit line.”
Kamalanathan teaches performing a set operation or a reset operation on the desired memory cell by applying a voltage greater than or equal to a threshold voltage of the self-selecting memory layer to the transistor of the desired memory cell through the selected bit line (col. 5, ll. 12-14 and ll. 18-20; col. 10, ll. 66 to col. 11, ll. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Kamalanathan’s set/reset programming teachings with the memory device of Bai and Ma. The combination would allow the memory cell to perform set and reset operations by applying a voltage at or above the threshold voltage to switch the memory element through the access transistor.
Regarding claim 16, Bai and Ma, as combined and as supported by Conte, teach the limitations of claim 13.
Bai teaches their memory may be multi-level (see column 7, lines 29-43).
Bai and Ma are silent with respect to the specific provision implementing a multi-level memory by changing an intensity of a reset pulse voltage.
Kamalanathan teaches implementing a multi-level memory by changing an intensity of a reset pulse voltage applied to the self-selecting memory layer of the desired memory cell using the selected bit line and the selected word line (col. 8, ll. 50-55; Figs. 4, 7-8). Specifically, Kamalanathan teaches that “a plurality of intermediate states can be generated using a partial reset signal” (col. 6, ll. 18-20) and that successive partial reset signals cause the memory element to enter lesser intermediate states (col. 6, ll. 52-54).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the multi-level programming teachings of Kamalanathan to the memory device of Bai and Ma to provide multiple distinct memory states by varying the magnitude of reset pulses. Kamalanathan teaches that increasing the magnitude of successive partial reset signals may cause the memory element to transition to a predetermined intermediate state faster (col. 8, ll. 60-63).
Regarding claim 17, Bai, Ma, and Kamalanathan, as combined and as supported by Conte, teach the limitations of claim 16.
Bai teaches the polarity of the reset pulse is different from a polarity of a set pulse voltage (see column 7, lines 22-28).
Kamalanathan further teaches wherein a polarity of the reset pulse voltage is different from a polarity of a set pulse voltage (col. 7, ll. 30-31 and ll. 43-47; Fig. 5).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Bai (US 10839897 B1) in view of Ma et al. (US 20110116301 A1; hereinafter “Ma”), as supported by Conte et al. (US 20220044099 A1; hereinafter “Conte”), and further in view of Kurotsuchi et al. (US 7859896 B2; hereinafter “Kurotsuchi”).
Regarding claim 15, Bai and Ma, as combined, teach the limitations of claim 13.
Bai teaches the read operation with a read voltage (see column 9, lines 9-19).
Bai and Ma are silent with respect to the specific provision performing a read operation on the desired memory cell by applying a read voltage to the self-selecting memory layer of the desired memory cell, and the read voltage is less than or equal to a threshold voltage of the self-selecting memory layer.
Kurotsuchi further teaches performing a read operation on the desired memory cell by applying a read voltage (col. 7, ll. 16-19) to the self-selecting memory layer of the desired memory cell, and the read voltage is less than or equal to a threshold voltage of the self-selecting memory layer (col. 8, ll. 16-20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply Kurotsuchi’s read-operation teachings to the memory device of Bai and Ma in order to read the stored state without risk of destroying stored information (col. 8, ll. 52-55; Fig. 9).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATHY K NGUYEN whose telephone number is (571) 270-0896. The examiner can normally be reached Monday-Friday 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KATHY KIEU NGUYEN/ Examiner, Art Unit 2899
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825
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