Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 6 are rejected under 35 U.S.C. 102(a) as being anticipated by Parthasarathy et al. (United States Patent Application Publication US 2021/0350857), hereinafter Parthasarathy.
Regarding claim 1, Parthasarathy teaches a method comprising: performing one or more monitoring operations on a system on chip (SoC) at a respective plurality of first voltage values to determine first error rates respectively corresponding to the respective plurality of first voltage values ([0101] “Blocks 203 to 209 illustrate the sequential read of bit counts (e.g., at a plurality of test voltages CA, ..., CE) ( e.g., ( e.g., VA' ... , VE).” [0052] “the read manager 113 is further configured to classify the error rate in the hard bit data using the measured signal and noise characteristics and selectively determine whether to read the soft bit data and/or whether to transmit the soft bit data to the controller 115 as a response to the read command.” [0059] “the calibration circuit 145 can measure the signal and noise characteristics 139 by reading different responses from the memory cells in a group (e.g., 131, ..., 133) by varying operating parameters used to read the memory cells, such as the voltage(s) applied during an operation to read data from memory cells.” Based on read of bit counts at various the voltages, error rates in hard bit data is determined. Furthermore, as shown in FIG. 1, 2, [0038]-[0041], the memory sub-system includes various integrated circuits within a same package, which is interpreted as a SoC.);
determining second error rates respectively corresponding to a respective plurality of second voltage values at which the one or more monitoring operations are not performed ([0103] “As illustrated in FIG. 3, the optimized read voltage can be calculated at block 211 from the bit counts (e.g., CA, .. . , CE). At block 213, the memory device 130 applies the optimized read voltage VO to the group of memory cells (e.g., 131 or 133) to obtain hard bit data that corresponds the states of the memory cells in the group (e.g., 131 or 133) under the applied voltage VO. [0103] “Concurrently with the calculation 211 of the optimized read voltage VO and/or the reading 213 of the hard bit data 177, the memory device 130 classifies or predicts, at block 215, the quality of the hard bit data read based on the calibration performed according to the bit counts measured in operations 203 to 209.” As shown in FIG. 3 and [0103], the optimized read voltage is determined. The optimized read voltage corresponds to a point where predicted or calculated to have lower error rates. Furthermore, as the optimized voltage is calculated instead of being measured, monitoring of the operation at the optimized voltage is not performed.); and
responsive to determining a particular voltage value corresponding to a predetermined error rate based on the first error rates and the second error rates, performing one or more operations on the SoC using the determined particular voltage ([0104] “If it is determined, at block 217, to read soft bit data 173, the memory device 130 adjusts the currently applied read voltage on the group of memory cells (e.g., 131 or 133) to adjacent voltages to read soft bit data 173. As illustrated in FIG. 3, the adjacent read voltages (e.g., 181 and 182) are determined based on offsets (e.g., 183 and 184) of the same amount from the optimized read voltage 151. In some implementations, multiple offset amounts are used to generate different sets of offsets to generate soft bit data 173 corresponding to the multiple amounts.” Based on the monitored voltages, which calculates the optimized voltage, the voltage to operate the memory cell, such as read operation, is performed.).
Regarding claim(s) 6, the claim(s) 6 is the apparatus claims of the method claim(s) 1. The claim(s) 6 does(do) not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, Parthasarathy teaches all the limitations of the claim(s) 6.
Regarding claim 9, Parthasarathy teaches wherein the first error rates and the second error rates respectively correspond to a bit error rate (BER) ([0112] “the likelihood of data integrity failure can be in the form of an estimated bit error rate in the hard bit data 177.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 7, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Parthasarathy in view of LI, Chuang-feng; HU, Zhao-wen (CN 110189788 A), hereinafter LI.
Regarding claim 2, Parthasarathy teaches all the limitations of the method of claim 1, as discussed above.
However, Parthasarathy does not teach determining the second error rates respectively corresponding to the respective plurality of second voltage values by extrapolating from the first error rates.
LI teaches determining the second error rates respectively corresponding to the respective plurality of second voltage values by extrapolating from the first error rates (Page 5 “the current read voltage is being prepared for reading flash memory voltage data. reading voltage refers to voltage of reading flash memory data is stored in the used. using the current read data of the voltage reading in the flash memory, the data of the read verification to obtain current error corresponding to the current read voltage. on a read-voltage refers to before the current read voltage for reading the voltage of data in flash memory, the same can be known on an error rate of a read voltage to read the data in the flash memory, the data read to verify the error rate on a corresponding read voltage. calculating the current error rate and a difference between an error rate according to the difference, the current read voltage and a read voltage calculation next read voltage according to the difference error is increased, if increased, from the previous read voltage to the adjusting direction of the current read voltage error, needs to be adjusted along the reverse direction, whereas if the reduced, is correct to the adjusting direction of the current read voltage from a previous read voltage, continuously along the direction for adjustment.” As the error rate is calculated from two error rates and corresponding voltages, a next error rate corresponding next read voltage is determined based on the calculation or extrapolation from the difference between two error rates.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Parthasarathy by incorporating the teaching of LI of determining the second error rates respectively corresponding to the respective plurality of second voltage values by extrapolating from the first error rates. They are all directed toward errors and read voltages in memory. As recognized by LI, directly determining read voltages result in low detection efficiency (Background). By extrapolating or obtaining the read voltage from other measurements of error rates at different voltages, the efficiency of a correct voltage can be improved. Therefore, it would be advantageous to incorporate the teaching of LI of determining the second error rates respectively corresponding to the respective plurality of second voltage values by extrapolating from the first error rates in order to improve the efficiency.
Regarding 7, Parthasarathy teaches all the limitations of the apparatus of claim 6, as discussed above.
LI further teaches wherein the predetermined error rate corresponds to a voltage value greater than the respective plurality of first voltage values (Page 5 “the current read voltage is being prepared for reading flash memory voltage data. reading voltage refers to voltage of reading flash memory data is stored in the used. using the current read data of the voltage reading in the flash memory, the data of the read verification to obtain current error corresponding to the current read voltage. on a read-voltage refers to before the current read voltage for reading the voltage of data in flash memory, the same can be known on an error rate of a read voltage to read the data in the flash memory, the data read to verify the error rate on a corresponding read voltage. calculating the current error rate and a difference between an error rate according to the difference, the current read voltage and a read voltage calculation next read voltage according to the difference error is increased, if increased, from the previous read voltage to the adjusting direction of the current read voltage error, needs to be adjusted along the reverse direction, whereas if the reduced, is correct to the adjusting direction of the current read voltage from a previous read voltage, continuously along the direction for adjustment.” As discussed above, LI suggests that an adjusted voltage is greater than the current read voltage and read voltage.).
Regarding claim 12, Parthasarathy teaches all the limitations of the apparatus of claim 6, as discussed above.
LI further teaches wherein the respective plurality of second voltage values are higher than the respective plurality of first voltage values (Page 5 “the current read voltage is being prepared for reading flash memory voltage data. reading voltage refers to voltage of reading flash memory data is stored in the used. using the current read data of the voltage reading in the flash memory, the data of the read verification to obtain current error corresponding to the current read voltage. on a read-voltage refers to before the current read voltage for reading the voltage of data in flash memory, the same can be known on an error rate of a read voltage to read the data in the flash memory, the data read to verify the error rate on a corresponding read voltage. calculating the current error rate and a difference between an error rate according to the difference, the current read voltage and a read voltage calculation next read voltage according to the difference error is increased, if increased, from the previous read voltage to the adjusting direction of the current read voltage error, needs to be adjusted along the reverse direction, whereas if the reduced, is correct to the adjusting direction of the current read voltage from a previous read voltage, continuously along the direction for adjustment.” As discussed above, LI suggests that an adjusted voltage is higher than the current read voltage and read voltage.).
Claim(s) 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Parthasarathy in view of Wang et al. (United States Patent Application Publication US 2016/0223436), hereinafter Wang.
Regarding claim 3, Parthasarathy teaches all the limitations of the method of claim 1, as discussed above.
However, Parthasarathy does not teach performing the plurality of monitoring operations at a plurality of frequency values.
Wang teaches performing the plurality of monitoring operations at a plurality of frequency values ([0052] “The plot 200 illustrates operating frequency (e.g., clock frequency) of the memory device (horizontal axis) and voltage level of a supply voltage (VDD) provided to the memory device (vertical axis). Each combination of operating frequency and voltage level in the plot 200 is associated with a pass status or a fail status of a test process, such as an error correcting code (ECC) decoding status associated with a decoding process.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teaching of Parthasarathy by incorporating the teaching of Wang of performing the plurality of monitoring operations at a plurality of frequency values. As recognized by Wang, the number of errors detected in the data may be related to the operating frequency of the memory array when the data is received ([0027]). Thus, by monitoring frequency, more accurate determination of error rates can be made. Therefore, it would be advantageous to incorporate the teaching of Wang of performing the plurality of monitoring operations at a plurality of frequency values.
Regarding claim 4, Parthasarathy in view of Wang teaches all the limitations of the method of claim 3, as discussed above.
Wang further teaches performing at least a portion of the one or more monitoring operations while varying the respective plurality of first voltage values, the plurality of frequency values, or any combination thereof ([0052] “in the upper-right corner, lower operating frequencies and higher voltage levels are associated with pass statuses, and in the lower-left corner, higher operating frequencies and lower voltage levels are associated with fail statuses.” As shown in FIG. 2, the plot shows a plurality of voltages and the plurality of frequency values.).
Regarding claim 5, Parthasarathy in view of Wang teaches all the limitations of the method of claim 3, as discussed above.
Wang further teaches performing at least a portion of the one or more monitoring operations while holding a voltage value constant, a frequency value constant, or any combination thereof ([0052] “in the upper-right corner, lower operating frequencies and higher voltage levels are associated with pass statuses, and in the lower-left corner, higher operating frequencies and lower voltage levels are associated with fail statuses.” The plot shows that a horizontal line is monitored at the plurality of frequency values while holding a voltage value constant and a vertical line is monitored at the plurality of voltage values while holding the frequency value.).
Claim(s) 8 are rejected under 35 U.S.C. 103 as being unpatentable over Parthasarathy in view of Mims et al. (United States Patent Application Publication US 2011/0099440), hereinafter Mims.
Regarding claim 8, Parthasarathy teaches all the limitations of the apparatus of claim 6, as discussed above.
However, Parthasarathy does not teach wherein the first error rates and the second error rates respectively correspond to a soft error rate (SER).
Mims teaches wherein the first error rates and the second error rates respectively correspond to a soft error rate (SER) ([0051] “FIG. 3 is a schematic diagram illustrating an embodiment of a test environment 300 suitable for performing a soft error rate (SER) test on the device under test 200 of FIG. 1.” [0055] “The above described test environment, as illustrated in the embodiments in FIGS. 1 and 3, together with execution of the SER software 400 enables test operators to quantify soft errors that occur in memory elements on a production ASIC. Soft error rates can be determined as a function of one or more of radiation intensity, data value or data pattern, as well as ASIC operating parameters such as voltage and temperature.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teaching of Parthasarathy by incorporating the teaching of Mims of the soft error rate (SER). They are all directed toward errors in memory devices. As recognized by Mims, as the size of storage elements decreases, the storage elements are more sensitive to a deposited charge and a given ionizing event is likely to affect more storage elements since more elements will intercept the path of the ionizing radiation ([0004]). By measuring the SER, a reliability and performance can be improved. Therefore, it would be advantageous to incorporate the teaching of Mims of the SER to improve the reliability and the performance.
Claim(s) 11 are rejected under 35 U.S.C. 103 as being unpatentable over Parthasarathy in view of Lai et al. (United States Patent Application Publication US 2021/0141407), hereinafter Lai.
Regarding claim 11, Parthasarathy teaches all the limitations of the apparatus of claim 6, as discussed above.
However, Parthasarathy does not teach wherein at least one of the one or more monitoring operations is performed during a boot operation of the SoC.
Lai teaches wherein at least one of the one or more monitoring operations is performed during a boot operation of the SoC ([0016] “When the electronic device 100 is enabled for a first time (e.g. powered on), the CPU 122 within the SoC 120 may read the boot code 134 from the storage unit 130, and execute the boot code 134 to control/instruct the power management chip 110 to generate a plurality of different supply voltages to the SoC 120… the AVS look-up table can be established according to the plurality of first target supply voltages respectively corresponding to the plurality of first operating frequencies of the CPU 122 and the plurality of second target supply voltages respectively corresponding to the plurality of second operating frequencies of the GPU 124, and the AVS look-up table can be stored into a memory within the SoC 120 or the storage unit 130 for further usage.” Monitoring operation for plurality of different supply voltages corresponding to a plurality of operating frequencies are performed when the device is powered on by the boot code, which is interpreted as a boot operation of the SoC.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teaching of Parthasarathy by incorporating the teaching of Lai of performing the monitoring during a boot operation. They are all directed toward error correction. As recognized by Lai, AVS scanning or measurement may require a lot of time during amass production and testing process, however, which negatively affects production line operation ([0005]). By performing the test during the initial booting operation, the AVS scanning can be performed on the final product, which can reflect real operation status of the SoC with a higher accuracy ([0015]). Therefore, it would be advantageous to incorporate the teaching of Lai of performing the monitoring during a boot operation for the measurement with the higher accuracy on the final product.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Parthasarathy in view of Ziaja et al. (United States Patent Application Publication US 2010/0332924), hereinafter Ziaja.
Regarding claim 10, Parthasarathy teaches all the limitations of the apparatus of claim 6, as discussed above.
However, Parthasarathy does not teach wherein the one or more monitoring operations comprises a plurality of at-speed scan operations.
Ziaja teaches wherein the one or more monitoring operations comprises a plurality of at-speed scan operations ([0024] “…the testing of memory array to be conducted at-speed, i.e. at the operational clock speed of the memory over a number of clock cycles.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teaching of Parthasarathy by incorporating the teaching of Ziaja of a plurality of at-speed scan operations. They are all directed toward error correction. As recognized by Ziaja, the test output data from scan testing may then be analyzed by a test system to determine whether the particular test passed or failed ([0005]). In may cases, the speed at which scan testing of memory arrays is conducted may be significantly lower than the speed at which the integrated circuit is intended to operate ([0005]). By using the at-speed scan operation, the testing for the operational frequency can be performed, which results in measurements with higher accuracy in an actual operational environment. Therefore, it would be advantageous to incorporate the teaching of Ziaja of a plurality of at-speed scan operations in order to measure with a higher accuracy in an actual operational environment.
Claim(s) 13, 16, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable Parthasarathy in view of Wang.
Regarding claim 13, Parthasarathy teaches an apparatus, comprising: a scan controller having a circuitry configured to: perform a plurality of scan operations on a system on chip (SoC) at a respective plurality of first voltage values to gather first error rates at the respective plurality of first voltage values ([0101] “Blocks 203 to 209 illustrate the sequential read of bit counts (e.g., at a plurality of test voltages CA, ..., CE) ( e.g., ( e.g., VA' ... , VE).” [0052] “the read manager 113 is further configured to classify the error rate in the hard bit data using the measured signal and noise characteristics and selectively determine whether to read the soft bit data and/or whether to transmit the soft bit data to the controller 115 as a response to the read command.” [0059] “the calibration circuit 145 can measure the signal and noise characteristics 139 by reading different responses from the memory cells in a group (e.g., 131, ..., 133) by varying operating parameters used to read the memory cells, such as the voltage(s) applied during an operation to read data from memory cells.” Based on read of bit counts at various the voltages, error rates in hard bit data is determined. Furthermore, as shown in FIG. 1, 2, [0038]-[0041], the memory sub-system includes various integrated circuits within a same package, which is interpreted as a SoC.);
determine estimated second error rates at a respective plurality of second voltage values at which the plurality of at-speed scan operations were not performed ([0103] “As illustrated in FIG. 3, the optimized read voltage can be calculated at block 211 from the bit counts (e.g., CA, .. . , CE). At block 213, the memory device 130 applies the optimized read voltage VO to the group of memory cells (e.g., 131 or 133) to obtain hard bit data that corresponds the states of the memory cells in the group (e.g., 131 or 133) under the applied voltage VO. [0103] “Concurrently with the calculation 211 of the optimized read voltage VO and/or the reading 213 of the hard bit data 177, the memory device 130 classifies or predicts, at block 215, the quality of the hard bit data read based on the calibration performed according to the bit counts measured in operations 203 to 209.” As shown in FIG. 3 and [0103], the optimized read voltage is determined. The optimized read voltage corresponds to a point where predicted or calculated to have lower error rates. Furthermore, as the optimized voltage is calculated instead of being measured, monitoring of the operation at the optimized voltage is not performed.);
generate a first portion of a plot using the gathered first error rates and the respective plurality of first voltage values; generate a second portion of the plot the estimated second error rates and the respective plurality of second voltage values (FIG. 3. FIG. 3 shows the plot with measured points and calculated curve.); and
in response to a first particular voltage value corresponding to a predetermined error rate being determined based on the first portion and second portion of the plot and a particular error rate associated with the particular voltage value, perform one or more operations on the SoC using the determined particular voltage ([0104] “If it is determined, at block 217, to read soft bit data 173, the memory device 130 adjusts the currently applied read voltage on the group of memory cells (e.g., 131 or 133) to adjacent voltages to read soft bit data 173. As illustrated in FIG. 3, the adjacent read voltages (e.g., 181 and 182) are determined based on offsets (e.g., 183 and 184) of the same amount from the optimized read voltage 151. In some implementations, multiple offset amounts are used to generate different sets of offsets to generate soft bit data 173 corresponding to the multiple amounts.” Based on the monitored voltages, which calculates the optimized voltage, the voltage to operate the memory cell, such as read operation, is performed.).
However, Parthasarathy does not teach at-speed scan operations.
Ziaja teaches at-speed scan operations ([0024] “…the testing of memory array to be conducted at-speed, i.e. at the operational clock speed of the memory over a number of clock cycles.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teaching of Parthasarathy by incorporating the teaching of Ziaja of at-speed scan operations. They are all directed toward error correction. As recognized by Ziaja, the test output data from scan testing may then be analyzed by a test system to determine whether the particular test passed or failed ([0005]). In may cases, the speed at which scan testing of memory arrays is conducted may be significantly lower than the speed at which the integrated circuit is intended to operate ([0005]). By using the at-speed scan operation, the testing for the operational frequency can be performed, which results in measurements with higher accuracy in an actual operational environment. Therefore, it would be advantageous to incorporate the teaching of Ziaja of a plurality of at-speed scan operations in order to measure with a higher accuracy in an actual operational environment.
Regarding claim 16, Parthasarathy in view of Ziaja teaches all the limitations of the apparatus of claim 13, as discussed above.
Ziaja further teaches wherein the scan controller is configured to perform at least one of the plurality of at-speed scan operations at a plurality of time periods during operation of the SoC ([0023] “During the actual test operations, the scan enable signal may be de asserted. Test operations involving scan elements 25 may include (after de-asserting the scan enable signal) providing a clock pulse to convey test stimulus data from various ones of scan elements 25 to various logic circuits, and providing another clock pulse to enable various ones of scan elements 25 to capture test result data.” Since Ziaja teaches that at-speed scanning during normal operation, Ziaja suggests that the at-speed scanning is performed at various time periods.).
Regarding claim 19, Parthasarathy in view of Ziaja teaches all the limitations of the apparatus of claim 13, as discussed above.
Parthasarathy, as modified above, further teaches wherein the scan controller is configured to operate autonomously (Parthasarathy suggests that the operations of FIG. 3-FIG. 5 are performed by itself based on the steps.).
Regarding claim 20, Parthasarathy in view of Ziaja teaches all the limitations of the apparatus of claim 13, as discussed above.
Parthasarathy, as modified above, further teaches wherein the scan controller is configured to operate without an intervention of an automatic testing equipment ([0050] “the read manager 113 implemented in the controller 115 can transmit a particular read command that is configured to request the memory device 130 to read soft bit data by boost modulation of voltages applied to read hard bit data. In response to such a read command, the read manager 113 implemented in the memory device 130 is configured to read the hard bit data by applying the optimized read voltage ( e.g., received from the controller 115, determined for the measured signal and noise characteristics, or determined in another way), and read the soft bit data by applying read voltages that are centered at the optimized read voltage with a predetermined offset.” [0053] “FIG. 2 illustrates an integrated circuit memory device 130 having a calibration circuit 145 configured to measure signal and noise characteristics according to one embodiment.” As shown in FIG. 1, the memory sub-system 110 includes memory sub-system controller 115, which further includes a read manager, and an integrated memory device 130, which suggests that an automatic testing equipment is not involved.).
Claim(s) 14, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Parthasarathy in view of Ziaja as applied to claim 13 above, and further in view of Wang.
Regarding claim 14, Parthasarathy in view of Ziaja teaches all the limitations of the apparatus of claim13, as discussed above.
Ziaja teaches at-speed scan operations ([0023] “During the actual test operations, the scan enable signal may be de asserted. Test operations involving scan elements 25 may include (after de-asserting the scan enable signal) providing a clock pulse to convey test stimulus data from various ones of scan elements 25 to various logic circuits, and providing another clock pulse to enable various ones of scan elements 25 to capture test result data.” Since Ziaja teaches that at-speed scanning during normal operation, Ziaja suggests that the at-speed scanning is performed at various time periods.).
However, Parthasarathy in view of Ziaja does not teach to perform additional one or more scan operations to gather third error rates at the respective plurality of first voltage values; and update the plot based on the gathered third error rates.
Wang teaches to perform additional one or more scan operations to gather third error rates at the respective plurality of first voltage values; and update the plot based on the gathered third error rates ([0052] “FIG. 2 depicts a plot 200 at a first time during an operational life of a memory device ( e.g., an SRAM device), such as the memory device 102 of FIG. 1...the first time may correspond to a time during operation (e.g., use) of the memory device, such as after a particular number of power-on operations of the memory device, after error detection/correction circuitry detects an uncorrectable error (e.g., a multi-bit error) during a read operation, after detecting a significant change to one or more characteristics of the memory device, or after some other event during operation of the memory device.” [0056] “FIG. 2 further depicts a plot 220 at a second time (e.g., during a second stage of operation) during the operational life of the memory device (e.g., after a particular number of power cycles of the memory device, after an uncorrectable error occurs, or after occurrence of some other condition, as described above).” After some times of operations, as shown in FIG. 2, the boundary is changed or updated from 212 to 222.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Parthasarathy in view of Ziaja by incorporating the teaching of Wang of performing additional one or more scan operations to gather third error rates at the respective plurality of first voltage values; and update the plot based on the gathered third error rates. They are all directed toward error detection. As recognized by Wang, due to physical wear at the memory device as a result of read and write operations at the memory device, which is degradation due to “aging”, a greater supply voltage may be used (for one or more operating frequencies) to achieve a pass status ([0056]). By performing additional scan operations after some operational life, the degradation due to aging can be corrected, which improves performance of the memory device. Therefore, it would be advantageous to incorporate the teaching of Wang of performing additional one or more scan operations to gather third error rates at the respective plurality of first voltage values; and update the plot based on the gathered third error rates in order to compensate the degradation of the aging.
Regarding claim 15, Parthasarathy in view of Ziaja and further in view of Wang teaches all the limitations of the apparatus of claim 14, as discussed above.
Wang further teaches wherein the scan controller having the circuitry is further configured to: determine a second particular voltage value corresponding to the predetermined error rate based on the first gathered error rates, the second estimated error rates, and the third gathered error rates ([0056] “The previous boundary (e.g., the boundary 212) is shown in the plot 220 to illustrate differences between the previous boundary 212 and the shifted boundary 222… By determining target voltage levels at later stages of operation, degradation due to "aging" (e.g., physical wear over the operational life of the memory device) may be compensated for by increasing a voltage level of the supply voltage (VDD) to a voltage level associated with a pass condition for a particular operating frequency.”).
Regarding claim 18, Parathasarathy in view of Ziaja teaches all the limitations of apparatus of claim 13, as discussed above.
Wang further teaches wherein the predetermined error rate is below a threshold error rate ([0027] “the controller 120 may be configured to determine target voltages for the multiple operating frequencies at various stages of the operational life of the memory array 110, and to adaptively scale the voltage level of the supply voltage (VDD) to a target (e.g., "minimum") voltage level associated with a target reliability level (e.g., a threshold number of errors) for a selected operating frequency.”[0061] “The method 300 further includes, in response to the first number of errors satisfying a threshold, adjusting (e.g., increasing) the supply voltage to a second voltage level that is greater than the first voltage level, at 308.”).
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Parthasarathy teaches calculating an optimized read voltages from bit counts. However, Parthasarathy does not teach “wherein the scan controller is configured to perform at least one of the plurality of at-speed scan operations based on a number of memory accesses in the SoC.”
LI teaches to determining a read voltage from a current read voltage and the corresponding current error rate and last read voltage and a corresponding error rate and calculating a difference of the current error rate and the last error rate to obtain the next read voltage. However, LI does not teach “wherein the scan controller is configured to perform at least one of the plurality of at-speed scan operations based on a number of memory accesses in the SoC.”
Wang teaches determining a number of errors for a plurality of voltages and a plurality of operating frequencies. Wang further teaches to adjust a supply voltage in response to number of errors satisfying a threshold. However, Wang does not teach “wherein the scan controller is configured to perform at least one of the plurality of at-speed scan operations based on a number of memory accesses in the SoC.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
YOO (United States Patent Application Publication US 2019/0267099) teaches to calculate average threshold voltages of the plurality of threshold voltage distributions and set a temporary read voltage corresponding to average threshold voltages of adjacent threshold voltage distribution and calculate an error rate based on a reference value and standard value and set an offset value by reflecting the error rate.
BAZARSKY et al. (United States Patent Application Publication US 2020/0118620) teaches to determine a read threshold voltage scanning order based on parameter associated with flash memory pages.
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