DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending.
Claim Objections
The following claims are objected to because of the following informalities. Appropriate correction is required.
Claim 1 should be amended to “determining, in response to a process being executed, whether a mapping, of [[of]] a target physical address to a virtual address that the process is accessing, is [[is]] stored in a translation lookaside buffer (TLB)”. This is to clarify what (mapping, target physical address, virtual address or process) is stored in TLB (see spec ¶[54]).
Claim 1 should be amended to “obtaining the target physical address, mapped , based [[based]] on accessing the single-level page table”. This is to clarify what (obtaining or mapped) corresponds to accessing single-level page table (see spec Fig. 5 and corresponding paragraphs).
Claim 9 is the electronic device claim corresponding to method claim 1, and is objected on the same grounds as claim 1.
Claim 2 should be amended to “wherein the determining of whether the process uses [[a]] the single-level page table is based on a register bit indicating a type of the process”. This is so that subsequent “the single level page table” is not unclear whether it is referring to the one here or the one in claim 1.
Claim 8 should be amended to “wherein the determining of whether the process uses [[a]] the single-level page table depends on whether the virtual address is in the user space or is in the kernel space”. Since this limitation is further limiting a previous limitation, single-level page table here should be same (and not different) as previously recited single-level page table in which this limitation is further limiting.
Claim 16 is the electronic device claim corresponding to method claim 8, and is objected on the same grounds as claim 8.
Claim 17 should be amended to “determining whether processes executing on the computing device use single-level page tables or whether the processes use multi-level page tables”. This is a typo.
Claim 17 should be amended to “for each process[[ed]] determined to use a multi-level page table, when a requested virtual address is not found in the TLB, using a corresponding multi-level page table to determine the requested virtual address”. This is a typo.
Claim 20 should be amended to “wherein bit values of a page table register are checked, for [[the]] respective processes, to determine which of the processes use a corresponding single-level page table and which of the processes use a corresponding multi-level page table”. This is to correct lack of antecedence basis.
Claims, dependent upon above identified claims, are also objected on the same grounds as said above identified claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Michaud (US 10459852).
Regarding claim 1, Michaud teaches
An operating method of an electronic device (electronic device = Fig. 1 memory management system), the operating method comprising:
determining, in response to a process being executed, whether a mapping of a target physical address to a virtual address that the process is accessing is stored in a translation lookaside buffer (TLB); (claim objection: This limitation should read “determining, in response to a process being executed, whether a mapping, of a target physical address to a virtual address that the process is accessing, is stored in a translation lookaside buffer (TLB)”.) (Michaud teaches responsive to application (process) requesting (executed) access, said application sends virtual address (virtual address) that is used to determine (determining) if a PTE (mapping) exists in a TLB (TLB), in said memory management system (see Fig. 1), where said PTE is found in said TLB and said PTE is used to generate physical address (target physical address) using said virtual address (see Fig. 6, col 11 ln 56 – col 12 ln 10).)
determining, in response to determining that the virtual address is not stored in the TLB, whether the process uses a single-level page table; and (This limitation is not performed because it is recited in a contingent manner. For a method claim, a step is not performed if its condition is not met (see MPEP 2111.04(II). In this instance, determination of single-level page table use is not performed because there is no recitation of virtual address being a miss to TLB occurring. Note that use of “in response to” merely recites a step to be taken as a result of a first condition but does not recite said first condition occurring.) (As noted supra, Michaud teaches a hit to TLB resulting in this limitation not being performed.)
in response to determining that the process uses the single-level page table, obtaining the target physical address mapped to the virtual address based on accessing the single-level page table (This limitation is not performed because it is recited in a contingent manner. For a method claim, a step is not performed if its condition is not met (see MPEP 2111.04(II). Since previous step of determination of single-level page table use does not occur, this limitation that depends on said determination also does not occur. In addition, obtaining of target physical address is also not performed because there is no recitation of single-level page table use occurring. Note that use of “in response to” merely recites a step to be taken as a result of a first condition but does not recite said first condition occurring.)
Regarding claim 4, Michaud teaches the operating method of claim 1 where Michaud also teaches
determining, in response to a second process being executed, whether a mapping of a second target physical address to a second virtual address that the second process is accessing is stored in the TLB; (Michaud teaches there are plural applications (second process) (see col 3 ln 12-13) wherein responsive to second application (second process) requesting (executed) access, said second application sends virtual address (second virtual address) that is used to determine (determining) if a PTE (mapping) exists in a TLB (TLB) where said PTE is found in said TLB and said PTE is used to generate physical address (second target physical address) using said virtual address (see Fig. 6, col 11 ln 56 – col 12 ln 10).)
determining, in response to determining that the second virtual address is not stored in the TLB, whether the second process uses a single-level page table; and (This limitation is not performed because it is recited in a contingent manner. For a method claim, a step is not performed if its condition is not met (see MPEP 2111.04(II). In this instance, determination of single-level page table use is not performed because there is no recitation of virtual address being a miss to TLB occurring (i.e. there is a TLB hit). Note that use of “in response to” merely recites a step to be taken as a result of a first condition but does not recite said first condition occurring.) (As noted supra, Michaud teaches a hit to TLB resulting in this limitation not being performed.)
in response to determining that the second process does not use a single-level page table, obtaining the second target physical address mapped to the second virtual address based on a multi-level page table (This limitation is not performed because it is recited in a contingent manner. For a method claim, a step is not performed if its condition is not met (see MPEP 2111.04(II). Since previous step of determination of single-level page table use does not occur, this limitation that depends on said determination also does not occur. In addition, obtaining of second target physical address is also not performed because there is no recitation of non-single-level page table use occurring. Note that use of “in response to” merely recites a step to be taken as a result of a first condition but does not recite said first condition occurring.)
Claims 17 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Schoinas (US 20060075146).
Regarding claim 17, Schoinas teaches
A method performed by a computing device, the method comprising:
determining whether processes executing on the computing device use single-level page tables or whether they user multi-level page tables; (claim objection: This limitation should read “determining whether processes executing on the computing device use single-level page tables or whether the processes use multi-level page tables”.) (Schoinas teaches receiving, from I/O device, I/O transaction (see Schoinas abstract) with guest physical address and source identifier that is used to identify context entries (see Fig. 5 and corresponding paragraphs), each, with multi-level (M) field 830 (see Fig. 8B, ¶[109-110] indicating whether single-level page table (single-level page tables) or multi-level page table (multi-level page tables) is to be used (see ¶[82]). Schoinas also teaches i) there are plural of said I/O transaction (processes) (see ¶[55]) and ii) using TLB for address translation (see ¶[142]) from guest physical address to host physical address (see ¶[56]).)
for each process determined to use a single-level page table, when a requested virtual address is not found in a translation lookaside buffer (TLB), using a corresponding single-level page table to determine the requested virtual address; and (This limitation is not performed because it is recited in a contingent manner. For a method claim, a step is not performed if its condition is not met (see MPEP 2111.04(II). In this instance, determination of single-level page table use is not performed because there is no recitation of i) virtual address being a miss to TLB occurring and ii) process using single-level page table as occurring.) (As noted supra, Schoinas teaches using TLB for address translation resulting in this limitation not being performed.)
for each processed determined to use a multi-level page table, when a requested virtual address is not found in the TLB, using a corresponding multi-level page table to determine the requested virtual address (This limitation is not performed because it is recited in a contingent manner. For a method claim, a step is not performed if its condition is not met (see MPEP 2111.04(II). In this instance, determination of multi-level page table use is not performed because there is no recitation of i) virtual address being a miss to TLB occurring and ii) process using multi-level page table as occurring.) (As noted supra, Schoinas teaches using TLB for address translation resulting in this limitation not being performed.)
Regarding claim 20, Schoinas teaches the method of claim 17 where Schoinas also teaches
wherein bit values of a page table register are checked, for the respective processes, to determine which of the processes use a corresponding single-level page table and which of the processes use a corresponding multi-level page table (claim objection: This limitation should read “wherein bit values of a page table register are checked, for respective processes, to determine which of the processes use a corresponding single-level page table and which of the processes use a corresponding multi-level page table”) (Schoinas teaches DMA requests (processes, respective process) are processed using default register (page table register) that includes single/multi-level table (M) field (with values of asserted or not) (bit values)) indicating whether to use single-level page table (corresponding single-level page table) or multi-level page table (corresponding multi-level page table) (see Fig. 6, ¶[76], [80], [82]).)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Michaud in view of Kessler (US 6715057).
Regarding claim 5, Michaud teaches the operating method of claim 4 where Michaud also teaches single-level page table (single-level page table) and multi-level page table (multi-level page table) (see Michaud Fig. 3-4 and corresponding paragraphs) but does not appear to explicitly teach said single-level and multi-level page tables having the following characteristic.
wherein a page size of the multi-level page table is less than a page size of the single-level page table
However, Kessler teaches
wherein a page size of [the] multi-level page table is less than a page size of [the] single-level page table (Kessler teaches when page size is above 512MB threshold, eliminating one or more levels of multi-level page table (see col 4 ln 58-66). In exemplary embodiment, three level page table (multi-level) is used for first page size (page size) less than 512MB (see Fig. 4, col 13 ln 39-46) and when second page size is greater than 512MB, said three level page table would be 2-level or 1-level (single-level) page table due to elimination of one or more levels (see col 4 ln 58-66). Note that said first page size (<512MB) is less than (less than) said second page size (>512MB).)
In view of Kessler, Michaud is modified such that said multi-level page table is used for first page size that is less than 512MB and said single level page table is used for second page size that is greater than 512MB.
Michaud and Kessler are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Michaud in the manner described supra because it would avoid mapping duplication of large pages in TLB (Kessler, col 4 ln 14-53).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Michaud in view of Steiss (US 20160170896).
Regarding claim 6, Michaud teaches the operating method of claim 4 where Michaud also teaches multi-level page table (multi-level page table) (see Michaud Fig. 4 and corresponding paragraphs) but does not appear to explicitly teach said multi-level page table having the following characteristic.
wherein each level of the multi-level page table has a page size larger than each level below it
However, Steiss teaches
wherein each level of [the] multi-level page table has a page size larger than each level below it (Steiss teaches page table that is organized as tree with multiple levels where level 1 corresponds to page size (page size) of 512GB (larger) and level 2 (below (below) level 1) corresponds to page size of 64GB (see Steiss abstract, Fig. 4).)
In view of Steiss, Michaud is modified such that said multi-level page table is organized as a tree where level 1 corresponds to page size that is greater than page size of level 2 that is below level 1.
Michaud and Steiss are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Michaud in the manner described supra because it would allow different page sizes to be applied to different applications, resulting in efficient use of memory (Steiss, ¶[37]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Michaud in view of Adams (US 20150032935).
Regarding claim 7, Michaud teaches the operating method of claim 1.
Michaud teaches a base method that accesses TLB in memory management system (electronic device) (see claim 1). The claimed invention improves upon said base method by (see also limitation below).
wherein a virtual address space of the electronic device is divided into a kernel space and a user space, and wherein processes in the kernel space use multi-level page tables and processes in the user space use single-level page tables
This improvement to said base method is an application of known technique from Adams – using single-level page tables for VM/OS and multi-level page tables for VMM. In particular, Adams teaches
wherein a virtual address space of the electronic device is divided into a kernel space and a user space, and wherein processes in the kernel space use multi-level page tables and processes in the user space use single-level page tables (Adams teaches VM/OS (user space) and VMM (kernel space) where said VM/OS uses single-level guest page tables 420 (single-level page tables) and said VMM uses shadow page tables 434 (multi-level page tables) with more (multi-level) or less levels of page tables than said VM/OS (see Fig. 4, ¶[56], [59]). Adams also teaches i) guest virtual address space (virtual address space) allocated (divided) to said VM/OS and said VMM (see Fig. 3, ¶[52]), ii) execution contexts (processes), in said OS (kernel space), maintaining/viewing (use) said guest page tables 420 (see ¶[47]) and iii) said VMM with memory management mechanism that maintains said shadow page tables used (use) in the course of code executed by code execution facilities (processes) in said VMM (see Fig. 5, ¶[79]).)
One of ordinary skill in the art would recognize that this known technique of using a specific page table type for respective processes of VM/OS and VMM can also be applied to Michaud’s memory management system (electronic device), and the result would have been predictable. In this instance, execution contexts (processes), in VM/OS (user space) uses said single-level page tables, and code executed by code execution facilities (processes), in VMM (kernel space), uses plural of said multi-level page tables wherein virtual address space is allocated (divided) to said VM/OS and said VMM. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Adam’s known technique would have yielded i) predictable result of said memory management system with execution contexts (processes), in VM/OS (user space) using said single-level page tables, and code executed by code execution facilities (processes), in VMM (kernel space), using plural of said multi-level page tables wherein virtual address space is allocated (divided) to said VM/OS and said VMM, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Claims 18 – 19 are rejected under 35 U.S.C. 103 as being unpatentable over Schoinas in view of Michaud.
Regarding claim 18, Schoinas teaches the method of claim 17.
Schoinas teaches a base method with TLB (see claim 17). The claimed invention improves upon said base method by (see also limitation below).
using a single-level page table to perform a first update of the TLB to include a mapping of a corresponding requested virtual address
This improvement to said base method is an application of known technique from Michaud – populating TLB with PTE from single-level page table. In particular, Michaud teaches
using a single-level page table to perform a first update of [the] TLB to include a mapping of a corresponding requested virtual address (Michaud teaches upon PTE (mapping), referenced by virtual address (requested virtual address), being found in page table, updating (first update) TLB (TLB) with said PTE (see Fig. 6, col 12 ln 18-18-25) wherein said page table is single-level page table (single-level page table) (see Fig. 3 and corresponding paragraphs).)
One of ordinary skill in the art would recognize that this known technique of populating TLB with PTE of page table can also be applied to populate TLB of Schoinas. In this instance, said TLB is updated with PTE, of single-level page table, corresponding to virtual address. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Michaud’s known technique would have yielded i) predictable result of said TLB being updated with PTE, of single-level page table, corresponding to virtual address, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Regarding claim 19, Schoinas in view of Michaud teach the method of claim 17.
Modified Schoinas teaches a base method with TLB (see claim 18). The claimed invention improves upon said base method by (see also limitation below).
using a multi-level page table to perform a first update of the TLB to include a mapping of a corresponding requested virtual address
This improvement to said base method is an application of known technique from Michaud – populating TLB with PTE from multi-level page table. In particular, Michaud teaches
using a multi-level page table to perform a second update of [the] TLB to include a mapping of a corresponding requested virtual address (Michaud teaches upon PTE (mapping), referenced by virtual address (requested virtual address), being found in page table, updating (second update) TLB (TLB) with said PTE (see Fig. 6, col 12 ln 18-18-25) wherein said page table is multi-level page table (multi-level page table) (see Fig. 4 and corresponding paragraphs).)
One of ordinary skill in the art would recognize that this known technique of populating TLB with PTE of page table can also be applied to populate TLB of modified Schoinas. In this instance, said TLB is updated with PTE, of multi-level page table, corresponding to virtual address. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Michaud’s known technique would have yielded i) predictable result of said TLB being updated with PTE, of multi-level page table, corresponding to virtual address, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Allowable Subject Matter
Claim 2 recites using single-level page table based on a register bit indicating type of process. This subject matter is reflected in its entirety in claim 2.
Schoinas teaches DMA requests (process) are processed using default register (register) that includes single/multi-level table (M) field (bit) which when asserted indicates use of single-level page table (corresponding single-level page table) (see Schoinas Fig. 6, ¶[76], [80], [82]). However, Schoinas does not appear to explicitly teach said M field (bit) indicates type (type) of said DMA requests (process). Therefore, claim 2 is allowable over Schoinas.
Claim 8 recites determination of using single-level page table, for process, is based on whether virtual address is in i) kernel space that uses multi-level page tables or ii) user space that uses single-level page tables. This subject matter is reflected in the following limitations of claims 7 – 8.
wherein processes in the kernel space use multi-level page tables and processes in the user space use single-level page tables (claim 7)
herein the determining of whether the process uses a single-level page table depends on whether the virtual address is in the user space or is in the kernel space
As noted in claim 7, Adams teaches using multi-level page tables in VMM (kernel space) and single-level page tables in VM/OS (user space). However, Adams does not appear to explicitly teach using single-level page table based on whether virtual address is in said VMM or said VM/OS. Therefore, claim 8 is also allowable over Adams.
In addition, Schoinas teaches DMA requests (with guest physical address (virtual address) (see Schoinas ¶[54])) are processed using default register that includes single/multi-level table (M) field which when asserted indicates use of single-level page table (single-level page table) (see Schoinas Fig. 6, ¶[76], [80], [82]). However, Schoinas does not appear to explicitly teach use of said single-level page table is based on whether said guest physical address (virtual address) is in kernel space or user space. Therefore, claim 8 is also allowable over Schoinas.
Claim 9 recites, at least, obtaining target physical address using single-level page table that is determined, upon a miss to TLB, to be used by a process. This subject matter is reflected in the following limitations of claim 9.
determine, in response to determining that the virtual address is not stored in the TLB, whether the process uses a single-level page table; and
in response to determining that the process uses the single-level page table, obtain the target physical address mapped to the virtual address based on accessing the single-level page table
Schoinas teaches processing DMA requests (process) using default register with single/multi-level table (M) field which when asserted indicates use of single-level page table (single-level page table) (see Schoinas Fig. 6, ¶[76], [80], [82]) where Michaud teaches accessing page table in response to a TLB miss for application request (process) (see Michaud Fig. 6 and corresponding paragraphs) wherein said page table is single-level page table (see Michaud Fig. 3 and corresponding paragraphs). While Michaud teaches accessing said single-level page table in response to said TLB miss, Michaud does not appear to explicitly teach specific step of checking whether said single page table is being used by said application request in response to said TLB miss. In other words, Michaud teaches generic single-level page table access in response to a TLB miss whereas the claim requires specifically checking for whether a process uses single-level page table access in response to a TLB miss. Therefore, claim 9 is allowable over prior art of record.
Claims, dependent upon above identified claims, are also allowable over prior art for the same reasons as said above identified claims.
Additional Remarks
In the interest of compact prosecution, claims 1, 4 and 17 should be amended to avoid reciting limitations in a contingent manner (see suggestion below). In the event, Applicant amends the claims to avoid reciting the limitations in a contingent manner, the claims would contain the similar allowable subject matter of claim 9. It is noted that claims 1 and 4 should also include recitation of executing process (second process). In the interest of compact prosecution, in claim 1, “determining, in response to a process being executed, whether a mapping of a target physical address to a virtual address that the process is accessing is stored in a translation lookaside buffer (TLB)” is mapped. However, this limitation is also contingent and thus claim 1 could also be rejected without this limitation being mapped (see Michaud col 12 ln 55-60 virtual address of application (process) is invalid (not executed) due to programming error). Similar remarks apply to claim 4 (“determining, in response to a second process being executed, whether a mapping of a second target physical address to a second virtual address that the second process is accessing is stored in the TLB”) but for second process.
1. An operating method of an electronic device, the operating method comprising:
executing a process;
determining, in response to [[a]] executing the process
determining that the virtual address is not stored in the TLB;
determining, in response to determining that the virtual address is not stored in the TLB, whether the process uses a single-level page table; [[and]]
determining that the process uses the single-level page table; and
in response to determining that the process uses the single-level page table, obtaining the target physical address mapped to the virtual address based on accessing the single-level page table.
4. The operating method of claim 1, further comprising:
executing a second process;
determining, in response to [[a]] executing the second process
determining that the second virtual address is not stored in the TLB;
determining, in response to determining that the second virtual address is not stored in the TLB, whether the second process uses a single-level page table; [[and]]
determining that the second process does not use the single-level page table; and
in response to determining that the second process does not use a single-level page table, obtaining the second target physical address mapped to the second virtual address based on a multi-level page table
17. A method performed by a computing device, the method comprising:
determining that a requested virtual address is not found in a translation lookaside buffer (TLB);
in response to determining that the requested virtual address is not found in the TLB, determining whether processes executing on the computing device use single-level page tables or whether they user multi-level page tables;
determining that a first subset of the processes uses a single-level page table;
for each of the first subset
determining that a second subset of the processes uses the multi-level page table;
for each of the second subset
Conclusion
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/CHIE YEW/ Primary Examiner, Art Unit 2139