DETAILED ACTION
This is in response to the application filed on 11/12/2024 in which claims 1 – 20 are presented for examination.
Status of Claims
Claims 1 – 20 are pending, of which claims 1, 9, and 16 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 306. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 7 – 9, 12, 14 – 16, 18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Harris et al., U.S. Patent Application 2020/0284981 (hereinafter referred to as Harris).
Referring to claim 1, Harris discloses “A first bridge apparatus” (Fig. 3G photonic bridge 300, Fig. 4 photonic modules 22) “comprising: a connector circuit having a first interface to communicate with a processor die and a second interface to communicate with a stack of memory dies” (Fig. 3G couplers 352 connect to processor die 302 and memory die 304. Fig. 1 stacked memory 34 and processor die 30 connecting to photonic modules 22. Note that in Fig. 4 and [0119] dies 440 and 441 are mounted to the same photonic module. Also, “dies 440 and 441 may include, for example, processors or memories”), “wherein the processor die and the stack of memory dies are vertically adjacent to the connector circuit which bridges the processor die and the stack of memory dies” (Fig. 4 photonic modules 22 under the dies 440/441 and the stack of dies 420-422. [0119] stacked memory dies 420-422, “dies 440 and 441 may include, for example, processors or memories”); “a first connector link circuitry coupled to the connector circuit, wherein the first connector link circuitry is to communicate with a third connector link of a second bridge apparatus; and a second connector link circuitry coupled to the connector circuit, wherein the second connector link circuitry is to communicate with a fourth connector link of a third bridge apparatus” (Figs. 5A and 5B photonic module 22 includes switches and connections to other photonic modules. Connections show a first connection between a first photonic module and a second photonic module. Connections also show a second connection between a first photonic module and a third photonic module).
As per claim 4, Harris discloses “the connector circuit of the first bridge apparatus further comprises a router and a switch” (Figs. 5A, 5C, 5D, and 6B photonic modules with switches. [0137] switches, [0109] Optical distribution networks 104 may route optical signals anywhere inside or outside the network. [0117] and [0144] dynamic reconfiguration for routing).
As per claim 7, Harris discloses “the first bridge apparatus further includes one or more of: a cache, a microcontroller, a built-in self-check circuit, a voltage regulator, and/or a power gate” (Fig. 7A photonic substrate with controllers 740 and debugging units 744. [0136] self-check).
As per claim 8, Harris discloses “the first bridge apparatus is coupled with the second bridge apparatus and the third bridge apparatus in a ring configuration or a grid configuration” (Figs. 1, 5B, 6C show grid configuration of photonic modules. [0086] – [0087] “Some multi-node architectures use a ring topology—each processor is in direct communication with two neighboring processors and communication with other processors passes through the neighboring processors. Other multi-node architectures use a star topology—a central hub is responsible for routing core-to-core communications. Yet another multi-node architectures use a multi-cast topology—each processor is in directed communication to several other processors. Some aspects of the photonic communication platforms described herein make them easily adaptable to any one of these architectures (and others)”).
Referring to claim 9, Harris discloses “An apparatus” (Fig. 1 computing system 10) “comprising: a substrate” (Figs. 1, 3I, and 4 shows photonic substrate 20); “processor dies including a first processor die and a second processor die” (Fig. 4 and [0119] stacked memory dies 420-422, “dies 440 and 441 may include, for example, processors or memories”); “stacks of memory dies including a first stack of memory dies and a second stack of memory dies” (Fig. 1 stacked memory 34 and [0088] “Some of the memory nodes include a single memory chip (see for example memory die 32). Other memory nodes include a stacked memory including multiple vertically-stacked memory dies.” See Fig. 1 opposite corner from stacked memory 34 is another stacked memory); “a first bridge apparatus on the substrate; and a second bridge apparatus on the substrate” (Figs. 1 and 4 many photonic modules 22 on the substrate 20), “wherein the first bridge apparatus or the second bridge apparatus comprises: a first connector circuit having a first interface to communicate with the first processor die and a second interface to communicate with a first stack of memory dies” (Fig. 3G couplers 352 connect to processor die 302 and memory die 304. Fig. 1 stacked memory 34 and processor die 30 connecting to photonic modules 22. Note that in Fig. 4 and [0119] dies 440 and 441 are mounted to the same photonic module. Also, “dies 440 and 441 may include, for example, processors or memories”), “wherein the first processor die and the first stack of memory dies are vertically adjacent to the first connector circuit that bridges the first processor die and the first stack of memory dies” (Fig. 4 photonic modules 22 under the dies 440/441 and the stack of dies 420-422. [0119] stacked memory dies 420-422, “dies 440 and 441 may include, for example, processors or memories”); “a first connector link circuitry coupled to the first connector circuit, wherein the first connector link circuitry is to communicate with a first connector link of the second bridge apparatus; and a second connector link circuitry coupled to the first
connector circuit, wherein the second connector link circuitry is to communicate with a second connector link of the second bridge apparatus” (Figs. 6A – 6C show multiple links connecting a photonic module with an adjacent photonic module); “wherein the second bridge apparatus comprises: a second connector circuit having a first interface to communicate with the second processor die and a second interface to communicate with the second stack of memory dies” (Figs. 5B and 6C show many photonic modules coupled to each other. Fig. 3G couplers 352 connect to processor die 302 and memory die 304. Fig. 1 stacked memory 34 and processor die 30 connecting to photonic modules 22. Fig. 1 stacked memory 34 and [0088] “Some of the memory nodes include a single memory chip (see for example memory die 32). Other memory nodes include a stacked memory including multiple vertically-stacked memory dies.” See Fig. 1 opposite corner from stacked memory 34 is another stacked memory. Also Fig. 4 and [0119] stacked memory dies 420-422, “dies 440 and 441 may include, for example, processors or memories”), “wherein the second processor die and the second stack of memory dies are vertically adjacent to the second connector circuit which bridges the second processor die and the second stack of memory dies” (Fig. 4 photonic modules 22 under the dies 440/441 and the stack of dies 420-422. [0119] stacked memory dies 420-422, “dies 440 and 441 may include, for example, processors or memories.” Figs. 5B and 6C show many photonic modules coupled to each other and Fig. 1 shows photonic modules 22 under memory dies and processor dies); “a [third] connector link circuitry coupled to the second connector circuit; and a [fourth] connector link circuitry coupled to the second connector circuit” (Figs. 6A – 6C show multiple links connecting a photonic module with an adjacent photonic module, each photonic module has multiple connector links).
Note, claim 12 recites the corresponding limitations of claim 4. Therefore, the rejection of claim 4 applies to claim 12. Further, Harris discloses “the first connector circuit and the second connector circuit” (Fig. 3G couplers 352 connect to processor die 302 and memory die 304. Fig. 1 stacked memory 34 and processor die 30 connecting to photonic modules 22. Note that in Fig. 4 and [0119] dies 440 and 441 are mounted to the same photonic module. Also, “dies 440 and 441 may include, for example, processors or memories”).
Note, claim 14 recites the corresponding limitations of claim 7. Therefore, the rejection of claim 7 applies to claim 14. Further, Harris discloses “the first bridge apparatus and the second bridge apparatus” (Figs. 1 and 4 many photonic modules 22 on the substrate 20).
Note, claim 15 recites the corresponding limitations of claim 8. Therefore, the rejection of claim 8 applies to claim 15.
Referring to claim 16, claim 1 recites the corresponding limitations as that of claim 16. Therefore, the rejection of claim 1 applies to claim 16.
Further, Harris discloses “An apparatus” (Fig. 1 computing system 10) “comprising: a substrate; and a first bridge apparatus on the substrate” (Figs. 1, 3I, and 4 shows photonic substrate 20. Figs. 1 and 4 many photonic modules 22 on the substrate 20); the first bridge apparatus comprising “a first connector link circuitry coupled to the first connector circuit, wherein the first connector link circuitry is to communicate with a first connector link of a second bridge apparatus; a second connector link circuitry coupled to the first connector circuit, wherein the second connector link circuitry is to communicate with a second connector link of the second bridge apparatus” (Figs. 6A – 6C show multiple links connecting a photonic module with an adjacent photonic module. Any one of the photonic modules has multiple links connecting to another “second” photonic module and also has multiple links connecting to another “third” photonic module); “a third connector link circuitry coupled to the first connector circuit, wherein the third connector link circuitry is to communicate with a first connector link of a third bridge apparatus; and a fourth connector link circuitry coupled to the first connector circuit, wherein the fourth connector link circuitry is to communicate with a fourth connector link of the third bridge apparatus” (Figs. 6A – 6C show multiple links connecting a photonic module with an adjacent photonic module. Any one of the photonic modules has multiple links connecting to another “second” photonic module and also has multiple links connecting to another “third” photonic module).
As per claim 18, Harris discloses “the first connector circuit is to communicate in any orientation from north-to-south or east-to-west” (Figs. 6A – 6C).
Note, claim 20 recites the corresponding limitations of claim 8. Therefore, the rejection of claim 8 applies to claim 20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Harris in view of Liu et al., U.S. Patent Application 2024/0186251 (hereinafter referred to as Liu).
As per claim 2, Harris discloses the bridge apparatus “further comprises pads to connect the processor die and the stack of memory dies, wherein the first bridge apparatus has a top surface and a bottom surface opposite the top surface, wherein the pads are on the top surface” (Figs. 3B, 3C and [0105] electrical connection can be metal pads).
Harris does not appear to explicitly disclose “wherein the bottom surface comprises copper pillars or solder balls to connect to a substrate.”
However, Liu discloses another method for connecting dies to bridges (Fig. 2A dies 230A and 230B connected via bridge 220). Liu discloses the bridge apparatus “further comprises pads to connect the processor die and the” “memory” die (Fig. 2D bridge 220 connecting to dies 230A and 230B, [0033] dies 230A and 230B may both be compute dies, one or both dies may also be memory dies), “wherein the first bridge apparatus has a top surface and a bottom surface opposite the top surface, wherein the pads are on the top surface, wherein the bottom surface comprises copper pillars or solder balls to connect to a substrate” (Fig. 2D top and bottom surface of bridge 220, solder balls on the bottom surface connect to substrate 205).
Harris and Liu are analogous art because they are from the same field of endeavor, which is connecting dies via bridges.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Harris and Liu before him or her, to modify the teachings of Harris to include the teachings of Liu so that a top surface of the bridge connects to the dies with pads and a bottom surface of the bridge connects to a substrate with solder balls.
The motivation for doing so would have been to provide a modular approach, which makes replacement of each bridge easier.
Therefore, it would have been obvious to combine Liu with Harris to obtain the invention as specified in the instant claim.
Note, claim 10 recites the corresponding limitations of claim 2. Therefore, the rejection of claim 2 applies to claim 10. Also, as above, Harris teaches both a first and second bridge (Figs. 1 and 4 many photonic modules 22 on the substrate 20).
It would have been obvious to one of ordinary skill in the art to duplicate the bridges (photonic modules) to be identical.
Claims 3, 5, 11, 13, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Harris in view of Das Sharma et al., U.S. Patent Application 2024/0030172 (hereinafter referred to as Das Sharma).
As per claim 3, Harris does not appear to explicitly disclose “the
connector circuit is a network-on-chip connector circuit.”
However, Das Sharma teaches another bridge apparatus for connecting dies ([0079] processor core die, memory die coupled by interconnect bridges) wherein “the connector circuit is a network-on-chip connector circuit” (Figs. 1 and 2 along with [0029] and [0071] NoC logic to interface with the die-to-die interconnect).
Harris and Das Sharma are analogous art because they are from the same field of endeavor, which is connecting dies.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Harris and Das Sharma before him or her, to modify the teachings of Harris to include the teachings of Das Sharma so that the connector circuit is a network-on-chip connector circuit.
The motivation for doing so would have been to provide a connector circuit that is capable of handling failures (as taught by Das Sharma at [0032]).
Therefore, it would have been obvious to combine Das Sharma with Harris to obtain the invention as specified in the instant claim.
As per claim 5, Harris does not appear to explicitly disclose “the first connector link circuitry and the second connector link circuitry are network-on-chip connector links.”
However, Das Sharma teaches another bridge apparatus for connecting dies ([0079] processor core die, memory die coupled by interconnect bridges) wherein “the first connector link circuitry and the second connector link circuitry are network-on-chip connector links” (Figs. 1 and 2 along with [0029] and [0071] NoC logic to interface with the die-to-die interconnect).
Harris and Das Sharma are analogous art because they are from the same field of endeavor, which is connecting dies.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Harris and Das Sharma before him or her, to modify the teachings of Harris to include the teachings of Das Sharma so that the first connector link circuitry and the second connector link circuitry are network-on-chip connector links.
The motivation for doing so would have been to provide a connector circuit that is capable of handling failures (as taught by Das Sharma at [0032]).
Therefore, it would have been obvious to combine Das Sharma with Harris to obtain the invention as specified in the instant claim.
Note, claim 11 recites the corresponding limitations of claim 3. Therefore, the rejection of claim 3 applies to claim 11. Also, as above, Harris teaches both a first connector circuit and second connector circuit (Fig. 3G couplers 352 connect to processor die 302 and memory die 304. Fig. 1 stacked memory 34 and processor die 30 connecting to photonic modules 22. Note that in Fig. 4 and [0119] dies 440 and 441 are mounted to the same photonic module. Also, “dies 440 and 441 may include, for example, processors or memories”).
Note, claim 13 recites the corresponding limitations of claim 5. Therefore, the rejection of claim 5 applies to claim 13. Also, as above, Harris teaches both a first connector link circuitry and second connector link circuitry (Figs. 6A – 6C show multiple links connecting a photonic module with an adjacent photonic module).
Note, claim 17 recites the corresponding limitations of claim 3. Therefore, the rejection of claim 3 applies to claim 17.
Note, claim 19 recites the corresponding limitations of claim 5. Therefore, the rejection of claim 5 applies to claim 19. Also, as above, Harris teaches a first connector link circuitry, second connector link circuitry, third connector link circuitry, and fourth connector link circuitry (Figs. 6A – 6C show multiple links connecting a photonic module with an adjacent photonic module. Any one of the photonic modules has multiple links connecting to another “second” photonic module and also has multiple links connecting to another “third” photonic module).
Claim 6 rejected under 35 U.S.C. 103 as being unpatentable over Harris in view of Elsherbini et al., U.S. Patent Application 2020/0091128 (hereinafter referred to as Elsherbini).
As per claim 6, Harris discloses “the first interface and the second interface” (Fig. 3G couplers 352 connect to processor die 302 and memory die 304. Fig. 1 stacked memory 34 and processor die 30 connecting to photonic modules 22. Note that in Fig. 4 and [0119] dies 440 and 441 are mounted to the same photonic module) “provide high bandwidth communication” “between the processor die and the stack of memory dies via the connector circuit” (Fig. 1 processor die and stack of memory dies. Abstract “enabling scaling of memory capacity and bandwidth well beyond what is possible with conventional computing systems”).
Harris does not appear to explicitly disclose “high bandwidth communication greater than 1 GHz.”
However, Elsherbini discloses another apparatus with bridges between dies ([0067]) including “high bandwidth communication greater than 1 GHz” ([0026] “the dies 114-3 and 114-5 may operate at high speed signaling frequencies (e.g., high speed signaling frequencies of 50 GHz or greater, or super high speed signaling frequencies of 100 GHz or greater)”).
Harris and Elsherbini are analogous art because they are from the same field of endeavor, which is connecting dies through a bridge.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Harris and Elsherbini before him or her, to modify the teachings of Harris to include the teachings of Elsherbini so that interfaces provide high bandwidth communication greater than 1 GHz.
The motivation for doing so would have been to help achieve reliable attachment of multiple IC dies at a lower cost, with improved power efficiency, with higher bandwidth, and/or with greater design flexibility, relative to conventional approaches (as stated by Elsherbini at [0017]).
Therefore, it would have been obvious to combine Elsherbini with Harris to obtain the invention as specified in the instant claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Applications 20200286814, 20210280518, 20210305133, 20230038892, 20230207445, 20230207565, 20230209800, 20240203968, 20250309126 and Patents 11694940, 11798865, 12432897 teach a bridge device connecting dies above the bridge.
Machine Translation of Korean Patent Application KR 20220090397 A teaches a bridge device connecting dies above the bridge.
U.S. Patent Application 20250253276 teaches multiple bridge devices connected to each other.
U.S. Patent 11036002 is the granted patent to Harris.
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184