DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
No prior art is being applied to the claims, because the prior art does not disclose or make obvious wherein the single-chip microcontroller is connected with an input end of the FPGA; an output end of the FPGA is connected with an input end of the DAC module; an output end of the DAC module is connected with a plurality of input ends of the isolation amplifier circuit; individual output end of the isolation amplifier circuit is connected with individual input end of the differential amplifier module; individual output end of the differential amplifier module is connected with individual input end of the digital power amplifier circuit; an input end of the sensor module is connected with the digital power amplifier circuit; and an output end of the sensor module is connected with the single-chip microcontroller; and the FPGA is configured to output a sine wave signal combined by multiple frequencies in the form of digital signal; the DAC module is configured to convert the digital signal to an analog signal and calculate to obtain a signal source; the signal source is isolated and amplified through the isolation amplifier circuit; the differential amplifier module is configured to adjust a voltage range of the signal source, so that an output voltage range at preceding stage fully matches an input voltage range at following stage; the signal source is subjected to power amplification through a digital power amplifier circuit,” as is currently claimed, in the combination, and as best understood.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
As to Claim 1,
The phrase “the DAC module is configured to convert the digital signal to an analog signal and calculate to obtain a signal source” on lines 2-3 of the last paragraph lacks proper written description. The Examiner acknowledges that a DAC converts an analog signal to a signal, and that applicant expressly claims that above. However, applicant also distinctly claims that the DAC module is configured to calculate to obtain a signal source. Applicant does not reasonably disclose the manner in which the DAC module is configured or otherwise able to perform such a calculation, especially when such a calculation is distinctly recited from any conversion of the digital signal to an analog signal. The original disclosure is completely silent as to the manner in which the DAC is configured to implement such a claim feature, and is completely silent as to what such a calculation would include. The disclosure is further completely silent as to what the signal source is and what its relationship is to the analog signal that the DAC obtains from conversion of the digital signal. A person of ordinary skill in the art would not reasonably recognize that applicant had possession of this claim feature, because such a person would not reasonably recognize the manner in which the DAC is configured to perform such a calculation, or what the relationship is between the signal source and the analog signal.
The phrase “and then outputs a controlled source electrical prospecting signal to the ground through the grounding electrode A and the grounding electrode B in the way of single channel, multi-channel output end in parallel, or multi-channel output end in cascade connection” on the last 4 lines lacks proper written description.
Applicant claims that the controlled source electrical prospecting signal is output to ground in the way of a single channel, multi-channel end in parallel, or multi-channel output end in cascade connection, but where such a feature is indefinite. The original disclosure is completely silent as to the use of all three of these features, as applicant at most shows a cascade configuration, as expressly claimed, between the digital power amplifier and electrodes. The original disclosure is completely silent as to what a single channel or multi-channel output end in parallel is or the manner in which it would be input. A person of ordinary skill in the art would not reasonably recognize the manner in which applicant implements such a feature, especially when a cascade configuration is already claimed and required.
As to Claim 3,
The phrase “a protection module, an independent power supply, a normally open relay; wherein the protection module is configured for protection of overvoltage, overcurrent and overheating; each independent power supply is connected with individual normally open relay; each normally open relay has two groups of normally open contact configured to control switch-on and switch-off in each independent power supply, respectively; each normally open relay is connected with individual digital power amplifier circuit to supply power to the digital power amplifier circuit; an input end of the protection module is connected with the single-chip microcontroller, and an output end of the protection module is connected with the normally open relay” on lines 1 to the end lacks proper written description.
1) Applicant claims a protection module, but where the original disclosure is completely silent as to what this module is or the manner in which it is implemented. The original disclosure does not cite any well-known device as the protection module, nor provide any components of this module to allow a person of ordinary skill in the art any recognize of the manner in which it is implemented to therefore be configured to perform the function as claimed. A person of ordinary skill in the art would not reasonably recognize the manner in which this module is implemented, which therefore lacks proper written description.
2) Applicant claims a “normally open relay,” but the original disclosure is completely silent as to the manner in which this feature is implemented. The Examiner is not raising an issue with regard to a relay, per se, but instead is raising an issue because there is no guidance as to why the relay is “normally open” or why it would not be open. The original disclosure is completely silent both as to the manner in which the relay is implemented, as to why this relay would not be open. Furthermore, applicant claims that each normally open relay has two groups of normally open contact configured to control switch-on and switch-off of each power supply, but where the original disclosure is completely silent as to the manner in which this feature is implemented. A relay cannot reasonably provide “control” of turning on and off a power supply, and applicant does not reasonably explain the manner in which the relays cause such a feature or are controlled to implement such a feature. A person of ordinary skill in the art would not reasonably recognize the manner in which this feature is implemented, which therefore lacks proper written description.
As to Claim 5,
The phrase “wherein in the case that the transmission device outputs in parallel connection of four channel output ends, an output voltage is 100 Vpp, and an output current is above 6 A” on lines 1-3 lacks proper written description.
1) Applicant already claims and requires a cascade connection, but applicant does not disclose the manner in which such a cascade connection and a parallel connection can exist. The original disclosure is completely silent as to the manner in which both connections case exist in the final product, and a person of ordinary skill in the art would therefore not reasonably recognize the manner in which this combination is implemented.
2) The original disclosure is completely silent as to the manner in which any parallel connection is implemented, as the only disclose is of a cascade connection. The amplifiers as disclosed could not reasonably be in parallel, and there is no disclosure as to what applicant does to cause or implement the parallel connection. A person of ordinary skill in the art would therefore not reasonably recognize the manner in which this combination is implemented.
As to Claim 9,
The phrase “the transmission device is also configured to transmit electromagnetic prospecting signal, and generate a non-harmonic controlled source signal with high voltage single frequency, or dual-frequency equal-amplitude or multi-frequency equal-amplitude in electrical prospecting and electromagnetic prospecting” on lines 1 to the end lacks proper written description.
Applicant claims that the transmission device is also configured to transmit electromagnetic prospecting signal, and generate a non-harmonic controlled source signal with high voltage single frequency, or dual-frequency equal-amplitude or multi-frequency equal-amplitude in electrical prospecting and electromagnetic prospecting, but where applicant does not reasonably disclose the manner in which these signals would be generated in addition to the controlled prospecting signal already recited in Claim 1. The original disclosure is completely silent as to the manner in which all signals are generated, in the combination or individually, including what the difference is between the signals, when they would be generated, and by what component or components they would be generated. A person of ordinary skill in the art would not reasonably recognize the manner in which these signals, in combination with the controlled prospecting signal of Claim 1, would be generated. As such, this phrase lacks proper written description.
As to Claim 10,
The phrase “A transmission method for multi-frequency equal-amplitude non-harmonic electrical prospecting signal using the transmission device of claim 1, comprising: (1) initializing the FPGA, and resetting a system clock signal; (2) defining a digital to analog (DA) data output clock and a port type of an output channel configured for data output from the FPGA to the DAC module; (3) defining a frequency control word and a phase control word; (4) defining an accumulator register, a phase register, a read-only memory (ROM); (5) instantiating a lookup table, and storing a data containing signal waveform information into the ROM for subsequent invocation; (6) generating a phase accumulator; accumulating a phase every other clock cycle; and changing, through a button, a value of the frequency control word to control a frequency of a generated signal; (7) generating a lookup table address; invoking the ROM and changing a value of the phase control word through the button to control an initial phase of the generated signal; (8) waiting for a direct digital synthesis (DDS) command; if a conditional statement is judged to be true, outputting a digital signal; if the conditional statement is judged to be false, maintaining a waiting state; and (9) waiting for a digital to analog (DA) clock signal; when a first rising edge of the DA clock signal occurs, collecting the digital signal output in step (8); completing data collection, and converting the digital signal into the analog signal; when a falling edge of the DA clock signal occurs, outputting the analog signal, and completing generation of a sine signal with single frequency or dual-frequency equal-amplitude or multi-frequency equal-amplitude; and if the DA clock signal is not received, the digital signal cannot be collected, and maintaining the waiting state” on lines 1 to the end lacks proper written description.
1) The phrase “defining a frequency control word and a phase control word” lacks proper written description, because the original disclosure is completely silent as to what these features are or the manner in which they are implemented. A person of ordinary skill in the art would not reasonably understand the manner in which these features are defined or what they do and do not include.
2) The phrase “defining an accumulator register, a phase register, a read-only memory (ROM)” lacks proper written description, because the original disclosure is completely silent as to the manner in which these features are defined. The Examiner is not raising an issue of merely providing these elements as structural elements, should that be what applicant intends, but applicant is not merely claiming providing these features and instead is claiming that they are defined. There is no disclosure as to the manner in which they are defined, and a person of ordinary skill in the art would not reasonably recognize the manner in which these features are defined or what they do and do not include.
3) The phrase “generating a phase accumulator; accumulating a phase every other clock cycle; and changing, through a button, a value of the frequency control word to control a frequency of a generated signal” lacks proper written description, because the original disclosure is completely silent as to the manner in which these features are defined. First, and similar to that noted above, the Examiner is not raising an issue of merely providing these elements as structural elements, should that be what applicant intends, but applicant is not merely claiming providing these features and instead is claiming that they are generated. There is no disclosure as to the manner in which they are generated, and a person of ordinary skill in the art would not reasonably recognize the manner in which these features are defined or what they do and do not include. Second, the original disclosure is completely silent as to any frequency control word or the manner in which it is changed. A person of ordinary skill in the art would not reasonably recognize the manner in which such word is changed, including what it is starting from and what it should or needs to become. This phrase therefore lacks proper written description.
As to Claims 2-10,
These claims stand rejected for incorporating and reciting the above rejected subject matter of their respective parent claim(s) and therefore stand rejected for the same reasons.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to Claim 1,
The phrase “the FPGA is configured to output a sine wave signal combined by multiple frequencies in the form of digital signal” on lines 1-2 of the last paragraph is indefinite. A sine wave by itself does not have more than one frequency, as plural signals are necessary for plural frequencies. It is therefore unclear how many sine wave signals are present in the claim. It is further unclear if applicant is claiming that plural sine wave signals, or a sine wave with other signals, are being combined, or if the sine wave signal is the final signal after the combining. Lastly, it is unclear what the relationship is between the sine wave signal and the digital signal. It is unclear if the digital signal is formed from the sine wave signal, combination of signals, or in general how the digital signal is formed.
The phrase “individual output end of the isolation amplifier circuit is connected with individual input end of the differential amplifier module; individual output end of the differential amplifier module is connected with individual input end of the digital power amplifier circuit” on lines 13-15 is indefinite.
1) At issue here is that the use of the term “individual” is unclear in light of the disclosure. In applicant’s disclosure, there are four outputs from the isolation amplifier (4) that are connected to four inputs for the differential amplifier (5). The term “individual” reasonably implies an intent for there to be more than one respective input and output in the above phrase, especially in light of the fact that there are plural inputs and outputs for the above amplifiers. However, reciting the term “individual” does not necessarily require more than one input or output, thus raising an issue of indefiniteness, in that the difference between merely reciting an output versus an individual output, and the difference between merely reciting an input versus an individual input, are unclear in light of the disclosure. It is unclear if applicant intends for the above elements to have plural inputs and outputs, and where respective individual outputs of the isolation amplifier are connected to respective individual inputs of the differential amplifier, or if applicant intends to only claim one input and one output. For the purpose of compact prosecution, the Examiner is interpreting the above phrase to require plural outputs from the isolation amplifier and plural inputs of the differential amplifier, such that “individual” ones of the plural outputs are respectively connected to “individual” ones of the plural inputs of the amplifiers.
2) The same issue exists with the phrase “individual output end of the differential amplifier module is connected with individual input end of the digital power amplifier circuit,” and thus the above explanation is equally applied to this phrase, including the manner in which it is being interpreted.
The phrase “the DAC module is configured to convert the digital signal to an analog signal and calculate to obtain a signal source” on lines 2-3 of the last paragraph is indefinite. The Examiner acknowledges that a DAC converts an analog signal to a signal, and that applicant expressly claims that above. However, applicant also distinctly claims that the DAC module is configured to calculate to obtain a signal source. To that extent, the difference and relationship between the analog signal and the signal source is unclear. If it is unclear, in light of the disclosure, if the analog signal is the signal source, or if these are two distinct signals. It is further unclear if the analog signal is used in some manner to obtain the signal source, or how these two signals are related.
The phrase “the differential amplifier module is configured to adjust a voltage range of the signal source, so that an output voltage range at preceding stage fully matches an input voltage range at following stage” on lines 4-7 of the last paragraph is indefinite. Applicant claims that the above amplifier adjusts a voltage range of the signal source such that an output voltage range at preceding stage fully matches an input voltage range at following stage; however, it is unclear what preceding and following stage this phrase is referencing, and it is unclear how any stage can have an output or input voltage range. A stage must be made up structure features in order to have a voltage or voltage range, but these stages are being completely distinctly recited from any structural feature of the claim. It is unclear if these stages are intended to include any of the structural features of the claim, and it is unclear how they are related to any of the structural features now claimed. Similarly, it is unclear how the voltage ranges relate to any of the structural features of the claim, as these too are being distinctly recited from any structural feature.
The phrase “the signal source is subjected to power amplification through a digital power amplifier circuit” on lines is indefinite. Applicant claims that the signal source is subjected to power amplification through a digital power amplifier circuit, but applicant previously claims a digital power amplifier circuit. As best understood, these circuits refer to the same circuits from the disclosure, but are being distinctly recited when they are not distinct.
The phrase “and then outputs a controlled source electrical prospecting signal to the ground through the grounding electrode A and the grounding electrode B in the way of single channel, multi-channel output end in parallel, or multi-channel output end in cascade connection” on the last 4 lines is indefinite.
1) It is unclear what outputs a controlled source electrical prospecting signal from the above claim. It is unclear if it is the power amplifier circuit or another component. Applicant does not state any device is configured to provide this output, and it is unclear how it relates to the previously recited features.
2) Applicant is positively reciting that the signal source is actually output, which amounts to a method step of outputting the signal. As explained in MPEP 2173.05(p)(II), method steps of using an apparatus inside an apparatus claim are indefinite.
3) Applicant claims that the controlled source electrical prospecting signal is output to ground in the way of a single channel, multi-channel end in parallel, or multi-channel output end in cascade connection, but where such a feature is indefinite. The original disclosure is completely silent as to the use of all three of these features, and it is unclear what applicant means by each of these options or what the metes and bounds are for each of these options. Furthermore, applicant already claims that the power amplifier is in a cascade configuration with the grounding electrodes A and B, and thus placing any signal into the digital power amplifier circuit would necessarily require a cascade mode of operation. As such, it is unclear how a single channel or multi-channel end in parallel could exist. Furthermore, it is unclear what applicant means by a single channel or multi-channel in parallel feature. No feature generating the prospecting signal is single channel or multi-channel in parallel, and thus it is unclear what applicant means by these features or what the metes and bounds are for these features. Lastly, applicant is claiming the above cascade connection distinctly from the cascade connection already claimed, and as best understood, these two features refer to the same feature of the disclosure but are being distinctly recited. The difference and relationship between the distinctly recited cascade connections are therefore unclear.
As to Claim 3,
The phrase “a protection module, an independent power supply, a normally open relay; wherein the protection module is configured for protection of overvoltage, overcurrent and overheating; each independent power supply is connected with individual normally open relay; each normally open relay has two groups of normally open contact configured to control switch-on and switch-off in each independent power supply, respectively; each normally open relay is connected with individual digital power amplifier circuit to supply power to the digital power amplifier circuit; an input end of the protection module is connected with the single-chip microcontroller, and an output end of the protection module is connected with the normally open relay” on lines 1 to the end is indefinite.
1) The phrase “a normally open relay” is indefinite, because it is unclear when this relay would and would not be open, and it is unclear what the term “normally” refers to in light of the disclosure. The original disclosure is completely silent as to what would cause this relay to be open, or not, and thus a person of ordinary skill in the art would not reasonably recognize the metes and bounds for what a normally open relay would and would not include. The same issue exists with regard to a “normally open contact.”
2) Applicant claims “each normally open relay” and “each independent power supply,” thereby implying that more than one of each of these features is present in the claim. However, only one independent power supply and normally open relay have been positively introduced, making it unclear how many relays and power supplies are or are not required in the claim.
As to Claim 4,
The phrase “wherein in the case that the transmission device outputs in cascade connection of four channel output ends, an output voltage is 400 peak-to-peak voltage (Vpp), and an output current is above 1.5 A” on lines 1-3 is indefinite.
1) Applicant claims that the output is in “cascade connection of four channel output ends,” but where this feature is completely distinctly recited from the previous cascade connection, which did not claim four channel output ends. The difference and relationship between this feature and the previously recited cascade connection are unclear.
2) Applicant claims “an output voltage” and “an output current,” but where these features are completely distinctly recited from the previous prospecting signal. It is unclear what feature outputs these signals, it is unclear how they are related to each other, in that they are distinctly recited and applicant does not reasonably explain how these two signals are generated, and it is unclear how this voltage and current are related to the prospecting signal. It is unclear if the prospecting signals includes this current and voltage, or if it is distinct from these features.
As to Claim 5,
The phrase “wherein in the case that the transmission device outputs in parallel connection of four channel output ends, an output voltage is 100 Vpp, and an output current is above 6 A” on lines 1-3 is indefinite.
1) Applicant claims that the output is in “parallel connection of four channel output ends,” but where this feature is completely distinctly recited from the previous cascade connection, which would therefore preclude a parallel connection. The difference and relationship between this feature and the previously recited cascade connection are unclear.
2) Applicant claims “an output voltage” and “an output current,” but where these features are completely distinctly recited from the previous prospecting signal. It is unclear what feature outputs these signals, it is unclear how they are related to each other, in that they are distinctly recited and applicant does not reasonably explain how these two signals are generated, and it is unclear how this voltage and current are related to the prospecting signal. It is unclear if the prospecting signals includes this current and voltage, or if it is distinct from these features.
As to Claim 6,
The phrase “the single-chip microcontroller adopts an STM32F103ZET6 chip; the FPGA adopts an EP4CE10E22C8N chip; the DAC module adopts a main chip of AD9767ASTZ; a main chip of the isolation amplifier circuit is ISO124U; and a model of the digital power amplifier circuit is TDA8920CTH” on lines 1-5 is indefinite.
1) Applicant claims that the above features “adopts” the above STM32F103ZET6, EP4CE10E22C8N, or AD9767ASTZ, but where the use of the term “adopts” is unclear. It is unclear if this term means that each of the above figures “is” the chips recited, or merely includes these chips.
2) Applicant claims “a model of the digital power amplifier circuit,” making it unclear if applicant is referring to a model number, or a model representation of the circuit, such as a computer model. It is unclear what model this phrase is referencing.
As to Claim 9,
The phrase “the transmission device is also configured to transmit electromagnetic prospecting signal, and generate a non-harmonic controlled source signal with high voltage single frequency, or dual-frequency equal-amplitude or multi-frequency equal-amplitude in electrical prospecting and electromagnetic prospecting” on lines 1 to the end is indefinite.
1) Applicant claims that the transmission device is also configured to transmit electromagnetic prospecting signal, but where applicant already claims that the transmission device is configured to generate a controlled source electrical prospecting signal. Applicant does not reasonably disclose the difference between these signals, and the difference and relationship between these signals are unclear. As best understood, applicant’s disclosure of a generating of the controlled prospecting signal would include any signal generated by the system for prospecting, and thus, it is unclear what the above electromagnetic prospecting signals is and how it is related to the controlled prospecting signal already claimed.
2) Similarly, the difference and relationship between each of the above signals and the previously recited prospecting signal is unclear. Applicant does not reasonably explain the difference between the signals, and it is unclear whether these signals are distinct or the same as the initially recited controlled prospecting signal.
3) Applicant does not reasonably explain the difference between each of the above signals, and it is unclear what a non-harmonic prospecting signal, what an electromagnetic prospecting signal, dual-frequency equal-amplitude or multi-frequency equal-amplitude in electrical prospecting and electromagnetic prospecting is or how each signals should be interpreted. It is unclear what types of signals would and would not be considered the above claimed signals.
As to Claim 10,
The phrase “A transmission method for multi-frequency equal-amplitude non-harmonic electrical prospecting signal using the transmission device of claim 1, comprising: (1) initializing the FPGA, and resetting a system clock signal; (2) defining a digital to analog (DA) data output clock and a port type of an output channel configured for data output from the FPGA to the DAC module; (3) defining a frequency control word and a phase control word; (4) defining an accumulator register, a phase register, a read-only memory (ROM); (5) instantiating a lookup table, and storing a data containing signal waveform information into the ROM for subsequent invocation; (6) generating a phase accumulator; accumulating a phase every other clock cycle; and changing, through a button, a value of the frequency control word to control a frequency of a generated signal; (7) generating a lookup table address; invoking the ROM and changing a value of the phase control word through the button to control an initial phase of the generated signal; (8) waiting for a direct digital synthesis (DDS) command; if a conditional statement is judged to be true, outputting a digital signal; if the conditional statement is judged to be false, maintaining a waiting state; and (9) waiting for a digital to analog (DA) clock signal; when a first rising edge of the DA clock signal occurs, collecting the digital signal output in step (8); completing data collection, and converting the digital signal into the analog signal; when a falling edge of the DA clock signal occurs, outputting the analog signal, and completing generation of a sine signal with single frequency or dual-frequency equal-amplitude or multi-frequency equal-amplitude; and if the DA clock signal is not received, the digital signal cannot be collected, and maintaining the waiting state” on lines 1 to the end is indefinite.
1) Applicant claims “A transmission method for multi-frequency equal-amplitude non-harmonic electrical prospecting signal using the transmission device of claim 1,” but where such a phrase is distinctly recited from the controlled prospecting signal of Claim 1. The difference and relationship between the above multi-frequency equal-amplitude non-harmonic electrical prospecting signal and the controlled prospecting signal of Claim 1 is unclear, in that it is unclear if these are distinct signals or the same signal. It is further unclear what would and would not be considered a multi-frequency equal-amplitude non-harmonic electrical prospecting signal as claimed, as the original disclosure does not reasonably provide guidance as to what this signal is.
2) The phrase “resetting a system clock signal” is indefinite, because it is distinctly recited from any of the features incorporated from Claim 1, which reasonably include all structural features of the device. It is therefore unclear what clock signal this phrase is referencing and how it relates to any of the structural features of the claim.
3) The phrase “defining a digital to analog (DA) data output clock and a port type of an output channel configured for data output from the FPGA to the DAC module” is indefinite, because it is distinctly recited from any of the features incorporated from Claim 1, which reasonably include all structural features of the device. It is therefore unclear what clock signal this phrase is referencing and how it relates to any of the structural features of the claim. Furthermore, it is unclear what is configured for data output, as it is unclear if applicant is claiming that an output of the FPGA is being configured as claimed or another feature from another component.
4) The phrase “defining a frequency control word and a phase control word” is indefinite, because it is unclear what each of these words are or what they do and do not include. Applicant provides no guidance or explanation as to what these features are how applicant implements them to reasonable establish the metes and bounds for these terms.
5) The phrase “defining an accumulator register, a phase register, a read-only memory (ROM)” is indefinite. Registers and memory are physical objects, and thus these features either do or do not exist with regard to the invention. It is unclear what applicant means by claiming that they are “defined,” in that it is unclear what a process of defining these features would and would not include. It is further unclear if these features are physically required in the claim, or if they need only be designed in a computer to be considered to be “defined.”
6) The phrase “instantiating a lookup table, and storing a data containing signal waveform information into the ROM for subsequent invocation” is indefinite. First, it is unclear what applicant means by this phrase, as it is unclear what instantiating means in the context of the claim. It is unclear if applicant means initializing, creating, or some other feature with regard to the lookup table. Second, the above signal waveform is unclear, because as best understood, this waveform would be the sine wave signal already recited in Claim 1, but where these features are distinctly recited where they are not distinct. The difference and relationship between these features are therefore unclear.
7) The phrase “generating a phase accumulator; accumulating a phase every other clock cycle; and changing, through a button, a value of the frequency control word to control a frequency of a generated signal” is indefinite. First, and similar to that noted above, it is unclear what applicant means by generating a phase accumulator. A phase accumulator is either present or not, and it is unclear if this phrase is intended to mean providing the accumulator or generating by way of a model. Second, it is unclear how the accumulating step is related to the generated accumulator. Applicant does not claim that any accumulating is done with the accumulator, and instead distinctly recites this features. As such, the difference and relationship between these features are unclear. Third, the difference and relationship between the above generated signal and an of the previously recited signals are unclear. It is unclear, for example, if the generated signal is the controlled prospecting signal, and if now, how the signals are related.
8) The phrase “generating a lookup table address; invoking the ROM and changing a value of the phase control word through the button to control an initial phase of the generated signal” is indefinite. First, similar to that noted above, it is unclear what applicant means by generating a lookup table address. A lookup table address is either present or not, and it is unclear if this phrase is intended to mean providing the lookup table address or generating it by way of a model. Second, the difference and relationship between the above lookup table address and the previously recited lookup table are unclear. It is unclear if the address is in or part of the previously recited table, or if it is elsewhere located or otherwise distinct.
9) The phrase “waiting for a direct digital synthesis (DDS) command; if a conditional statement is judged to be true, outputting a digital signal; if the conditional statement is judged to be false, maintaining a waiting state” is indefinite. First, it is unclear how the above command relates to any of the previously recited structural features, or, in short, where this signal comes from. While method claims do not have to recite any structure, applicant has recited structure, such as the single-chip microcontroller of Claim 1. When a device has been recited that would generate the above command, it is indefinite to distinctly recite these features as the difference and relationship between these features becomes unclear. To that extent, it is further unclear what generates the above command, what performs the judging as claimed. Second, applicant claims the outputting of a digital signal, but where such a signal was already recited in Claim 1. It is unclear if these digital signals are the same signal, and if so, it is indefinite to distinctly recite the signals. The difference and relationship between these digital signals are therefore unclear.
10) The phrase “(9) waiting for a digital to analog (DA) clock signal; when a first rising edge of the DA clock signal occurs, collecting the digital signal output in step (8); completing data collection, and converting the digital signal into the analog signal; when a falling edge of the DA clock signal occurs, outputting the analog signal, and completing generation of a sine signal with single frequency or dual-frequency equal-amplitude or multi-frequency equal-amplitude; and if the DA clock signal is not received, the digital signal cannot be collected, and maintaining the waiting state” is indefinite. First, more than one digital signal was previously recited, and it is therefore unclear what digital signal this phrase is referencing. Second, it is unclear how any of the above claim features, such as the collecting, converting, and generation claim features relate to those similar features or the structural features of Claim 1. For example, applicant claims converting the digital signal into the analog signal, but applicant claims this distinctly from the DAC of claim 1. However, such a conversion would reasonable be performed by the DAC, rendering the difference and relationship between these features unclear. It is unclear how any of the above claim features are related to the already recited structural features of Claim 1. Second, the phrase “a sine signal with single frequency or dual-frequency equal-amplitude or multi-frequency equal-amplitude” is indefinite, but a sine signal and each of these other features have already been recited in Claim 1. The difference and relationship between the above features and the similarly but distinctly recited versions in Claim 1 area unclear.
As to Claims 2-10,
These claims stand rejected for incorporating and reciting the above rejected subject matter of their respective parent claim(s) and therefore stand rejected for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The closest prior art reference is US 2022/0187488 to FU et al., which discloses the generation of an electrical prospecting signal using isolated circuits, power amplification circuits connected in cascade and subsequently connected to electrodes, and a single-chip microcomputer or FPGA used to generate an initial signal. However, this reference does not disclose the single-chip microcontroller is connected with an input end of the FPGA; an output end of the FPGA is connected with an input end of the DAC module; an output end of the DAC module is connected with a plurality of input ends of the isolation amplifier circuit; individual output end of the isolation amplifier circuit is connected with individual input end of the differential amplifier module; individual output end of the differential amplifier module is connected with individual input end of the digital power amplifier circuit; an input end of the sensor module is connected with the digital power amplifier circuit; and an output end of the sensor module is connected with the single-chip microcontroller; and the FPGA is configured to output a sine wave signal combined by multiple frequencies in the form of digital signal; the DAC module is configured to convert the digital signal to an analog signal and calculate to obtain a signal source; the signal source is isolated and amplified through the isolation amplifier circuit; the differential amplifier module is configured to adjust a voltage range of the signal source, so that an output voltage range at preceding stage fully matches an input voltage range at following stage; the signal source is subjected to power amplification through a digital power amplifier circuit, in the combination, and thus does not disclose the claim features.
Attention is also drawn to CN205643734 to Cheng et al. which also discloses a circuit that generates an electrical prospecting signal, including a high voltage signal source, a front amplifying circuit, a signal processing circuit, a single chip, a latch, a relay group and a plurality of ground electrodes, amplifying circuit, signal processing circuit, but which fails to include the above noted claim feature, in the combination as claimed.
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DAVID M. SCHINDLER
Primary Examiner
Art Unit 2858
/DAVID M SCHINDLER/Primary Examiner, Art Unit 2858
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