DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “separate printed circuit board electrically connected to the exposed portion of some of the fingers” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. The separate printed circuit board referenced with number 200 does not touch the exposed portions of the fingers in for example figures 2 & 3.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over applicant cited Zaderej et al (WO2018/009554)1 in view of Takiar et al (US2012/0164828).
A smart connector (¶0077 “Smart High or Low-Side Power Switches”) comprising:
an Application Specific Electronics Packaging device (¶0044 “manufactured using an Application Specific Electronics Packaging ("ASEP") system and method”, component 10) comprising a plurality of fingers (e.g.: 34, 56, 134, 234, 256, 334 and others), a substrate overmolded (Abstract sentences 6 & 7) onto the fingers (figures 7 & 8 fingers 357, 358 molded into 390, 338 & 396), the substrate having a plurality of openings provided therethrough forming exposed portions of the fingers (¶0012 “each lead frame defining an opening and having at least one finger which extends into the opening”, ¶0047 next to last sentence), electroplated traces (“electroplating process not only electroplates the traces 46/conductive traces 48 to form electronic circuit traces 50”) on the substrate which are electrically coupled to the exposed portions (figures 2, 2C/D/E/F), and at least one electrical component mounted on the substrate and electrically coupled to the traces (figures 2I at 86); and
a separate printed circuit board electrically connected to the exposed portion of some of the fingers of the Application Specific Electronics Packaging device, the separate printed circuit board having electrical components configured to control functionality of the at least one electrical component of the Application Specific Electronics Packaging device or having electrical components configured to modify properties of the at least one electrical component of the Application Specific Electronics Packaging device.
Zaderej does not disclose the separate PCB connected to exposed portions of some of the fingers.
Takiar discloses a separate printed circuit board (circuit board stacking in figures 4, 5 & 16, ¶0044 1st sentence, ¶0049 “stacked”) electrically connected to the exposed portion of some of the fingers (114) of the Application Specific Electronics Packaging device (Zaderej discloses the ASEP), the separate printed circuit board having electrical components (¶0051 2nd sentence) configured to control functionality of the at least one electrical component of the Application Specific Electronics Packaging device (¶0007 ¶0021 used to control “host” devices) or having electrical components configured to modify properties of the at least one electrical component of the Application Specific Electronics Packaging device.
At the time the invention was made it would have been well known to one of ordinary skill in the electrical connector art to upgrade the capacity of the ASEP device of Zaderej by stacking another PCB onto the die and fingers of Zaderej as taught by Takiar. An advantage for this combination would be to enable high-density, compact designs, that reduces electromagnetic interference (EMI), and improves overall signal integrity. This combination follows the KSR case law rationale A; combining prior art elements according to known methods to yield predictable results.
Claim 6 Zaderej discloses the smart connector as defined in claim 1, wherein the at least one electrical component on the Application Specific Electronics Packaging device comprises a field effect transistor (¶0077).
Claim 7 Zaderej discloses the smart connector as defined in claim 6, wherein the at least one electrical component of the Application Specific Electronics Packaging device further comprises a current sensor (¶0044).
Claim 8 Zaderej discloses the smart connector as defined in claim 1, further comprising a housing (375) in which the Application Specific Electronics Packaging device and the printed circuit board are mounted (fig. 9).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Zaderej et al (WO2018/009554) in view of Takiar et al (US2012/0164828).
Neither Zaderej nor Takiar disclose that the separate printed circuit board is replaceable by another circuit board.
At the time the invention was made it would have been well known to one of ordinary skill to replace or change out the circuit board of Zaderej/Takiar with another circuit board. A motivation for this would be to replace a faulty board.
This combination follows the KSR case law rationale B; simple substitution of one known element for another to obtain predictable results.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Zaderej et al (WO2018/009554) in view of Takiar et al (US2012/0164828).
Zaderej discloses that the ASEP device comprises an FET (¶0077). There is no disclosure in either Zaderej or Takiar that the components on the separate PCB comprise a micro controller and a communication protocol.
At the time the invention was made it would have been well known to one of ordinary skill to include components on the PCB like a micro controller and a communication protocol. The motivation for this combination would be to increase functionality of the device. This combination follows the KSR case law rationale C; use of known technique to improve similar devices (methods, or products) in the same way.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Zaderej et al (WO2018/009554) in view of Takiar et al (US2012/0164828).
Zaderej does not disclose that the at least one electrical component on the ASEP device comprises a communication frontend device like an RJ connector. Takiar does not disclose that the electrical components on the separate printed circuit board comprises a micro controller unit.
At the time the invention was made it would have been well known to one of ordinary skill to include well known components on either or both the ASEP device or the separate PCB. A motivation for this would be to increase functionality of the invention by allowing it to be used in various situations.
This combination follows the KSR case law rationale B; simple substitution of one known element for another to obtain predictable results.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Zaderej et al (WO2018/009554) in view of Takiar et al (US2012/0164828).
Zaderej does not disclose that the ASEP device comprises a motor driver. There is also no disclosure in either Zaderej or Takiar that the components on the separate PCB comprise a micro controller and a communication protocol.
At the time the invention was made it would have been well known to one of ordinary skill to include components on the PCB like a motor driver and on the separate PCB a micro controller and a communication protocol. The motivation for this combination would be to increase functionality of the device. This combination follows the KSR case law rationale C; use of known technique to improve similar devices (methods, or products) in the same way.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Zaderej et al (WO2018/009554) in view of Takiar et al (US2012/0164828).
Neither Zaderej nor Takiar disclose a plurality of ASEP devices are electrically connected to the printed circuit board.
At the time the invention was made it would have been well known to one of ordinary skill to connect a plurality of ASEP devices to the printed circuit board. A motivation for this combination would be to increase functionality of the device. Long standing case law has stated that it has been held that a mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michael C Zarroli whose telephone number is (571)272-2101. The examiner can normally be reached Monday-Friday 9-5 ET IFP.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ramon Mercado can be reached at 5712705744. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MICHAEL C. ZARROLI
Primary Examiner
Art Unit 3658B
/MICHAEL C ZARROLI/Primary Examiner, Art Unit 3658 /M.C.Z/Primary Examiner, Art Unit 3658
1 This reference was published one year and 11 days before the earliest priority date of the instant application. This reference has common inventors and assignee.