Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This is the initial office action based on the application filed on November 13rd, 2024, which claims 1-10 are presented for examination.
Status of Claims
3. Claims 1-10 are pending, of which claims, of which claim 1is in independent form.
Priority
4. This application is a DIV of 17/738,324 05/06/2022 PAT 12190101
17/738,324 is a CIP of 17/136,480 12/29/2020 PAT 11681514
The Office's Note:
5. The Office has cited particular paragraphs / columns and line numbers in the reference(s) applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim(s), other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the cited passages as taught by the prior art or relied upon by the Examiner.
Allowable Subject Matter
6. Claim 9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
7. Claims 1-8 and 10 rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
Claim 1 recites expanding a predetermined algorithm embedded in a firmware in the flash chip into the RAM; calculating, by the expanded predetermined algorithm, a number of available cluster spaces in at least one flash sector; and erasing the at least one flash sector upon the number of available cluster spaces being smaller than an erase threshold.
The limitations above are processes that under the broadest reasonable interpretation fall into the “mathematical concepts” and “mental processes” grouping of abstract ideas –“concepts performed in the human mind by observation, evaluation, judgement, and opinion”, see MPEP 2106.04 (a)(2) (III).
This judicial exception is not integrated into a practical application because the additional elements of “a mouse chip, a flash chip, a flash controller and a RAM” are not indicative of integration into a practical application since they are recited at a high level of generality. Additionally, these additional elements amount to no more than mere instructions to implement the abstract idea on a computer and merely use a computer as a tool to practice the judicial exception. Even when viewed in combination, these additional elements are still mere instructions to implement the judicial exception.
The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception for the same reasons as presented above. The claims as a whole describe how to apply the concept of experimental parameter testing and business indicators using ““a mouse chip, a flash chip, a flash controller and a RAM”, which are generic computer components, to apply the abstract idea on a computer. Moreover, the additional elements of are known and conventional computing elements as evidenced by the spec at para 0023-0039---describing these elements at a high level of generality. Even when considered in combination, these additional elements represent mere instructions to implement an abstract idea or other exception on a computer, which do not provide an inventive concept. Therefore, the claims are ineligible.
Dependent claims 2-8 and 10 recite additional details that further narrow the previously recited abstract idea. There are no additional elements that are indicative of integration into a practical application; nor are there additional elements that amount to significantly more that the judicial exception. Thus, even when viewed as a whole, nothing in the claims adds significantly more to the abstract idea. Therefore, the claims are ineligible.
Claim Rejections - 35 USC § 102
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Niijima et al. (US 5598370).
Claim 1 is rejected, Niijima teaches an operating method of a mouse chip, the mouse chip comprising a flash chip, a flash controller and a random access memory (RAM), the operating method comprising (Niijima, abstract and summary):
expanding a predetermined algorithm embedded in a firmware in the flash chip into the RAM (Niijima, US 5598370, column 1, line 53 to 65, When the block erase type flash memory is used for a solid state file, it is convenient to memory management if the size of a block is made equal to a sector, which is a unit of access in the magnetic disk apparatus. European Patent. Application 392895, for example, discloses a flash EEPROM system of the sector erase type. The system makes it possible to simultaneously erase any plural sectors by providing a latch for each sector, which is a unit of erasure, and setting a latch corresponding to a sector to be erased. Also known is a flash memory whose unit of erasure is a block having a size equivalent to a plurality of sectors (e. g. 4K bytes). This is sometimes called the cluster erase type to distinguish it from the sector erase type.);
calculating, by the expanded predetermined algorithm, a number of available cluster spaces in at least one flash sector(Niijima, column 5, line 43 to 55, A logical set is created for which actual erasure is performed, and which is called a cluster. The cluster consists of one or more blocks each of which is a physical erasure unit. In the embodiment, eight sectors constitute one block, and eight blocks constitute one cluster. Each cluster is provided with a cluster information sector which holds areas for the cluster erase count and sequence number. The cluster erase count and the sequence number are saved as part of the management information in the cluster information sector. In the embodiment, a sector positioned at the top physical address of each cluster is assigned to the cluster information sector. Column 5, line 66 to column 6, line 4. Niijima, column 6, line 37 to 56.); and
erasing the at least one flash sector upon the number of available cluster spaces being smaller than an erase threshold (Niijima, column 6, line 37 to 56, The operation of the controller 30 in erasing a cluster (FIG. 4) will be explained by referring to FIG. 8. First, a cluster to be erased is determined. Although there are various methods, it is usual to determine a cluster as the one to be erased when the number of valid sectors for that cluster gets below a fixed value (step 80). If the cluster to be erased is X, the controller copies the valid data of X to a data sector in another cluster (step 81).).
Claim 2 is rejected for the reasons set forth hereinabove for claim 1, Niijima teaches the operating method as claimed in claim 1, wherein the RAM is an independent RAM or a cache memory (Niijima, column 5, line 25 to 35, FIG. 4 shows a schematic configuration of the SSF 20. The SSF 20 comprises a controller 30 connected to the family bus 18, and an internal bus 31 consisting of a random access memory (RAM) 32, a bus control element 33 and a flash memory 34. The RAM 32 includes an area 35 for storing the address translation table, and a buffer area 36. In addition, the RAM 32 includes an area for storing the maximum sequence number (M), which is described later. The bus control element 33 has the well-known receiver/driver configuration for interconnecting the internal bus 31 and a memory bus connected to the flash memory 34.).
Claim 3 is rejected for the reasons set forth hereinabove for claim 1, Niijima teaches the operating method as claimed in claim 1, further comprising: not erasing the at least one flash sector upon the number of available cluster spaces being larger than or equal to the erase threshold(Niijima, column 6, line 37 to 56,The operation of the controller 30 in erasing a cluster (FIG. 4) will be explained by referring to FIG. 8. First, a cluster to be erased is determined. Although there are various methods, it is usual to determine a cluster as the one to be erased when the number of valid sectors for that cluster gets below a fixed value (step 80). If the cluster to be erased is X, the controller copies the valid data of X to a data sector in another cluster (step 81).).
Claim 4 is rejected for the reasons set forth hereinabove for claim 1, Niijima teaches the operating method as claimed in claim 1, wherein a cluster space is arranged to contain user configurations, which comprises at least one of count per inch setting, LED setting and key setting of a mouse device adopting the mouse chip(Niijima, column 3, line 56-58, The controller writes user data to sectors other than the cluster information sector for the cluster thus initialized according to their address sequence.).
Claim 5 is rejected for the reasons set forth hereinabove for claim 4, Niijima teaches the operating method as claimed in claim 4, wherein the at least one flash sector is previously selected exclusively for storing the user configurations( Niijima, column 5, line 56 to 60, FIG. 6 shows the configuration of sectors other than the cluster information sector of each cluster (hereinafter called "data sectors"). As shown, a data sector includes an area for storing an attribute and an error correction code (ECC) in addition to a data area for storing 512 byte user data.).
Claim 6 is rejected for the reasons set forth hereinabove for claim 1, Niijima teaches the operating method as claimed in claim 1, wherein in the calculating, the operating method comprises (Niijima, column 5, line 43 to 55 Niijima, column 6, line 37 to 56.):
checking a sector dirty bit and a cluster dirty bit in the at least one flash sector(Niijima, column 7, line 48 to 55, Until writing is complete for one cluster, that is, until all the sectors in the cluster are used, or it is decided that the rest of the cluster is to be left unused, data is not written into other clusters. If all sectors within a cluster are bad, writing of data is terminated therein. Such termination can be determined because bad sector information is previously written in a part of the flash memory 34 in the initialize process in SSF fabrication.); and
calculating a difference of a total cluster spaces of the at least one flash sector and a cluster index indicating the cluster dirty bit among the sector dirty bit to obtain the number of available cluster spaces(Niijima, column 7, line 48 to 55, Until writing is complete for one cluster, that is, until all the sectors in the cluster are used, or it is decided that the rest of the cluster is to be left unused, data is not written into other clusters. If all sectors within a cluster are bad, writing of data is terminated therein. Such termination can be determined because bad sector information is previously written in a part of the flash memory 34 in the initialize process in SSF fabrication.).
Claim 7 is rejected for the reasons set forth hereinabove for claim 6, Niijima teaches the operating method as claimed in claim 6, wherein in the erasing, the operating method further comprises: setting the cluster index to zero(Niijima, column 8, line 28 to 42, The process flow of the first method will be explained by referring to FIG. 10. First, the area of the address translation table is held in the RAM so as to initialize the value of each entry at a specific value (for example, 0) (step 100). Then, all cluster information sectors are read and sorted in the ascending order of sequence number (steps 101 and 102). Thereafter, clusters are selected from the lowest sequence number, and the sectors in the selected cluster are read in the order of address. In the embodiment, the sectors are sequentially read from the cluster information sector in ascending order of address. The physical address of that cluster is written in the entry of the address translation table pointed by the reverse pointer of the read sector. Even if an address of another sector has been written in the entry, the address of the sector just read is written (steps 103-108).).
Claim 8 is rejected for the reasons set forth hereinabove for claim 1, Niijima teaches the operating method as claimed in claim 1, wherein the flash chip does not enter an erase mode after the number of available cluster spaces is checked and before the mouse chip is powered off(Niijima, column 8, line 8 to 17, At the time when the system is powered-up, the address translation table is reconstructed while determining the validity or invalidity of sectors with the sequence number in the cluster and the location of sectors in the cluster. If there are a plurality of physical sectors for a specific logical sector, it is judged that the one in the cluster with the greatest sequence number is valid. If two or more physical sectors exist for one logical sector, a valid sector for the logical sector is settled by the time series information.).
Claim 10 is rejected for the reasons set forth hereinabove for claim 1, Niijima teaches the operating method as claimed in claim 1, wherein after the predetermined algorithm is expanded, the operating method further comprises: restoring user configurations from the firmware in the flash chip to the RAM(Niijima, column 5, line 25 to 35, FIG. 4 shows a schematic configuration of the SSF 20. The SSF 20 comprises a controller 30 connected to the family bus 18, and an internal bus 31 consisting of a random access memory (RAM) 32, a bus control element 33 and a flash memory 34. The RAM 32 includes an area 35 for storing the address translation table, and a buffer area 36. In addition, the RAM 32 includes an area for storing the maximum sequence number (M), which is described later. The bus control element 33 has the well-known receiver/driver configuration for interconnecting the internal bus 31 and a memory bus connected to the flash memory 34.).
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY KHUONG THANH NGUYEN whose telephone number is (571)270-7139. The examiner can normally be reached Monday - Friday 0800-1630.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lewis Bullock can be reached at 5712723759. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY KHUONG T NGUYEN/ Primary Examiner, Art Unit 2199
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