DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claim(s) 1, 2, 4, 5, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Rusconi Clerici Beltrami et al. (U.S. Pub. No. 2020/0021914 A1, hereinafter "Rusconi") in view of Sugawara (Japanese Pub. No. JP 2005142999 A).
Regarding Claim 1, Rusconi teaches a driver device (driver device 1, Figs. 1-3, Para. [0077]) for operating a modulated speaker (piezoelectric speaker 2, Figs. 1-3, Paras. [0077] and [0078]) wherein the speaker includes one or more membranes and or modulators (piezoelectric speaker 2 comprises a membrane, Para. [0060]), and the driver device comprising:
one or more voltage drivers each configured to provide a voltage signal to one or more membranes and or modulators (power stage 6 [voltage driver] provides piezoelectric speaker 2 membrane a voltage signal, Figs. 1-3, Para. [0066]); and
a controller (noise shaping unit 16 include a central processor or a controller/control unit of the driver device 1, Para. [0077]);
wherein the controller is configured to receive an audio signal (the noise shaping unit 6 which contains the controller receives input audio signal 3, Figs. 1-3, Para. [0062]), convert the digital signal to a N bit, noise shaped signal (using the circuit of Fig. 3, digital signal P is fed in the noise shaping unit 16 which outputs N bit noise shaped signal R, Fig. 3, Para. [0088]); modulate the N bit noise shaped signal by a carrier frequency (digital pulse width modulation (PWM) generator 5 converts the signal from the correction circuit 4 into a pulse-width modulated switch signal, Para. [0065]; i.e. the PWM generator 5 will modulated the N bit noise shaped signal by a carrier frequency) and drive a N bit PWM source to operate one or more voltage drivers (the voltage driver 8 is actuated by means of the switch signal converted by the PWM generator 5, Figs. 1-3, Para. [0066]).
Rusconi fails to explicitly teach driver device for operating a modulated ultrasound speaker;
generate a digital signal at a sample rate corresponding to twice the carrier frequency.
However, Sugawara teaches driver device for operating a modulated ultrasound speaker (a modulation system for ultrasonic speaker driving, Fig. 1, Abstract, Para. [0001]);
generate a digital signal at a sample rate corresponding to twice the carrier frequency (digitized AM modulation, Para. [0016]; the digital signal is sampled at twice the carrier frequency, Paras. [0022] and [0010]-[0012]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the driver device (as taught by Rusconi) to include the generation of a digital signal at a sample rate twice the carrier frequency (as taught by Sugawara). Doing so, stability of the digital circuit is realized (Sugawara Para. [0014]).
Regarding Claim 2, Rusconi in view of Sugawara teach wherein a voltage driver includes a low pass filter (Sugawara, low-pass filter 6, Fig. 1, Paras. [0017], [0019], and [0027]).
Regarding Claim 4, Rusconi in view of Sugawara teach wherein the controller is any of but not limited to; a microprocessor; a FPGA; a DSP; an ASIC digital block or any combination of these (Rusconi, noise shaping unit 16 include a central processor or a controller/control unit of the driver device 1. Noise shaping unit 16 can be an Application Specific Integrated Circuit (ASIC) or can be a part of the ASIC. Additionally, the correction unit 4, each summing register 10, 17 and/or the PWM-generator 5 also can be part of the processor or of the controller of the noise shaping unit 16, for example as software or hard-wired in the ASIC, Para. [0077]).
Regarding Claim 5, Rusconi in view of Sugawara teach wherein the audio signal is any of but not limited to; a digital signal; a PDM signal; a PWM signal; a I2S signal; an analog signal (Rusconi, digital input audio signal 3, Figs. 1-3, Para. [0062]).
Regarding Claim 7, Rusconi in view of Sugawara teach wherein the carrier frequency is any of but not limited to; between 200 KHz to 600 KHz; between 600 KHz to 1 MHz; above 1 MHz (Sugawara, carrier frequency is 40 KHz, Para. [0021]).
3. Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Rusconi Clerici Beltrami et al. (U.S. Pub. No. 2020/0021914 A1, hereinafter "Rusconi") in view of Sugawara (Japanese Pub. No. JP 2005142999 A), and further in view of Mayazaki (U.S. Pub. No. 2007/0121969 A1).
Regarding Claim 3, Rusconi in view of Sugawara fails to explicitly teach wherein a voltage driver includes at least a resistor which combined with the membrane capacitance provides a low pass filter.
However, Mayazaki teaches wherein a voltage driver includes at least a resistor which combined with the membrane capacitance provides a low pass filter (resistors R21 and RL1 connects inductance LL to capacitance CL1, Fig. 4, Para. [0146]; a serial resonance circuit (LPF) formed by CL1 and LL, Para. [0154]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the driver device (as taught by Rusconi in view of Sugawara) to include the driver resistor (as taught by Mayazaki). Doing so, it is possible to improve reproduction quality due to balance adjustment of the reproduction band (Mayazaki Para. [0033).
4. Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Rusconi Clerici Beltrami et al. (U.S. Pub. No. 2020/0021914 A1, hereinafter "Rusconi") in view of Sugawara (Japanese Pub. No. JP 2005142999 A) in view of Zaucha et al. (U.S. Pub. No. 2007/0005160 A1, hereinafter "Zaucha"), and further in view of Liang (U.S. Pub. No. 2022/0037997 A1).
Regarding Claim 6, Rusconi in view of Sugawara fails to explicitly teach wherein the audio signal is a digital single bit signal with data rates up to any of but not limited to; 1 MHz; 2 MHz; 3 MHz; 4 MHz; 5 MHz; 6 MHz; 13 MHz; 25 MHz.
However, Zaucha teaches wherein the audio signal is a digital single bit signal (input audio signal from sources 14a-14c are in the form of one-bit datastreams, Fig. 1, Para. (0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the driver device (as taught by Rusconi in view of Sugawara) to include the single bit digital audio signal (as taught by Zaucha). Doing so eliminates passive analog filtering which leads to more compact form factor of the ultrasound speaker.
However, Liang teaches wherein the audio signal with data rates up to any of but not limited to; 1 MHz; 2 MHz; 3 MHz; 4 MHz; 5 MHz; 6 MHz; 13 MHz; 25 MHz (audio signal IN has a data rate of 48 Ksps and R=1024, C=16 then CK0=49.152 MHz, CK1=3.072 MHz. In another example, the input signal IN has a data rate of 48 Ksps and R=336, C=16 then CK0=16.128 MHz, CK1=1.008 MHz, Fig. 1, Para. [0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the driver device (as taught by Rusconi in view of Sugawara, and further in view of Zaucha) to include the audio signal data rate (as taught by Liang). Doing so, the step size per DC-DC switching cycle can be reduced, which leads to better resolution and lower total harmonic distortion (Liang Para. [0041]).
5. Claim(s) 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Rusconi Clerici Beltrami et al. (U.S. Pub. No. 2020/0021914 A1, hereinafter "Rusconi") in view of Sugawara (Japanese Pub. No. JP 2005142999 A), and further in view of Liang (U.S. Pub. No. 2022/0037997 A1).
Regarding Claim 8, Rusconi in view of Sugawara fails to explicitly teach further including a clock circuit configured to generate a clock signal using an external reference clock signal.
However, Liang teaches further including a clock circuit (phase-locked loop 104, Fig. 1, Para. [0040]) configured to generate a clock signal using an external reference clock signal (phase-locked loop 104 uses external reference signal to generate a clock signal CK0, Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the driver device (as taught by Rusconi in view of Sugawara) to include the clock circuit (as taught by Liang). Doing so, the step size per DC-DC switching cycle can be reduced, which leads to better resolution and lower total harmonic distortion (Liang Para. [0041]).
Regarding Claim 9, Rusconi in view of Sugawara fails to explicitly teach further including a clock circuit configured to generate a clock signal using the digital data as a reference clock signal.
However, Liang teaches further including a clock circuit configured to generate a clock signal using the digital data as a reference clock signal (the digital input signal IN is used as the reference signal by the phase-locked loop 104 to generate clock signal CK0, Fig. 1, Para. [0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the driver device (as taught by Rusconi in view of Sugawara) to include the digital data as the reference signal for the clock circuit (as taught by Liang). Doing so, the step size per DC-DC switching cycle can be reduced, which leads to better resolution and lower total harmonic distortion (Liang Para. [0041]).
6. Claim(s) 10, 13, 14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Rusconi Clerici Beltrami et al. (U.S. Pub. No. 2020/0021914 A1, hereinafter "Rusconi") in view of Sugawara (Japanese Pub. No. JP 2005142999 A), and further in view of Kupershmidt et al. (U.S. Pub. No. 2016/0277832 A1, hereinafter "Kupershmidt").
Regarding Claim 10, Rusconi teaches a driver device (driver device 1, Figs. 1-3, Para. [0077]) for operating a modulated speaker (piezoelectric speaker 2, Figs. 1-3, Paras. [0077] and [0078]) wherein the speaker includes one or more membranes and or modulators (piezoelectric speaker 2 comprises a membrane, Para. [0060]), and the driver device comprising:
one or more voltage drivers each configured to provide a voltage signal to one or more membranes and or modulators (power stage 6 [voltage driver] provides piezoelectric speaker 2 membrane a voltage signal, Figs. 1-3, Para. [0066]); and
a controller (noise shaping unit 16 include a central processor or a controller/control unit of the driver device 1, Para. [0077]);
wherein the controller is configured to receive an audio signal (the noise shaping unit 6 which contains the controller receives input audio signal 3, Figs. 1-3, Para. [0062]), convert the digital signal to a N bit, noise shaped signal (using the circuit of Fig. 3, digital signal P is fed in the noise shaping unit 16 which outputs N bit noise shaped signal R, Fig. 3, Para. [0088]); modulate the N bit noise shaped signal by a carrier frequency (digital pulse width modulation (PWM) generator 5 converts the signal from the correction circuit 4 into a pulse-width modulated switch signal, Para. [0065]; i.e. the PWM generator 5 will modulated the N bit noise shaped signal by a carrier frequency) and drive a N bit PWM source to operate one or more voltage drivers (the voltage driver 8 is actuated by means of the switch signal converted by the PWM generator 5, Figs. 1-3, Para. [0066]).
Rusconi fails to explicitly teach driver device for operating a modulated ultrasound speaker;
a charge pump with one or more voltage levels;
generate a digital signal at a sample rate corresponding to twice the carrier frequency.
Rusconi fails to explicitly teach driver device for operating a modulated ultrasound speaker;
generate a digital signal at a sample rate corresponding to twice the carrier frequency.
However, Sugawara teaches driver device for operating a modulated ultrasound speaker (a modulation system for ultrasonic speaker driving, Fig. 1, Abstract, Para. [0001]);
generate a digital signal at a sample rate corresponding to twice the carrier frequency (digitized AM modulation, Para. [0016]; the digital signal is sampled at twice the carrier frequency, Paras. [0022] and [0010]-[0012]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the driver device (as taught by Rusconi) to include the generation of a digital signal at a sample rate twice the carrier frequency (as taught by Sugawara). Doing so, stability of the digital circuit is realized (Sugawara Para. [0014]).
However, Kupershmidt teaches a charge pump with one or more voltage levels (charge pump 30, Fig. 3, Para. [0065]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the driver device (as taught by Rusconi in view of Sugawara) to include the charge pump (as taught by Kupershmidt). Doing so, losses can be compensated for (Kupershmidt Para. [0061]).
Regarding Claim 13, Rusconi in view of Sugawara, and further in view of Kupershmidt teach wherein the controller is any of but not limited to; a microprocessor; a FPGA; a DSP; an ASIC digital block or any combination of these (Rusconi, noise shaping unit 16 include a central processor or a controller/control unit of the driver device 1. Noise shaping unit 16 can be an Application Specific Integrated Circuit (ASIC) or can be a part of the ASIC. Additionally, the correction unit 4, each summing register 10, 17 and/or the PWM-generator 5 also can be part of the processor or of the controller of the noise shaping unit 16, for example as software or hard-wired in the ASIC, Para. [0077]).
Regarding Claim 14, Rusconi in view of Sugawara, and further in view of Kupershmidt teach wherein the audio signal is any of but not limited to; a digital signal; a PDM signal; a PWM signal; a I2S signal; an analog signal (Rusconi, digital input audio signal 3, Figs. 1-3, Para. [0062]).
Regarding Claim 16, Rusconi in view of Sugawara, and further in view of Kupershmidt teach wherein the carrier frequency is any of but not limited to; between 200 KHz to 600 KHz; between 600 KHz to 1 MHz; above 1 MHz (Sugawara, carrier frequency is 40 KHz, Para. [0021]).
7. Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Rusconi Clerici Beltrami et al. (U.S. Pub. No. 2020/0021914 A1, hereinafter "Rusconi") in view of Sugawara (Japanese Pub. No. JP 2005142999 A) in view of Kupershmidt et al. (U.S. Pub. No. 2016/0277832 A1, hereinafter "Kupershmidt"), and further in view of Lee (U.S. Pub. No. 2010/0092010 A1).
Regarding Claim 11, Rusconi in view of Sugawara, and further in view of Kupershmidt fail to explicitly teach wherein the voltage drivers include a low pass filter.
However, Lee teaches wherein a voltage driver include a low pass filter (voltage driver 250 is a low-pass filter, Fig. 2, Paras. [0019] and [0020]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the driver device (as taught by Rusconi in view of Sugawara, and further in view of Kupershmidt) to include the voltage driver low-pass filter (as taught by Lee). Doing so, signal components higher than the designated frequency within the output audio signal can be filtered (Lee Claim 11).
8. Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Rusconi Clerici Beltrami et al. (U.S. Pub. No. 2020/0021914 A1, hereinafter "Rusconi") in view of Sugawara (Japanese Pub. No. JP 2005142999 A) in view of Kupershmidt et al. (U.S. Pub. No. 2016/0277832 A1, hereinafter "Kupershmidt"), and further in view of Mayazaki (U.S. Pub. No. 2007/0121969 A1).
Regarding Claim 12, Rusconi in view of Sugawara, and further in view of Kupershmidt fail to explicitly teach wherein a voltage driver includes at least a resistor which combined with the membrane capacitance provides a low pass filter.
However, Mayazaki teaches wherein a voltage driver includes at least a resistor which combined with the membrane capacitance provides a low pass filter (resistors R21 and RL1 connects inductance LL to capacitance CL1, Fig. 4, Para. [0146]; a serial resonance circuit (LPF) formed by CL1 and LL, Para. [0154]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the driver device (as taught by Rusconi in view of Sugawara, and further in view of Kupershmidt) to include the driver resistor (as taught by Mayazaki). Doing so, it is possible to improve reproduction quality due to balance adjustment of the reproduction band (Mayazaki Para. [0033).
9. Claim(s) 15 is rejected under 35 U.S.C. 103 as being unpatentable over Rusconi Clerici Beltrami et al. (U.S. Pub. No. 2020/0021914 A1, hereinafter "Rusconi") in view of Sugawara (Japanese Pub. No. JP 2005142999 A) in view of Kupershmidt et al. (U.S. Pub. No. 2016/0277832 A1, hereinafter "Kupershmidt") in view of Zaucha et al. (U.S. Pub. No. 2007/0005160 A1, hereinafter "Zaucha"), and further in view of Liang (U.S. Pub. No. 2022/0037997 A1).
Regarding Claim 15, Rusconi in view of Sugawara, and further in view of Kupershmidt fail to explicitly teach wherein the audio signal is a digital single bit signal with data rates up to any of but not limited to; 1 MHz; 2 MHz; 3 MHz; 4 MHz; 5 MHz; 6 MHz; 13 MHz; 25 MHz.
However, Zaucha teaches wherein the audio signal is a digital single bit signal (input audio signal from sources 14a-14c are in the form of one-bit datastreams, Fig. 1, Para. (0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the driver device (as taught by Rusconi in view of Sugawara, and further in view of Kupershmidt) to include the single bit digital audio signal (as taught by Zaucha). Doing so eliminates passive analog filtering which leads to more compact form factor of the ultrasound speaker.
However, Liang teaches wherein the audio signal with data rates up to any of but not limited to; 1 MHz; 2 MHz; 3 MHz; 4 MHz; 5 MHz; 6 MHz; 13 MHz; 25 MHz (audio signal IN has a data rate of 48 Ksps and R=1024, C=16 then CK0=49.152 MHz, CK1=3.072 MHz. In another example, the input signal IN has a data rate of 48 Ksps and R=336, C=16 then CK0=16.128 MHz, CK1=1.008 MHz, Fig. 1, Para. [0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the driver device (as taught by Rusconi in view of Sugawara in view of Kupershmidt, and further in view of Zaucha) to include the audio signal data rate (as taught by Liang). Doing so, the step size per DC-DC switching cycle can be reduced, which leads to better resolution and lower total harmonic distortion (Liang Para. [0041]).
10. Claim(s) 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Rusconi Clerici Beltrami et al. (U.S. Pub. No. 2020/0021914 A1, hereinafter "Rusconi") in view of Sugawara (Japanese Pub. No. JP 2005142999 A) in view of Kupershmidt et al. (U.S. Pub. No. 2016/0277832 A1, hereinafter "Kupershmidt"), and further in view of Liang (U.S. Pub. No. 2022/0037997 A1).
Regarding Claim 17, Rusconi in view of Sugawara, and further in view of Kupershmidt fails to explicitly teach further including a clock circuit configured to generate a clock signal using an external reference clock signal.
However, Liang teaches further including a clock circuit (phase-locked loop 104, Fig. 1, Para. [0040]) configured to generate a clock signal using an external reference clock signal (phase-locked loop 104 uses external reference signal to generate a clock signal CK0, Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the driver device (as taught by Rusconi in view of Sugawara, and further in view of Kupershmidt) to include the clock circuit (as taught by Liang). Doing so, the step size per DC-DC switching cycle can be reduced, which leads to better resolution and lower total harmonic distortion (Liang Para. [0041]).
Regarding Claim 18, Rusconi in view of Sugawara, and further in view of Kupershmidt fails to explicitly teach further including a clock circuit configured to generate a clock signal using the digital data as a reference clock signal.
However, Liang teaches further including a clock circuit configured to generate a clock signal using the digital data as a reference clock signal (the digital input signal IN is used as the reference signal by the phase-locked loop 104 to generate clock signal CK0, Fig. 1, Para. [0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the driver device (as taught by Rusconi in view of Sugawara, and further in view of Kupershmidt) to include the digital data as the reference signal for the clock circuit (as taught by Liang). Doing so, the step size per DC-DC switching cycle can be reduced, which leads to better resolution and lower total harmonic distortion (Liang Para. [0041]).
Conclusion
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHIMEZIE E BEKEE whose telephone number is (571)272-0202. The examiner can normally be reached M-F 7.30-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Duc Nguyen can be reached at 571-272-7503. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHIMEZIE EZERIWE BEKEE/ Examiner, Art Unit 2691
/DUC NGUYEN/Supervisory Patent Examiner, Art Unit 2691
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