DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Regarding Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the first amplifier" in the last line. There is insufficient antecedent basis for this limitation in the claim.
Apparently, it should be “the peak amplifier”. Examination is based on considering it as the peak amplifier.
Claim Rejections - 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 8-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mei (US 2014/0253246 A1).
Regarding Claim 1, Mei discloses in Fig. 6, A Doherty amplifier (Mei discloses a wideband Doherty amplifier network (§0001, §0012, FIG. 6), comprising:
a main amplifier (Mei discloses "a main amplifier" (2) (§0005, §0044, FIG. 1, FIG. 6);
a peak amplifier (Mei discloses "a peak amplifier" (3) (§0005, §0044, FIG. 1, FIG. 6);
a Doherty splitter configured for: splitting an input signal into a main signal part and a peak signal part; and providing the main signal part and the peak signal part to the main amplifier and the peak amplifier, respectively (Mei discloses that "The input signal to Doherty amplifier 1 is a differential signal that includes in-phase (I) and quadrature (Q) components" provided to the main amplifier and peak amplifier, respectively (§0005, FIG. 1);
a Doherty combiner having a first input port, a second input port, and an output port (Mei discloses a Doherty combiner device (100) including "a first input (102) and second input coupled to the main amplifier and the peak amplifier respectively" and an output port (106) (§0037, §0041, FIG. 4A, FIG. 6);
a non-impedance-inverting connection between an output of the main amplifier and the first input port (Mei discloses that "the main amplifier 2 is directly coupled to the differential port 102 without any intervening non-inverting impedance matching network" representing a transforming ratio of 1 (§0044, FIG. 7);
a first impedance inverting network arranged in between an output of the peak amplifier and the second input port (Mei discloses that "The peaking amplifier 3 is coupled to the other differential port via a simple quarter-wavelength transmission line 5" (§0044, FIG. 7);
wherein the Doherty splitter, the non-impedance-inverting connection, and the first impedance inverting network are configured such that a signal at the first input port of the Doherty combiner and a signal at the second input port of the Doherty combiner have opposite phases (Mei discloses that "the signals provided to the differential ports (102, 104) are 180 degrees out of phase" (§0044, FIG. 6, FIG. 7);
wherein the Doherty combiner comprises: a second impedance inverting network in between the first input port and the output port; and a third impedance inverting network in between the second input port and the output port (Mei discloses a Doherty combiner device (100) comprising couplers with transmission lines coupled between the respective differential input ports (102, 104) and the output port (106) (§0037, FIG. 4A, FIG. 6); and
wherein the Doherty combiner is configured to add the signal amplified by the main amplifier and the signal amplified by the first §peak amplifier in-phase at the output port (Mei discloses that the "Doherty combiner device 100 of the present invention combines the I, Q signals perfectly at the output port" (§0044, FIG. 6, FIG. 7).
Regarding Claim 2, The Doherty amplifier according to claim 1, wherein the second impedance inverting network comprises a transmission line or assembly of transmission lines having a first electrical length at the operational frequency (Fig. 4A; §0037 – disclosing that "Doherty combiner device 100 includes a first coupler 110 and a second coupler 120. Each coupler (110, 120) is implemented using a pair of tightly coupled transmission lines");
wherein the third impedance inverting network comprises a transmission line or assembly of transmission lines having a second electrical length at the operational frequency. (Fig. 4A; §0037 – describing that the couplers utilize transmission lines connected to the differential ports 102, 104);
wherein the first electrical length and the second electrical length differ by substantially 180 degrees at the operational frequency. (Fig. 7, Fig. 8A; §0044 – describing that signals provided to the differential ports are 180 degrees out of phase via the quarter-wavelength transmission line and splitter configuration).
Regarding Claim 8, the Doherty amplifier according to claim 1, wherein the first impedance inverting network comprises a first impedance matching network connected to the output of the peak amplifier, a first quarter-wavelength transmission line, and a second quarter-wavelength transmission line. (Fig. 2, Fig. 7; §0006, §0044 – disclosing quarter-wavelength transmission line 5 coupled to the peak amplifier);
wherein the first quarter-wavelength transmission line is arranged between the first impedance matching network and the second quarter-wavelength transmission line. (Fig. 2; §0006 – describing cascaded quarter-wavelength transmission lines TL4, TL12 in the matching network).
Regarding Claim 9, the Doherty amplifier according to claim 8, wherein the peak amplifier comprises a peak power transistor having an intrinsic drain. (Fig. 8A; §0006, §0045 – "Peaking_Amp_transistor" having intrinsic output impedance characteristics);
wherein the first impedance matching network is connected in between the intrinsic drain of the peak power transistor and the quarter-wavelength transmission line. (Fig. 8A; §0006, §0045 – showing matching networks connected directly to the transistor output/intrinsic drain terminals).
Regarding Claim 10, the Doherty amplifier according to claim 1, wherein the non-impedance-inverting connection comprises a second impedance matching network connected to the output of the main amplifier and a quarter-wavelength transmission line. (Fig. 7; §0044 – "the main amplifier 2 is directly coupled to the differential port 102... represents a special case of a non-inverting impedance matching network that has a transforming ratio of 1").
Regarding Claim 11, the Doherty amplifier according to claim 10, wherein the main amplifier comprises a main power transistor having an intrinsic drain. (Fig. 8A; §0006 – referencing "Main_Amp_transistor" and amplifier output terminals);
wherein the second impedance matching network is connected in between the intrinsic drain of the main power transistor and the quarter-wavelength transmission line. (Fig. 8A; §0006 – "output of the main amplifier 2 is directed to an inverting impedance matching network").
Regarding Claim 12, the Doherty amplifier according to claim 1, further comprising a printed circuit board. (Fig. 13, Figs. 14A–14J; §0050 – §0051 – disclosing integrated circuit and printed substrate/multilayer board implementations of the Doherty combiner);
wherein the Doherty combiner is realized on the printed circuit board. (Fig. 13; §0050 – "cross-section of an integrated circuit implementing the Doherty Combiner device").
Regarding Claim 13, the Doherty amplifier according to claim 12, wherein the first impedance inverting network comprises a first impedance matching network connected to the output of the peak amplifier, a first quarter-wavelength transmission line, and a second quarter-wavelength transmission line. (Fig. 2, Fig. 7; §0006, §0044);
wherein the first quarter-wavelength transmission line is arranged between the first impedance matching network and the second quarter-wavelength transmission line. (Fig. 2; §0006);
wherein the first quarter-wavelength transmission line and the second quarter-wavelength transmission line of the first impedance inverting network are realized on the printed circuit board. (Fig. 13, Figs. 14A–14J; §0050 – §0051 – transmission lines implemented across substrate layers M3–M6);
wherein the first impedance matching network is partially realized on the printed circuit board. (Fig. 13; §0006, §0050 – matching networks incorporating distributed elements on the PCB alongside device packaging).
Regarding Claim 14, the Doherty amplifier according to claim 13, wherein the non-impedance-inverting connection comprises a second impedance matching network connected to the output of the main amplifier and a quarter-wavelength transmission line. (Fig. 7; §0044);
wherein the quarter-wavelength transmission line of the non-impedance-inverting connection is realized on the printed circuit board. (Fig. 13; §0050 – §0051 – layout of transmission lines on board layers);
wherein the second impedance matching network is partially realized on the printed circuit board. (Fig. 13; §0006, §0050).
Regarding Claim 15, the Doherty amplifier according to claim 1, wherein the main amplifier and the peak amplifier are provided as packaged devices. (§0006 – noting that "power amplifiers (2, 3) are treated as pure power sources, whereas the matching networks (4, 5) are deemed to include packaging, parasitic capacitors").
Regarding Claim 17, Mei also teaches that the invention of the broadband Doherty Amplifier (as described above in response to claim 1) is intended for a base station for mobile telecommunications (§0004 – "market forces are requiring base stations to support a wider range of frequency bands... base station power amplifier has emerged as one of the key components").
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Root (US Pat. no. 8,593,219 B1) in view of the secondary considerations/common knowledge in the art.
Regarding Claim 1, Root discloses in Fig. 2,
A Doherty amplifier (Col. 2, lines 50–55; Col. 6, lines 52–65; FIG. 2), comprising:
A main amplifier; (Col. 6, lines 59–65; carrier amplifier stage 230 including carrier amplifier device 236 in FIG. 2);
a peak amplifier; (Col. 6, lines 59–65; peaking amplifier stage 210 including peaking amplifier device 216 in FIG. 2);
a Doherty splitter configured for: splitting an input signal into a main signal part and a peak signal part; and providing the main signal part and the peak signal part to the main amplifier and the peak amplifier, respectively; (Col. 6, lines 60–65; signal splitter 204 in FIG. 2);
a Doherty combiner having a first input port, a second input port, and an output port; (Col. 6, lines 63–65; power combiner 252 having inputs coupled to carrier amplifier stage 230 and frequency adjustable phase delay circuit 220 in FIG. 2);
a non-impedance-inverting connection between an output of the main amplifier and the first input port; (Col. 6, lines 63–65; Col. 7, lines 20–25; connection via impedance transform circuit 238 to power combiner 252 in FIG. 2);
a first impedance inverting network arranged in between an output of the peak amplifier and the second input port; (Col. 7, lines 1–5; Col. 9, lines 15–25; frequency adjustable phase delay circuit 220 and phase-matching transmission line 280 coupled to peaking amplifier stage 210 output in FIG. 2);
wherein the Doherty splitter, the non-impedance-inverting connection, and the first impedance inverting network are configured such that a signal at the first input port of the Doherty combiner and a signal at the second input port of the Doherty combiner have opposite phases; (Col. 6, lines 50–65; Col. 7, lines 1–10; FIG. 2);
wherein the Doherty combiner comprises: a second impedance inverting network in between the first input port and the output port; and a third impedance inverting network in between the second input port and the output port; §Note: Primary reference implements these via wideband matching networks and multiple section LC structures, but specific discrete dual-branch structural phrasing may be viewed under alternate interpretations (Col. 8, lines 1–25; Col. 9, lines 1–15; FIG. 2, FIG. 3);
wherein the Doherty combiner is configured to add the signal amplified by the main amplifier and the signal amplified by the first §peak amplifier in-phase at the output port. (Col. 6, lines 35–45; Col. 7, lines 35–45; power combiner 252 providing output signal at output 258 in FIG. 2);
While Root broadly discloses frequency-adjustable phase delay circuits and multi-section impedance transformations for inverted and non-inverting Doherty topologies, to the extent an examiner or strict reading finds that the exact structural integration of specific dual combiner-branch impedance networks in combination with the precise closed-loop phase-delay tracking parameters for the peak amplifier path is not identically spelled out in a single embodiment in the primary reference, a secondary reference or common general knowledge in RF amplifier design is looked to for complete harmonious alignment.
However, it is a standard textbook knowledge in radio frequency engineering and secondary wireless power amplifier disclosures (such as standard microwave engineering principles on broadband combining networks by Pozar or standard coupling structures) explicitly teach the integration of corresponding symmetric/asymmetric branch reactance and secondary phase-alignment networks to optimize combining efficiency across multi-standard bands.
A person of ordinary skill in the art (POSITA) at the time of the invention would have found it obvious to combine the wideband multi-section LC matching and adjustable phase delay teachings of US 8,593,219 B1 with standard secondary network configurations or common knowledge adjustments to precisely tune branch line lengths and phase responses for specific multi-band deployment requirements.
Modifying and fine-tuning the phase delay circuits and impedance networks provides enhanced bandwidth flexibility, minimizes power leakage back into the cutoff peaking amplifier, reduces insertion loss, and extends high operational efficiency across multiple commercial frequency bands (such as 700 MHz, 800 MHz, and 900 MHz bands) as described in the primary reference itself (Col. 16, lines 30–50).
Claims 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Mei (US Pat. no. 8,593,219 B1) in view of the secondary considerations/common knowledge in the art.
Regarding Claim 3, Mei teaches all limitations of claim 2. Mei further teaches that one of the second impedances in inverting network and the third impedance inverting network comprises a quarter-wavelength transmission line. (Fig. 7; §0044 – "The peaking amplifier 3 is coupled to the other differential port via a simple quarter-wavelength transmission line 5");
wherein the other of the second impedance inverting network and the third impedance inverting network comprises a quarter-wavelength transmission line in series with a half-wavelength transmission line (Fig. 2; §0006 – noting conventional configurations or expanded multi-section matching networks, combined with Fig. 7 direct connection where the main amplifier path acts as a direct/non-inverting connection).
Mei, however, doesn’t teach the precise selection of a half-wavelength transmission line in series with a quarter-wavelength transmission line in the specific branch arrangement.
Standard textbook knowledge in RF engineering (e.g., Pozar, Microwave Engineering) teaches cascading quarter-wave and half-wave transmission line sections for phase and impedance adjustment.
Therefore, a person of ordinary skill in the art would find it obvious to modifying Mei's transmission line lengths to incorporate standard half-wavelength delay sections where phase rotation matching is required to achieve desired phase relationships and impedance matching characteristics without altering the core wideband balun combining topology.
Regarding Claim 4, Mei teaches all limitations of the Doherty amplifier according to claim 3 as an obvious modification in view of common knowledge in the art, wherein Mei also teaches that the Doherty combiner further comprises a second half-wavelength transmission line in between the first input and the second input of the Doherty combiner. (Fig. 4A; §0037 – coupled transmission line structures between inputs 102 and 104)
wherein a center region of the second half-wavelength transmission line is RF grounded (Fig. 4A, Fig. 6; §0037 – "by simply grounding one of the differential ports it becomes an impedance transformer").
Regarding Claim 5, Mei also teaches that the half-wavelength transmission lines and the quarter-wavelength transmission lines of the second impedance inverting network and the third impedance inverting network jointly form a rat-race coupler. (Fig. 4A, Fig. 6; §0037 – §0038 – describing tightly coupled transmission line structures functioning as baluns and hybrid-ring/coupler equivalents).
Regarding Claim 6, Mei again teaches a biasing circuitry for providing a bias signal to the main amplifier and the peak amplifier. (§0006 – stating that "matching networks (4, 5) are deemed to include packaging, parasitic capacitors, and bias circuitry").
wherein the biasing circuitry is connected to the center region of the second half-wavelength transmission line arranged between the first input and the second input of the Doherty combiner. (Fig. 4A, Fig. 6; §0037 – §0044 – placement of ground/bias points at the symmetric center of the balancing structure).
Regarding Claim 7, Mei teaches all limitations of the Doherty amplifier according to claim 3 as an obvious modification in view of common knowledge in the art, wherein the characteristic impedances of all the transmission lines of the second impedance inverting network and the third impedance inverting network are all equal to a same characteristic impedance. (Fig. 4A, Fig. 8A; §0037, §0045 – disclosing uniform odd-mode impedances Zo = Zs/4 across the coupler transmission lines).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Mei in view of Canning et al. (US 20160308495 A1).
Regarding Claim 16, Mei teaches all limitations of claim 15. Mei further teaches that the main amplifier and the peak amplifier are provided in a single package. (§0005 – §0006 – describing the integration of main and peak amplifier architectures within amplifier module deployment structures);
Mei also teaches main and peak amplifiers combined using a wideband balun network (Figs. 6, 7).
Mei, however, is not explicit about housing both amplifier transistors in a single integrated package.
Canning in the same field of endeavor teaches a packaged Doherty amplifier including and electrically conductive RF input terminal, an electrically conductive RF output input terminal, a main amplifier including a first input terminal and a first output driving terminal, the first input terminal being connected to the RF input terminal, and the first output driving terminal opposite from the substrate, and a peaking amplifier including a second input terminal and a second output driving terminal, the second input terminal being connected to the RF input terminal, and the second output driving terminal opposite from the substrate. The packaged Doherty amplifier further includes an output combining network being configured to feed output current from the first and second output driving terminals into a summing node. The output combining network includes a transmission line transformer balun that is mounted on the substrate and includes first and second input ports and a first output port connected to the summing node, a first electrical connection between the first output driving terminal and the first input port, and a second electrical connection between the second output driving terminal and the second input port. The second electrical connection includes a quarter wave impedance inverter. The packaged Doherty amplifier further includes a first output impedance matching network connected between the summing node and the RF output terminal.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to placing the main and peak amplifier dies into a common multi-chip package substrate to reduce parasitic interconnect inductances, minimize board footprint, and improve high-frequency performance consistency following the teaching of Canning.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached on (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
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