Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the U.S. patent application 18946284 filed on November 13, 2024.
Of original claims 1-20: no claims have been added, amended or cancelled. Accordingly, claims 1-20 are pending, and have been examined in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 10, 2025, complies with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Objections
Claims 4-18 are objected to because of the following informalities:
Claim 4, recites the limitations “transmitting the access request to the second component in response to that the access isolation status is a second status,” and “stopping accessing the second component in response to that the access isolation status is a first status.” For better clarity, it’s suggested that the aforementioned limitations be further amended to “transmitting the access request to the second component in response to an indication that the access isolation status is a second status,” and “stopping accessing the second component in response to an indication that the access isolation status is a first status,” respectively; (emphasis added).
Claim 5, recites the limitations “recording a first total quantity of times in response to that the access isolation status is the second status,” and “obtaining the access result corresponding to the access request and recording a second total quantity of times in response to that the access is ended.” For better clarity, it’s suggested that the aforementioned limitations be further amended to “recording a first total quantity of times in response to an indication that the access isolation status is the second status,” and “obtaining the access result corresponding to the access request and recording a second total quantity of times in response to an indication that the access is ended,” respectively; (emphasis added).
Claim 6, recites the limitations “in response to that the second total quantity of times is same as the first total quantity of times,” and “in response to that the second total quantity of times is different from the first total quantity of times.” For better clarity, it’s suggested that the aforementioned limitations be further amended to “in response to an indication that the second total quantity of times is same as the first total quantity of times,” and “in response to an indication that the second total quantity of times is different from the first total quantity of times;” respectively; (emphasis added).
Claim 7, recites the limitations “in response to that the timeout status is timeout, determining that the bus transmission status of the second component is abnormal.” For better clarity, it’s suggested that the aforementioned limitations be further amended to “in response to an indication that the timeout status is timeout, determining that the bus transmission status of the second component is abnormal.” (emphasis added).
Claim 8 recites the limitations “in response to that the timeout status is timeout, determining that the bus transmission status of the second component is abnormal.” For better clarity, it’s suggested that the aforementioned limitations be further amended to “in response to an indication that the timeout status is timeout, determining that the bus transmission status of the second component is abnormal.” (emphasis added).
Claim 9 recites the limitations “in response to that the timeout status is timeout, determining that the bus transmission status of the second component is abnormal.” For better clarity, it’s suggested that the aforementioned limitations be further amended to “in response to an indication that the timeout status is timeout, determining that the bus transmission status of the second component is abnormal.” (emphasis added).
Claim 10 recites the limitations “in response to that the timeout status is timeout, determining that the bus transmission status of the second component is abnormal.” For better clarity, it’s suggested that the aforementioned limitations be further amended to “in response to an indication that the timeout status is timeout, determining that the bus transmission status of the second component is abnormal.” (emphasis added).
Claim 11 recites the limitations “in response to that the timeout status is timeout, determining that the bus transmission status of the second component is abnormal.” For better clarity, it’s suggested that the aforementioned limitations be further amended to “in response to an indication that the timeout status is timeout, determining that the bus transmission status of the second component is abnormal.” (emphasis added).
Claim 12 recites the limitations “in response to that the timeout status is timeout, determining that the bus transmission status of the second component is abnormal.” For better clarity, it’s suggested that the aforementioned limitations be further amended to “in response to an indication that the timeout status is timeout, determining that the bus transmission status of the second component is abnormal.” (emphasis added).
Claims 13-18 recite the limitations “in response to that the acknowledgment signal indicating completion of transmission.” For better clarity, it’s suggested that the aforementioned limitations be further amended to “in response to an indication that the acknowledgment signal indicating completion of transmission.” (emphasis added).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 7-10, 13-16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. (“Zhao’; US20230342503A1) in view of Hayden et al. (“Hayden”; US20150355989A1).
Per claim 1: Zhao discloses a method for cross-domain access (Zhao FIGS. 5-6 and 10), comprising: transmitting an access request of a first component at a first security level to a second component at a second security level (Zhao para. [0011], “the subsystem of the low security level needs to request a configuration from the subsystem of the high security level”).
Zhao does not disclose an arrangement for: detecting a bus transmission status of the second component; generating an interrupt signal based on the bus transmission status, and taking a preset result indicating that the bus transmission status is in a preset status as an access result corresponding to the access request transmitted by the second component; and performing exception handling corresponding to the interrupt signal, to restore access of the first component to the second component.
However, in an analogous art, Hayden discloses an arrangement for:
detecting a bus transmission status of the second component (Hayden para. [0027], “the safety node provides a (programmable) timeout monitor which detects if a transaction on the downstream section is taking an excessive time to respond.”);
generating an interrupt signal based on the bus transmission status, and taking a preset result indicating that the bus transmission status is in a preset status as an access result corresponding to the access request transmitted by the second component (Hayden para. [0027], “the safety node then detaches the connection to the forwarded transaction, and allows the master to complete its transaction by returning a prearranged dummy/error response (or broadly referred herein as “a prearranged response”). The safety node then assumes the role of master and maintains the transaction on the downstream section, until such time as the downstream slave device responds, or the bus segment is reset. While the downstream bus section remains busy, the safety node rejects any subsequent access requests by any of the masters on the upstream section, together with a prearranged response, in such a way as to enable those masters to avoid deadlock or stall and to proceed with other processing, such as an error handler. Phrased differently, the safety node rejects any subsequent requests by any of the masters on the upstream section by transmitting or triggering an immediate dummy/error response (e.g., prearranged error response) to those subsequent requests, thus enabling these masters to avoid deadlock or stall.”; Hayden para. 0033], “The prearranged response can include of either or both of (a) in-band response signaling within the bus protocol, and (b) side-band response outside the bus protocol, such as an interrupt. For instance, if a normal-completion in-band response is issued (with a dummy response or a normal response received after the transaction has timed out), the in-band response can be accompanied by a side-band response (e.g., error interrupt) so that the master is notified of the timeout.”; Hayden para [0042], “a timeout interrupt register for indicating whether a timeout interrupt signal is active or inactive;”); and
performing exception handling corresponding to the interrupt signal (Hayden para. [0075], “When the safety node is in the timeout state, the outstanding transaction will be terminated by a prearranged dummy response on the master side. After that, bus transactions on the bus segment upstream from the safety node will operate as normal. All other new master interface transactions being issued downstream from the safety node (i.e., going through the safety node) will receive an error response immediately”), to restore access of the first component to the second component (Hayden para. [0083], “When the timeout interrupt register is set as inactive or has been reset, the value “0” indicates a timeout violation is no longer present and the timeout interrupt signal is not active.”).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify Zhao to include, as taught by Hayden, an arrangement for: detecting a bus transmission status of the second component; generating an interrupt signal based on the bus transmission status, and taking a preset result indicating that the bus transmission status is in a preset status as an access result corresponding to the access request transmitted by the second component; and performing exception handling corresponding to the interrupt signal, to restore access of the first component to the second component. Motivation for modifying would have been to avoid deadlock or stall in cross-domain requests, in order to increase a user-friendliness, attractiveness and broadened adoption of the Zhao/Hayden arrangement within the cross-domain security field.
Per claim 2: The Zhao/Hayden combination made obvious the method according to claim 1. Hayden further discloses an arrangement wherein the performing exception handling corresponding to the interrupt signal comprises:
performing access isolation between the first component and the second component based on the interrupt signal (Hayden para. [0094], “Safety nodes can increase interoperability while reducing the CCF fraction of the system, because the isolation provided by safety nodes can prevent faults from affecting multiple masters at the same time (thereby reducing CCF contribution)”);
restarting the second component, and restoring the bus transmission status of the second component to a normal status (Hayden para. [0083], “When the timeout interrupt register is set as inactive or has been reset, the value “0” indicates a timeout violation is no longer present and the timeout interrupt signal is not active.”); and
releasing the access isolation between the first component and the second component, to restore access of the first component to the second component (Hayden para. [0093], “Systems utilizing the safety nodes can recover from hardware faults (i.e., having a great degree of survivability) while having the benefit of interconnecting the two systems.”; Hayden para. [0073], “by an interrupt and/or by a status bit in a register, indicating that the downstream bus segment has recovered”).
Per claim 3: The Zhao/Hayden combination made obvious the method according to claim 2. Hayden further discloses an arrangement wherein
the performing access isolation the first component and the second component based on the interrupt signal comprises:
setting, based on the interrupt signal, an access isolation status of the first component accessing the second component to a first status (Hayden para. [0033], “The prearranged response can include of either or both of (a) in-band response signaling within the bus protocol, and (b) side-band response outside the bus protocol, such as an interrupt. For instance, if a normal-completion in-band response is issued (with a dummy response or a normal response received after the transaction has timed out), the in-band response can be accompanied by a side-band response (e.g., error interrupt) so that the master is notified of the timeout.”; Hayden para [0042], “a timeout interrupt register for indicating whether a timeout interrupt signal is active or inactive;”; Hayden para. [0094], “Safety nodes can increase interoperability while reducing the CCF fraction of the system, because the isolation provided by safety nodes can prevent faults from affecting multiple masters at the same time (thereby reducing CCF contribution)”); and
the releasing the access isolation between the first component and the second component comprises: setting an isolation release status to the first status (Hayden para. [0042], “The timeout monitor 132 can be configured to set values for at least some of the one or more registers 130.”; Hayden para. [0073], “by an interrupt and/or by a status bit in a register, indicating that the downstream bus segment has recovered”), and/or setting the access isolation status to a second status (Hayden para. [0043], “safety node 124 can provide write protect registers assigned to each peripheral to disable write access from a given master, or access protect registers assigned to each peripheral to disable read access from a given master. Another feature of the safety node may include locks for locking the write protect registers and/or access protect registers.”).
Per claim 4: The Zhao/Hayden combination made obvious the method according to claim 1. Hayden further discloses an arrangement wherein the transmitting an access request of a first component at a first security level to a second component at a second security level comprises:
checking an access isolation status of the first component accessing the second component (Hayden para. [0043], “safety node 124 can provide write protect registers assigned to each peripheral to disable write access from a given master, or access protect registers assigned to each peripheral to disable read access from a given master. Another feature of the safety node may include locks for locking the write protect registers and/or access protect registers.”); and
transmitting the access request to the second component in response to that the access isolation status is a second status (Hayden para. [0073], “by an interrupt and/or by a status bit in a register, indicating that the downstream bus segment has recovered”); and
the method further comprises: stopping accessing the second component in response to that the access isolation status is a first status (Hayden para. [0083], “When the timeout interrupt register (e.g., a 1-bit register at position 13 dedicated for storing the status bit) is set as active, the value “1” indicates that a timeout violation has been detected and a timeout interrupt signal has been asserted (or is active)”; Hayden para. [0027], “While the downstream bus section remains busy, the safety node rejects any subsequent access requests by any of the masters on the upstream section”; Hayden para. [0043], “Another feature of the safety node may include locks for locking the write protect registers and/or access protect registers.”).
Per claim 7: The Zhao/Hayden combination made obvious the method according to claim 1. Hayden further discloses an arrangement wherein the detecting a bus transmission status of the second component comprises:
detecting a timeout status of an acknowledgment signal indicating completion of transmission that is returned by the second component; and in response to that the timeout status is timeout, determining that the bus transmission status of the second component is abnormal (Hayden para. [0033], “if a normal-completion in-band response is issued (with a dummy response or a normal response received after the transaction has timed out), the in-band response can be accompanied by a side-band response (e.g., error interrupt) so that the master is notified of the timeout”).
Per claim 8: The Zhao/Hayden combination made obvious the method according to claim 2. Hayden further discloses an arrangement wherein the detecting a bus transmission status of the second component comprises:
detecting a timeout status of an acknowledgment signal indicating completion of transmission that is returned by the second component; and in response to that the timeout status is timeout, determining that the bus transmission status of the second component is abnormal (Hayden para. [0033], “if a normal-completion in-band response is issued (with a dummy response or a normal response received after the transaction has timed out), the in-band response can be accompanied by a side-band response (e.g., error interrupt) so that the master is notified of the timeout”).
Per claim 9: The Zhao/Hayden combination made obvious the method according to claim 3. Hayden further discloses an arrangement wherein the detecting a bus transmission status of the second component comprises:
detecting a timeout status of an acknowledgment signal indicating completion of transmission that is returned by the second component; and in response to that the timeout status is timeout, determining that the bus transmission status of the second component is abnormal (Hayden para. [0033], “if a normal-completion in-band response is issued (with a dummy response or a normal response received after the transaction has timed out), the in-band response can be accompanied by a side-band response (e.g., error interrupt) so that the master is notified of the timeout”).
Per claim 10: The Zhao/Hayden combination made obvious the method according to claim 4. Hayden further discloses an arrangement wherein the detecting a bus transmission status of the second component comprises:
detecting a timeout status of an acknowledgment signal indicating completion of transmission that is returned by the second component; and in response to that the timeout status is timeout, determining that the bus transmission status of the second component is abnormal (Hayden para. [0033], “if a normal-completion in-band response is issued (with a dummy response or a normal response received after the transaction has timed out), the in-band response can be accompanied by a side-band response (e.g., error interrupt) so that the master is notified of the timeout”).
Per claim 13: The Zhao/Hayden combination made obvious the method according to claim 7. Hayden further discloses an arrangement further comprising: in response to that the acknowledgment signal indicating completion of transmission that is returned by the second component is received within preset time, taking data that has been transmitted by the second component as the access result corresponding to the access request (Hayden para. [0029], “This safety node solution has the advantage of being able to wait for a late or delayed response to a transaction, rather than simply aborting a transaction or resetting the system”; Hayden para. [0020], “These hazards would result in a timeout error, i.e., lack of expected response, or a delayed expected response”; Hayden para. [0076], “, if the write completes later after the timeout error, the safety node may use an interrupt or status indication (bit in a register) to notify the originating master. The handler for this indication may then take diagnostic or corrective action to determine the current state of the system and to take appropriate action to protect the system.”).
Per claim 14: The Zhao/Hayden combination made obvious the method according to claim 8. Hayden further discloses an arrangement further comprising: in response to that the acknowledgment signal indicating completion of transmission that is returned by the second component is received within preset time, taking data that has been transmitted by the second component as the access result corresponding to the access request (Hayden para. [0029], “This safety node solution has the advantage of being able to wait for a late or delayed response to a transaction, rather than simply aborting a transaction or resetting the system”; Hayden para. [0020], “These hazards would result in a timeout error, i.e., lack of expected response, or a delayed expected response”; Hayden para. [0076], “, if the write completes later after the timeout error, the safety node may use an interrupt or status indication (bit in a register) to notify the originating master. The handler for this indication may then take diagnostic or corrective action to determine the current state of the system and to take appropriate action to protect the system.”).
Per claim 15: The Zhao/Hayden combination made obvious the method according to claim 9. Hayden further discloses an arrangement further comprising: in response to that the acknowledgment signal indicating completion of transmission that is returned by the second component is received within preset time, taking data that has been transmitted by the second component as the access result corresponding to the access request (Hayden para. [0029], “This safety node solution has the advantage of being able to wait for a late or delayed response to a transaction, rather than simply aborting a transaction or resetting the system”; Hayden para. [0020], “These hazards would result in a timeout error, i.e., lack of expected response, or a delayed expected response”; Hayden para. [0076], “, if the write completes later after the timeout error, the safety node may use an interrupt or status indication (bit in a register) to notify the originating master. The handler for this indication may then take diagnostic or corrective action to determine the current state of the system and to take appropriate action to protect the system.”).
Per claim 16: The Zhao/Hayden combination made obvious the method according to claim 10. Hayden further discloses an arrangement further comprising: in response to that the acknowledgment signal indicating completion of transmission that is returned by the second component is received within preset time, taking data that has been transmitted by the second component as the access result corresponding to the access request (Hayden para. [0029], “This safety node solution has the advantage of being able to wait for a late or delayed response to a transaction, rather than simply aborting a transaction or resetting the system”; Hayden para. [0020], “These hazards would result in a timeout error, i.e., lack of expected response, or a delayed expected response”; Hayden para. [0076], “, if the write completes later after the timeout error, the safety node may use an interrupt or status indication (bit in a register) to notify the originating master. The handler for this indication may then take diagnostic or corrective action to determine the current state of the system and to take appropriate action to protect the system.”).
Per claim 19: Zhao discloses a non-transitory computer readable storage medium, wherein the storage medium stores a computer program, and the non-transitory computer program is used for implementing a method for cross-domain access (Zhao para. [0207], “computer program product, when run on a computer, enable an electronic device to perform the security isolation method”), wherein the method for cross-domain access comprises:
Zhao does not disclose an arrangement for: transmitting an access request of a first component at a first security level to a second component at a second security level; detecting a bus transmission status of the second component; detecting a bus transmission status of the second component; generating an interrupt signal based on the bus transmission status, and taking a preset result indicating that the bus transmission status is in a preset status as an access result corresponding to the access request transmitted by the second component; and performing exception handling corresponding to the interrupt signal to restore access of the first component to the second component.
However, in an analogous art, Zhao discloses an arrangement for: transmitting an access request of a first component at a first security level to a second component at a second security level (Zhao para. [0011], “the subsystem of the low security level needs to request a configuration from the subsystem of the high security level”);
detecting a bus transmission status of the second component (Hayden para. [0027], “the safety node provides a (programmable) timeout monitor which detects if a transaction on the downstream section is taking an excessive time to respond.”);
generating an interrupt signal based on the bus transmission status, and taking a preset result indicating that the bus transmission status is in a preset status as an access result corresponding to the access request transmitted by the second component (Hayden para. [0027], “the safety node then detaches the connection to the forwarded transaction, and allows the master to complete its transaction by returning a prearranged dummy/error response (or broadly referred herein as “a prearranged response”). The safety node then assumes the role of master and maintains the transaction on the downstream section, until such time as the downstream slave device responds, or the bus segment is reset. While the downstream bus section remains busy, the safety node rejects any subsequent access requests by any of the masters on the upstream section, together with a prearranged response, in such a way as to enable those masters to avoid deadlock or stall and to proceed with other processing, such as an error handler. Phrased differently, the safety node rejects any subsequent requests by any of the masters on the upstream section by transmitting or triggering an immediate dummy/error response (e.g., prearranged error response) to those subsequent requests, thus enabling these masters to avoid deadlock or stall.”; Hayden para. 0033], “The prearranged response can include of either or both of (a) in-band response signaling within the bus protocol, and (b) side-band response outside the bus protocol, such as an interrupt. For instance, if a normal-completion in-band response is issued (with a dummy response or a normal response received after the transaction has timed out), the in-band response can be accompanied by a side-band response (e.g., error interrupt) so that the master is notified of the timeout.”; Hayden para [0042], “a timeout interrupt register for indicating whether a timeout interrupt signal is active or inactive;”); and
performing exception handling corresponding to the interrupt signal (Hayden para. [0075], “When the safety node is in the timeout state, the outstanding transaction will be terminated by a prearranged dummy response on the master side. After that, bus transactions on the bus segment upstream from the safety node will operate as normal. All other new master interface transactions being issued downstream from the safety node (i.e., going through the safety node) will receive an error response immediately”), to restore access of the first component to the second component (Hayden para. [0083], “When the timeout interrupt register is set as inactive or has been reset, the value “0” indicates a timeout violation is no longer present and the timeout interrupt signal is not active.”).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify Zhao to include, as taught by Hayden, an arrangement for: transmitting an access request of a first component at a first security level to a second component at a second security level; detecting a bus transmission status of the second component; detecting a bus transmission status of the second component; generating an interrupt signal based on the bus transmission status, and taking a preset result indicating that the bus transmission status is in a preset status as an access result corresponding to the access request transmitted by the second component; and performing exception handling corresponding to the interrupt signal to restore access of the first component to the second component. Motivation for modifying would have been to avoid deadlock or stall in cross-domain requests, in order to increase a user-friendliness, attractiveness and broadened adoption of the Zhao/Hayden arrangement within the cross-domain security field.
Per claim 20: Zhao discloses an electronic device (Zhao para. [0206], “”electronic device”), wherein the electronic device comprises:
a processor (Zhao para. [0213], “a single-chip microcomputer, a chip or the like”); and
a memory, configured to store processor-executable instructions (Zhao para. [0213], “storage medium includes any medium that can store program code, for example, a Universal Serial Bus (USB) flash drive, a removable hard disk, a read-only memory (ROM), a random-access memory (RAM), a magnetic disk, or an optical disc.”), and
transmitting an access request of a first component at a first security level to a second component at a second security level (Zhao para. [0011], “the subsystem of the low security level needs to request a configuration from the subsystem of the high security level”).
Zhao does not disclose an arrangement wherein the processor is configured to read the executable instructions from the memory, and execute the instructions to implement a method for cross-domain access, wherein the method for cross-domain access comprises: detecting a bus transmission status of the second component; generating an interrupt signal based on the bus transmission status, and taking a preset result indicating that the bus transmission status is in a preset status as an access result corresponding to the access request transmitted by the second component; ); and performing exception handling corresponding to the interrupt signal, to restore access of the first component to the second component.
However, in an analogous art, Hayden discloses an arrangement for:
detecting a bus transmission status of the second component (Hayden para. [0027], “the safety node provides a (programmable) timeout monitor which detects if a transaction on the downstream section is taking an excessive time to respond.”);
generating an interrupt signal based on the bus transmission status, and taking a preset result indicating that the bus transmission status is in a preset status as an access result corresponding to the access request transmitted by the second component (Hayden para. [0027], “the safety node then detaches the connection to the forwarded transaction, and allows the master to complete its transaction by returning a prearranged dummy/error response (or broadly referred herein as “a prearranged response”). The safety node then assumes the role of master and maintains the transaction on the downstream section, until such time as the downstream slave device responds, or the bus segment is reset. While the downstream bus section remains busy, the safety node rejects any subsequent access requests by any of the masters on the upstream section, together with a prearranged response, in such a way as to enable those masters to avoid deadlock or stall and to proceed with other processing, such as an error handler. Phrased differently, the safety node rejects any subsequent requests by any of the masters on the upstream section by transmitting or triggering an immediate dummy/error response (e.g., prearranged error response) to those subsequent requests, thus enabling these masters to avoid deadlock or stall.”; Hayden para. 0033], “The prearranged response can include of either or both of (a) in-band response signaling within the bus protocol, and (b) side-band response outside the bus protocol, such as an interrupt. For instance, if a normal-completion in-band response is issued (with a dummy response or a normal response received after the transaction has timed out), the in-band response can be accompanied by a side-band response (e.g., error interrupt) so that the master is notified of the timeout.”; Hayden para [0042], “a timeout interrupt register for indicating whether a timeout interrupt signal is active or inactive;”); and
performing exception handling corresponding to the interrupt signal (Hayden para. [0075], “When the safety node is in the timeout state, the outstanding transaction will be terminated by a prearranged dummy response on the master side. After that, bus transactions on the bus segment upstream from the safety node will operate as normal. All other new master interface transactions being issued downstream from the safety node (i.e., going through the safety node) will receive an error response immediately”), to restore access of the first component to the second component (Hayden para. [0083], “When the timeout interrupt register is set as inactive or has been reset, the value “0” indicates a timeout violation is no longer present and the timeout interrupt signal is not active.”).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify Zhao to include, as taught by Hayden, an arrangement wherein the processor is configured to read the executable instructions from the memory, and execute the instructions to implement a method for cross-domain access, wherein the method for cross-domain access comprises: detecting a bus transmission status of the second component; generating an interrupt signal based on the bus transmission status, and taking a preset result indicating that the bus transmission status is in a preset status as an access result corresponding to the access request transmitted by the second component; ); and performing exception handling corresponding to the interrupt signal, to restore access of the first component to the second component. Motivation for modifying would have been to avoid deadlock or stall in cross-domain requests, in order to increase a user-friendliness, attractiveness and broadened adoption of the Zhao/Hayden arrangement within the cross-domain security field.
Allowable Subject Matter
Claims 5-6, 11-12 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the objection addressed in section “Claim Objections” above, and rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/Paul Skwierawski/
Patent Examiner, Art Unit 2439
/LUU T PHAM/Supervisory Patent Examiner, Art Unit 2439
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