CTNF 18/946,405 CTNF 84227 DETAILED ACTION 12-151 AIA 26-51 12-51 Status of Claims Claims 1 has been cancelled. Claims 2 – 21 are pending. This office action is Non-Final. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections 07-29-01 AIA Claim s 2 – 21 are objected to because of the following informalities: Regarding claims 2 and 12, the term “at” in the limitation “…buffer of at the second…” is unnecessary and appears to be in error . Appropriate correction is required. Regarding claims 10 and 20, the term “from” appears to be in error. The Examiner believes the term should be “form”. Appropriate correction is required. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 2, 3,6 – 8, 10, 12, 13, 16 – 18, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s of U.S. Patent No. 12,032,511 . Although the claims at issue are not identical, they are not patentably distinct from each other because they are directed to the same invention; a system and method to establish a high-precision common time base across separate chips and synchronization via a determined maximum latency . Similarities in the claims are provided in the table below (emphasis added by the Examiner): Instance Application No. ‘405 Patent No. ‘511 2. A method for transmitting data between integrated-circuit chips, comprising : receiving, at a second integrated-circuit chip, data from a first integrated-circuit chip that is destined for a third integrated- circuit chip, wherein the first integrated-circuit chip, the second integrated-circuit chip, and the third integrated-circuit chip are part of a topology of integrated-circuit chips; storing the data in a buffer at the second integrated-circuit chip; and transmitting, from the second integrated-circuit chip, the data stored in the buffer of at the second integrated-circuit chip to a third integrated-circuit chip after a maximum inter-chip latency has elapsed since time of transmission of the data from the first integrated-circuit chip to the second integrated-circuit chip . 10. A method for transmitting data among integrated circuit chips, the method comprising : at a first time, transmitting data from a first integrated circuit chip to a second, adjacent integrated circuit chip in a series-ring arrangement of integrated circuit chips of a semiconductor device ; storing the data in a buffer at the second integrated circuit chip ; determining a characteristic inter-chip latency of the series-ring arrangement of integrated circuit chips; releasing the data from the buffer at a second time, wherein an interval between the first time and the second time is based on the characteristic inter-chip latency of the series-ring arrangement of integrated circuit chips ; and transmitting the data from the second integrated circuit chip to a third integrated circuit chip, the third integrated circuit chip being adjacent to the second integrated circuit chip in the series-ring arrangement of integrated circuit chips . 3. The method of claim 2, wherein the maximum inter-chip latency is a function of a maximum inter-chip loop latency from among inter-chip loop latencies determined for each pair of integrated-circuit chips in the topology. 11. The method of claim 10, wherein the characteristic inter-chip latency represents the maximum expected one-way data transmission latency between two integrated circuit chips in the series-ring arrangement of integrated circuit chips. 6. The method of claim 2, wherein two or more chips of the topology of integrated- circuit chips are application specific integrated circuit (ASIC) chips configured to execute neural network operations. 14. The method of claim 10, wherein one or more of the first, second, and third integrated circuit chips are application specific integrated circuit (ASIC) chips configured to execute neural network operations. 7. The method of claim 6, wherein each ASIC chip is configured to implement a corresponding layer of a neural network. 14. The method of claim 10, wherein one or more of the first, second, and third integrated circuit chips are application specific integrated circuit (ASIC) chips configured to execute neural network operations. 8. The method of claim 7, wherein a first ASIC chip is configured to implement a first layer of the neural network and a second ASIC chip is configured to implement a second layer of the neural network based on an output from the first ASIC chip. 14. The method of claim 10, wherein one or more of the first, second, and third integrated circuit chips are application specific integrated circuit (ASIC) chips configured to execute neural network operations. 10. The method of claim 2, wherein the integrated-circuit chips of the topology from [[form]] a closed loop 1 . 11. The method of claim 10, wherein the characteristic inter-chip latency represents the maximum expected one-way data transmission latency between two integrated circuit chips in the series-ring arrangement of integrated circuit chips. 12. A system, comprising: one or more processors; and one or more storage devices coupled with the one or more processors, the one or more storage devices storing instructions that when executed by the one or more processors to perform operations, comprising: receiving, at a second integrated-circuit chip, data from a first integrated- circuit chip that is destined for a third integrated-circuit chip, wherein the first integrated-circuit chip, the second integrated-circuit chip, and the third integrated-circuit chip are part of a topology of integrated-circuit chips; storing the data in a buffer at the second integrated-circuit chip; and transmitting, from the second integrated-circuit chip, the data stored in the buffer of at the second integrated-circuit chip to a third integrated-circuit chip after a maximum inter-chip latency has elapsed since time of transmission of the data from the first integrated-circuit chip to the second integrated-circuit chip. 10. A method for transmitting data among integrated circuit chips, the method comprising: at a first time, transmitting data from a first integrated circuit chip to a second, adjacent integrated circuit chip in a series-ring arrangement of integrated circuit chips of a semiconductor device; storing the data in a buffer at the second integrated circuit chip; determining a characteristic inter-chip latency of the series-ring arrangement of integrated circuit chips; releasing the data from the buffer at a second time, wherein an interval between the first time and the second time is based on the characteristic inter-chip latency of the series-ring arrangement of integrated circuit chips; and transmitting the data from the second integrated circuit chip to a third integrated circuit chip, the third integrated circuit chip being adjacent to the second integrated circuit chip in the series-ring arrangement of integrated circuit chips. 13. The system of claim 12, wherein the maximum inter-chip latency is a function of a maximum inter-chip loop latency from among inter-chip loop latencies determined for each pair of integrated-circuit chips in the topology. 11. The method of claim 10, wherein the characteristic inter-chip latency represents the maximum expected one-way data transmission latency between two integrated circuit chips in the series-ring arrangement of integrated circuit chips. 16. The system of claim 12, wherein two or more chips of the topology of integrated- circuit chips are application specific integrated circuit (ASIC) chips configured to execute neural network operations. 14. The method of claim 10, wherein one or more of the first, second, and third integrated circuit chips are application specific integrated circuit (ASIC) chips configured to execute neural network operations. 17. The system of claim 16, wherein each ASIC chip is configured to implement a corresponding layer of a neural network. 14. The method of claim 10, wherein one or more of the first, second, and third integrated circuit chips are application specific integrated circuit (ASIC) chips configured to execute neural network operations. 18. The system of claim 17, wherein a first ASIC chip is configured to implement a first layer of the neural network and a second ASIC chip is configured to implement a second layer of the neural network based on an output from the first ASIC chip. 14. The method of claim 10, wherein one or more of the first, second, and third integrated circuit chips are application specific integrated circuit (ASIC) chips configured to execute neural network operations. 20. The system of claim 12, wherein the integrated-circuit chips of the topology from [[form]] a closed loop. 11. The method of claim 10, wherein the characteristic inter-chip latency represents the maximum expected one-way data transmission latency between two integrated circuit chips in the series-ring arrangement of integrated circuit chips . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 4, 5, 9, 11,14, 15, 19, and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Buonpane; Michael S. et al. (US Patent Application Publication No. 2010/0017569 A1) “PCB Including Multiple Chips Sharing an Off-Chip Memory, a Method of Accessing Off-Chip Memory and a MCM Utilizing Fewer Off-Chip Memories Than Chips” is cited to teach a PCB having fewer off-chip memories than chips, a MCM, and a method of accessing an off-chip shared memory space. The method includes: (1) generating a memory request at a first chip of the printed circuit board, (2) transforming the memory request to a shared memory request and (3) directing the shared memory request to an off-chip shared memory space indirectly coupled to the first chip via a second chip of the printed circuit board. Beukema; Troy James et al. (US Patent No. 10,826,536 B1) “Inter-chip Data Transmission System Using Single-ended Transceivers” is cited to teach a single-ended inter-chip data transmission system and a single-ended inter-chip data reception system for processing data. A controlled Hamming weight parallel data encoder at a transmitter device accepts N data bits with an arbitrary Hamming weight as input and generates M data bits with a controlled Hamming weight as output, wherein M is greater than N. A transmission circuit provides a time-aligned transmission of the controlled Hamming weight encoded data across a single-ended data bus. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERRELL S JOHNSON whose telephone number is (571)270-3485. The examiner can normally be reached 10AM-7PM EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TERRELL S JOHNSON/Primary Examiner, Art Unit 2176 Application/Control Number: 18/946,405 Page 2 Art Unit: 2176 Application/Control Number: 18/946,405 Page 3 Art Unit: 2176 Application/Control Number: 18/946,405 Page 4 Art Unit: 2176 Application/Control Number: 18/946,405 Page 5 Art Unit: 2176 Application/Control Number: 18/946,405 Page 6 Art Unit: 2176 Application/Control Number: 18/946,405 Page 7 Art Unit: 2176 Application/Control Number: 18/946,405 Page 8 Art Unit: 2176 Application/Control Number: 18/946,405 Page 9 Art Unit: 2176 Application/Control Number: 18/946,405 Page 10 Art Unit: 2176 Application/Control Number: 18/946,405 Page 11 Art Unit: 2176 Application/Control Number: 18/946,405 Page 12 Art Unit: 2176 Application/Control Number: 18/946,405 Page 13 Art Unit: 2176 Application/Control Number: 18/946,405 Page 14 Art Unit: 2176 Application/Control Number: 18/946,405 Page 15 Art Unit: 2176 Application/Control Number: 18/946,405 Page 16 Art Unit: 2176 Application/Control Number: 18/946,405 Page 17 Art Unit: 2176 Application/Control Number: 18/946,405 Page 18 Art Unit: 2176 Application/Control Number: 18/946,405 Page 19 Art Unit: 2176 Application/Control Number: 18/946,405 Page 20 Art Unit: 2176 1 Series -ring is a type of closed loop topology.
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