DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is in response to communications filed 2/12/2026 Claims 1 and 11 are amended. Claims 2-10, 12-15 are original.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/12/2026 was filed after the mailing date of the claims on 11/13/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant's arguments filed 2/12/2026 have been fully considered but they are not persuasive.
Applicant argues on page 13 of the remarks that “Wang merely disclose that the algorithm of
the decode program 103 includes a feature of "calculating a time delay for displaying a first
group of one or more frames of a video picture stream located in an output frame buffer. Here,
the output frame buffer is a mere storage containing the video picture stream. However, this is
entirely different from the above elements of claim 1, which requires an operation of setting "the
output buffer based on time required for a post-processing".
Thus, Applicant respectfully submits that Wang fails to disclose or suggest "set a size of
the output buffer based on time required for a post-processing," as claimed.”
Examiner respectfully disagrees. Wang Col. 6 lines 51-58, “It is important to note that the DecodeDelay may be determined using standard decoding mode performance characteristics regardless of whether the decoder 305 is currently operating in a fast decoding mode or a standard decoding mode. In order to effectively use this method of display buffer underflow and recovery, the DecodeDelay may be determined for at least two future video frames.”
The DecodeDelay in Wang encompasses the entire pipeline delay including post-processing because the output frame buffer 309 in Wang sits between the decoder and display, exactly where post-processed frames are stored before rendering. The “time delay for displaying” necessarily includes the time required for post-processing before frames can be placed in the output buffer. A POSTIA would understand that sizing the output buffer to accommodate the time delay inherently means sizing it based on the post-processing time, since post-processing is the primary time-consuming step between decoding and display in both Wang and applicant’s own specification.
Applicant argues on page 13-14 of the remarks that “Kumar merely teaches adjusting the size of the playback buffer based on the data rate ("at an increased or decreased rate") at which the application provides streaming content. However, Applicant respectfully submits that this portion of Kumar fails to disclose or suggest "adjust a speed of inputting the plurality of frames into the input buffer based on a speed at which the rendered frame is played via the display," as claimed.”
Examiner respectfully disagrees. Kumar’s teaching of adjusting the clock signal speed to the application to change the content provision rate is directly equivalent to adjusting the input speed to the buffer based on display playback speed. The claim language does not require any specific mechanism for adjustment, merely that the speed of inputting frames is adjusted based on rendered frame playback speed, which Kumar clearly teaches.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claim(s) 1 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application 2014/0146896, Nanda et al. (hereinafter Nanda) in view of U.S. Patent 8660191, Wang et al. (hereinafter Wang) further in view of U.S. Patent 11595316 Kumar et al. (hereinafter Kumar).
2. Regarding Claim 1, Nanda discloses An electronic device (Fig. 1) comprising:
a display (Fig. 1; [0012], “a display device”), at least one processor comprising processing circuitry; and
memory (Fig. 1; [0014], “memory 120”), comprising one or more storage mediums ([0024] “device readable storage”), a decoder (Fig. 1; [0012] “a decode engine 110”), a post-processing module (Fig. 1; [0012], “a post processing engine 130”), a renderer (Fig. 1; [0013], “post processing engine 130 and rendered for display by the display engine 140”), the memory being configured to store instructions,
wherein the decoder is configured to decode a frame among a plurality of frames of a video stored in an input buffer ([0013], “The decode engine 110 decodes frames in a decode order defined by a group of picture (GOP) frame structure for the video.” Fig. 4; [0019], “The decode engine 400 may include a receiver 410, a decoder 420, a controller 430, a transmitter 440, and a buffer 450…The decoder 420 may decode the frames and store the I and P frames in the buffer 450”), and
to generate a decoded frame, wherein the post-processing module (Fig. 2: 130 post processing engine) is configured to post-processes the decoded frame ([0012], “the post processing engine 130 may modify the video (e.g., brightness, quality) based on various parameters” [0013], “After the frames are decoded they are to be post processed by the post processing engine 130 “), and
to generate a post-processed frame, wherein the renderer is configured to render the decoded frame or the post-processed frame stored in an output buffer ([0013], “rendered for display by the display engine 140.” [0014] “The decode engine 110 may write the decoded frames to memory 120, a host processor (not illustrated) may reorder the frames stored in the memory 120, and the frames may be read from the memory 120 by the post processing engine 130 in the correct order.”), wherein the instructions ([0019] “The controller 430 may instruct the decoder 420 what type of frames it is decoding and what frames it needs for decoding (e.g., I frames for decoding of P frames, I and P frames for decoding of B frames)”), when executed by the at least one processor individually or collectively, cause the electronic device to:
However, Nanda does not explicitly disclose set a size of the output buffer based on time required for a post-processing, and adjust a speed of inputting the plurality of frames into the input buffer based on a speed at which the rendered frame is played via the display.
Wang teaches set a size of the output buffer based on time required (Fig. 3: 309 output frame buffer; Col. 2 lines 60-63, “a calculating a time delay for displaying a first group of one or more frames of a video picture stream located in an output frame buffer.” the output buffer is set/controlled based on time calculations for post-processing. Col. 6 lines 51-58, (DecodeDelay determination) with Fig. 3 (output frame buffer 309 sitting between decoder and display), time delay calculation for the output frame buffer inherently encompasses and is driven by post-processing time. The output buffer size is set to accommodate total pipeline delay, of which post-processing time is the dominant component)
A POSITA would have been motivated to incorporate Wang’s time-based output buffer sizing into Nanda’s decode/post-process/render pipeline to prevent buffer underflow/overflow and ensure smooth playback.
Wang does not explicitly disclose adjust a speed of inputting the plurality of frames into the input buffer based on a speed at which the rendered frame is played via the display.
Further, Kumar teaches adjust a speed of inputting the plurality of frames into the input buffer based on a speed at which the rendered frame is played via the display (Abstract, “The size of the buffer can be changed during the playback of streaming content. To perform the change seamlessly, embodiments can cause the application to provide the streaming content at an increased or decreased rate, depending on how the size of the playback buffer is to be changed. The changed rate for providing the streaming content can be achieved by slowing down or speeding up a clock signal that is provided to the application”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have combined Nanda’s decode, post-process, display pipeline with Wang’s display-time/output-buffer delay calculations to know the effective display drain rate, and then applied Kumar’s teaching to increase/decrease the source/input rate during playback to maintain the desired buffer level. Using Wang’s invention to measure how fast the display plays frames and Kumar’s invention to tune how fast frames are fed into Nanda’s input buffer is a routine pairing of known techniques to solve the well-known problem underrun/overrun, yielding predictable result of smooth, synchronized playback.
3. Claim 11 is a method claim, rejected with respect to the same limitations rejected in device claim 1.
Allowable Subject Matter
Claims 2-10, 12-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 2, Nanda discloses The electronic device of claim 1, wherein the instructions ([0019] “The controller 430 may instruct the decoder 420 what type of frames it is decoding and what frames it needs for decoding (e.g., I frames for decoding of P frames, I and P frames for decoding of B frames)”), when executed by the at least one processor individually or collectively, cause the electronic device to:
Nanda in view of Wang further in view of Kumar does not explicitly disclose obtain an input requesting for the post-processing, based on the input, identify generation time for generating the post-processed frame, based on the generation time, determine whether to cease playing the rendered frame via the display, based on a determination to cease the playing, set the post-processing when playing the video is ceased, and based on a determination not to cease the playing, set the post-processing when the video is played.
Claim 12 is objected to the same limitation objected to in device claim 2.
Regarding Claim 7, Nanda discloses The electronic device of claim 1, wherein the instructions ([0019] “The controller 430 may instruct the decoder 420 what type of frames it is decoding and what frames it needs for decoding (e.g., I frames for decoding of P frames, I and P frames for decoding of B frames)”), when executed by the at least one processor individually or collectively, further cause the electronic device to:
Nanda in view of Wang further in view of Kumar does not explicitly disclose set a backup buffer where the frame decoded by the decoder are stored and that is accessed by the post-processing module, and generate, by the post-processing module, the post-processed frame based on one or more decoded frames stored in the backup buffer.
Claim 17 is objected to the same limitation objected to in device claim 7.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to OMER KHALID whose telephone number is (571)270-5997. The examiner can normally be reached Monday- Friday 9am-7pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Miller can be reached at (571) 272-7353. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OMER KHALID/Examiner, Art Unit 2422
/JOHN W MILLER/Supervisory Patent Examiner, Art Unit 2422
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