Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Foreign Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/19/26, 06/03/25, 02/12/25 and 12/05/24 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 and 19 recites the limitation "the isolation region" in line 1 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4.) Claim(s) 1-20 is/are rejected under 35 U.S.C. 102 (a1) (a2) as being anticipated by Yanagita et al. (US Pub No.: 2015/0179691A1).
With regard to Claim 1, Yanagita et al. disclose a light detecting device (Light detecting solid-state imaging device, Abstract; Paragraphs 0045, 0137; Figure 16), comprising:
a first semiconductor layer including a photoelectric conversion region and a floating diffusion region (First semiconductor substrate/sensor substrate 3 includes the photodiodes and floating diffusion FD, Paragraphs 0040-0044; Figure 3);
a second semiconductor layer including an amplification transistor (Circuit substrate 9 contains the amplification transistor Tr5, Paragraph 0049; Figure 3);
a first wiring layer (31) including a first electrode (35) and a second electrode (39) (First wiring layer 31 of the substrate 3 includes a first electrode 35. Third electrode 39 is also formed on a first wiring layer 31 of the sensor substrate 3, Paragraphs 0044, 0083; Figure 6C); and
a second wiring layer including a third electrode (45) and a fourth electrode (49) (Second wiring layer 41 includes a second electrode 45 and a fourth electrode 49, Paragraphs 0044; 0083; Figure 6C),
wherein the first electrode contacts to the third electrode (Electrode 35 and electrode 45 are joined together, Paragraph 0044; Figure 3),
wherein the second electrode contacts to the fourth electrode (Electrode 39 and electrode 49, Paragraph 0083; Figure 6C),
wherein the first electrode is electrically connected to a first element (floating diffusion FD) (First electrode 35 which is on the first wiring layer 31 is connected to a floating diffusion FD through plugs 32 and 34 and the wiring 33, Paragraphs 0044-0046, 0048),
wherein the second electrode (39) is electrically connected to a second element (first or second wiring) (In FIG. 6A, the pixel area 12 in the sensor substrate 3 of the first semiconductor chip unit 11 and an electrode 39 in which the TRG wiring 38 and the GND wiring 55 are connected to a wiring on the circuit substrate 9 side are shown. As shown in FIG. 6A, the TRG wiring 38 and the GND wiring 55 cross the pixel area 12 in the horizontal direction in the drawing, and is connected to the electrode 39 provided in the peripheral area of the pixel area 12, Paragraph 0079-0086), and
wherein the first element and the second element are different (As mentioned above, the first element is a FD while the second element is wiring, Paragraphs 0044-0048; 0079-0086).
Regarding Claim 2, Yanagita et al. disclose the light detecting device according to claim 1, wherein the first element is a floating diffusion or a photoelectric conversion region (As mentioned above, the first element is a FD while the second element is wiring, Paragraphs 0044-0048; 0079-0086).
With regard to Claim 3, Yanagita et al. disclose the light detecting device according to claim 2, wherein the second element is a first wiring in the first wiring layer or a second wiring in the second wiring layer (In FIG. 6A, the pixel area 12 in the sensor substrate 3 of the first semiconductor chip unit 11 and an electrode 39 in which the TRG wiring 38 and the GND wiring 55 are connected to a wiring on the circuit substrate 9 side are shown. As shown in FIG. 6A, the TRG wiring 38 and the GND wiring 55 cross the pixel area 12 in the horizontal direction in the drawing, and is connected to the electrode 39 provided in the peripheral area of the pixel area 12, Paragraph 0079-0086).
Regarding Claim 4, Yanagita et al. disclose the light detecting device according to claim 3, wherein the first wiring or the second wiring is a shield wiring (GND wiring acts as a shield to the FD wiring, Paragraphs 0095-0096).
In regard to Claim 5, Yanagita et al. disclose the light detecting device according to claim 3, wherein the first wiring or the second wiring is electrically connected to a predetermined potential, a ground potential or a fixed potential (The GND wiring 55 is connected to a ground terminal or the like, which is not shown, so as to be a ground potential, Paragraph 0096).
With regard to Claim 6, Yanagita et al. disclose the light detecting device according to claim 3, wherein the first wiring or the second wiring electrically separates from the floating diffusion (At least two layers of wiring are desired on the first wiring layer 31. In FIG. 9, two layers which are a layer for forming the GND wiring 55 and a layer for forming another wiring such as the TRG wiring or the like are shown. For example, on the same layer as the wiring 33 of the FD wiring, another wiring such as the TRG wiring or the like may be formed. On the same layer as the wiring 56 of the FD wiring, the GND wiring 55 is formed, Paragraphs 0095-0097).
In regard to Claim 7, Yanagita et al. disclose the light detecting device according to claim 1, wherein the first electrode (35) and the second electrode (39) are electrically separated from each other (The first electrode 35 is formed while the second electrode 39 on a surface of the first wiring layer 31. The first electrode 35 is connected to electrode 45 while the second electrode 39 is connected to the electrode 49, Paragraphs 0044, 0083, 0091, 0111).
Regarding Claim 8, Yanagita et al. disclose the light detecting device according to claim 1, wherein the first electrode (35) is electrically independent from the second electrode (39) (The first electrode 35 is formed while the second electrode 39 on a surface of the first wiring layer 31. The first electrode 35 is connected to electrode 45 while the second electrode 39 is connected to the electrode 49, Paragraphs 0044, 0083, 0091, 0111).
With regard to Claim 9, Yanagita et al. disclose the light detecting device according to claim 1, wherein the second semiconductor layer has a first region and a second region, and the first region is separated from the second region (On the circuit substrate 9, the control circuit of the pixel unit which is not shown or the logic circuit including the signal processing circuit is mounted. In addition, on the circuit substrate 9, a pixel transistor other than the transfer transistor Tr1 is formed. In FIG. 3, an amplification transistor Tr5 and a selection transistor Tr6 are shown. On a surface of the circuit substrate 9, diffusion regions 27, 28, and 29 which are source/drain of the amplification transistor Tr5 and the selection transistor Tr6 are formed. In addition, an amplification gate electrode 25 and a selection gate electrode 26 are formed on the circuit substrate 9, Paragraph 0049; Figure 3).
Regarding Claim 10, Yanagita et al. disclose the light detecting device according to claim 9, wherein the isolation region is a full trench (An element isolation unit 69 is provided between the photodiodes PD. A periphery of the photodiode PD is surrounded by the element isolation unit 69, and each of the photodiodes PD is isolated by the element isolation unit 69. The photodiodes PD are isolated by the element isolation unit 69, thereby preventing color mixing between pixels, Paragraphs 0124, 0130).
In regard to Claim 11, Yanagita et al. disclose the light detecting device according to claim 1, wherein the third electrode (electrode 45) is electrically connected to the amplification transistor, a reset transistor or a select transistor (A region 37 in which the first electrode 35 and the second electrode 45 are formed is smaller than an area of a region 36 in which the plurality of photodiodes PD 1 to PD 4 that share the amplification transistor Tr5 are formed, Paragraph 0055).
Regarding Claim 12, Yanagita et al. disclose the light detecting device according to claim 1, wherein the fourth electrode (49) is electrically connected to a first wiring in the first wiring layer or a second wiring in the second wiring layer (The fourth electrode 49 is connected to a circuit element or the like which is formed on the circuit substrate 9 through the plugs 42 and 44 and the wiring 48. In an outer peripheral portion of the pixel area 12, the TRG wiring 38 and the GND wiring 55 are connected with the circuit element of the circuit substrate 9 through the third electrode 39 and the fourth electrode 49. In the third electrode 39 and the fourth electrode 49, a plurality of electrodes are disposed in a matrix shape in a periphery of the pixel area 12. The third electrode 39 and the fourth electrode 49 may be formed to have, for example, a size of about 1 to 20 micrometers, and thereby formed at equal intervals of about 1 micrometer from the neighboring electrode., Paragraphs 0084-0085).
With regard to Claim 13, Yanagita et al. disclose the light detecting device according to claim 12, wherein the first wiring or the second wiring is a shield wiring (It is possible to shield the FD wiring in the second wiring layer 41 on the circuit substrate 9, Paragraphs 0099, 0101, 0104).
Regarding Claim 14, Yanagita et al. disclose the light detecting device according to claim 12, wherein the first wiring or the second wiring is electrically connected to a predetermined potential, a ground potential or a fixed potential (The GND wiring 55 is connected to a ground terminal or the like, which is not shown, so as to be a ground potential, Paragraph 0096).
In regard to Claim 15, Yanagita et al. disclose the light detecting device according to claim 12, wherein the first wiring or the second wiring electrically separates a floating diffusion (At least two layers of wiring are desired on the first wiring layer 31. In FIG. 9, two layers which are a layer for forming the GND wiring 55 and a layer for forming another wiring such as the TRG wiring or the like are shown. For example, on the same layer as the wiring 33 of the FD wiring, another wiring such as the TRG wiring or the like may be formed. On the same layer as the wiring 56 of the FD wiring, the GND wiring 55 is formed, Paragraphs 0095-0097).
With regard to Claim 16, Yanagita et al. disclose the light detecting device according to claim 1, wherein the third electrode (45) and the fourth electrode (49) are electrically separated from each other (The first electrode 35 is connected to third electrode 45 while the second electrode 39 is connected to the fourth electrode 49, Paragraphs 0044, 0083, 0091, 0111).
Regarding Claim 17, Yanagita et al. disclose the light detecting device according to claim 1, wherein the third electrode (45) is electrically independent from the fourth electrode (49) (The first electrode 35 is connected to third electrode 45 while the second electrode 39 is connected to the fourth electrode 49, Paragraphs 0044, 0083, 0091, 0111).
In regard to Claim 18, Yanagita et al. disclose a light detecting device (Light detecting solid-state imaging device, Abstract; Paragraphs 0045, 0137; Figure 16), comprising:
a first semiconductor layer including a photoelectric conversion region and a floating diffusion region (First semiconductor substrate/sensor substrate 3 includes the photodiodes and floating diffusion FD, Paragraphs 0040-0044; Figure 3);
a second semiconductor layer including an amplification transistor (Circuit substrate 9 contains the amplification transistor Tr5, Paragraph 0049; Figure 3);
a first wiring layer (31) including a first electrode (35) and a second electrode (39) (First wiring layer 31 of the substrate 3 includes a first electrode 35. Third electrode 39 is also formed on a first wiring layer 31 of the sensor substrate 3, Paragraphs 0044, 0083; Figure 6C); and
a second wiring layer including a third electrode (45) and a fourth electrode (49) (Second wiring layer 41 includes a second electrode 45 and a fourth electrode 49, Paragraphs 0044; 0083; Figure 6C),
wherein the first electrode contacts to the third electrode (Electrode 35 and electrode 45 are joined together, Paragraph 0044; Figure 3),
wherein the second electrode contacts to the fourth electrode (Electrode 39 and electrode 49, Paragraph 0083; Figure 6C),
wherein the first electrode is electrically connected to the floating diffusion (floating diffusion FD) (First electrode 35 which is on the first wiring layer 31 is connected to a floating diffusion FD through plugs 32 and 34 and the wiring 33, Paragraphs 0044-0046, 0048),
wherein the third electrode (45) is electrically connected to an amplification transistor (A region 37 in which the first electrode 35 and the second electrode 45 are formed is smaller than an area of a region 36 in which the plurality of photodiodes PD 1 to PD 4 that share the amplification transistor Tr5 are formed, Paragraph 0055), and
wherein the second semiconductor layer (9) has a first region and a second region, and the first region is separated from the second region (On the circuit substrate 9, the control circuit of the pixel unit which is not shown or the logic circuit including the signal processing circuit is mounted. In addition, on the circuit substrate 9, a pixel transistor other than the transfer transistor Tr1 is formed. In FIG. 3, an amplification transistor Tr5 and a selection transistor Tr6 are shown. On a surface of the circuit substrate 9, diffusion regions 27, 28, and 29 which are source/drain of the amplification transistor Tr5 and the selection transistor Tr6 are formed. In addition, an amplification gate electrode 25 and a selection gate electrode 26 are formed on the circuit substrate 9, Paragraph 0049; Figure 3).
With regard to Claim 19, Yanagita et al. disclose the light detecting device according to claim 18, wherein the isolation region is a full trench (An element isolation unit 69 is provided between the photodiodes PD. A periphery of the photodiode PD is surrounded by the element isolation unit 69, and each of the photodiodes PD is isolated by the element isolation unit 69. The photodiodes PD are isolated by the element isolation unit 69, thereby preventing color mixing between pixels, Paragraphs 0124, 0130).
In regard to Claim 20, Yanagita et al. disclose the light detecting device according to claim 18, wherein a first region of the second semiconductor layer (9) includes the amplification transistor and a second region of the second semiconductor layer includes a reset transistor, a select transistor or a region which electrically connects to a ground potential (On the circuit substrate 9, the control circuit of the pixel unit which is not shown or the logic circuit including the signal processing circuit is mounted. In addition, on the circuit substrate 9, a pixel transistor other than the transfer transistor Tr1 is formed. In FIG. 3, an amplification transistor Tr5 and a selection transistor Tr6 are shown. On a surface of the circuit substrate 9, diffusion regions 27, 28, and 29 which are source/drain of the amplification transistor Tr5 and the selection transistor Tr6 are formed. In addition, an amplification gate electrode 25 and a selection gate electrode 26 are formed on the circuit substrate 9, Paragraph 0049; Figure 3).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRITHAM DAVID PRABHAKHER whose telephone number is (571)270-1128. The examiner can normally be reached Monday to Friday 8:00 am to 5:00 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached at 5712727372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Pritham David Prabhakher
Patent Examiner
Pritham.Prabhakher@uspto.gov
/PRITHAM D PRABHAKHER/Primary Examiner, Art Unit 2638
Prosecution Insights