Prosecution Insights
Last updated: August 17, 2026
Application No. 18/946,545

POWER AND PERFORMANCE MANAGEMENT OF PERIPHERAL COMPONENT INTERCONNECT EXPRESS DEVICES

Non-Final OA §102§103
Filed
Nov 13, 2024
Examiner
CHOUDHURY, ZAHID
Art Unit
2175
Tech Center
2100 — Computer Architecture & Software
Assignee
Qualcomm Incorporated
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
640 granted / 749 resolved
+30.4% vs TC avg
Moderate +9% lift
Without
With
+8.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
11 currently pending
Career history
757
Total Applications
across all art units

Statute-Specific Performance

§101
5.5%
-34.5% vs TC avg
§103
47.3%
+7.3% vs TC avg
§102
26.8%
-13.2% vs TC avg
§112
8.5%
-31.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 749 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Claim limitation in claims 15-20 “means for detecting……means for initiating …means for configuring… means for tracking…. means for determining… means for minimizing….. means for setting….. means for determining.... means for setting….. means for determining…… ; and means for configuring have been interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because it uses/they use a generic placeholder “means for” coupled with functional language “detecting” “initiating” “configuring” “tracking” “determining” “minimizing” “setting” “determining” “setting” “determining” and “configuring” without reciting sufficient structure to achieve the function. Furthermore, the generic placeholder is not preceded by a structural modifier. Since the claim limitation(s) invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, claim(s) 21 has/have been interpreted to cover the corresponding structure described in the specification that achieves the claimed function, and equivalents thereof. A review of the specification shows that the following appears to be the corresponding structure described in the specification for the 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph limitation: Fig.3-Fig.8 [0031]-[0038]. [0043]-[0065] If applicant wishes to provide further explanation or dispute the examiner’s interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action. If applicant does not intend to have the claim limitation(s) treated under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112 , sixth paragraph, applicant may amend the claim(s) so that it/they will clearly not invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, or present a sufficient showing that the claim recites/recite sufficient structure, material, or acts for performing the claimed function to preclude application of 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3,5-10,12-17 and 19-20 are rejected under 35 U.S.C. 102(a(2) as being anticipated (Weiner et al. (Weiner) (Pub No. US 2026/0133615). Regrading Claim 1 Weiner discloses: an apparatus [Fig.1 and Fig.3] for data communication, comprising: an interface circuit configured to provide an interface with a wired data link connected with a link partner; [[0050] oot complex 106 may be operatively coupled via signal conductors 103. The signal conductors 103 may be high-speed interconnects, facilitating data transfer and communication between the end-point devices 104A, 104B, 104C, the switching circuitry 107, and the root complex 106. Specifically, the signal conductors 103 may be implemented as PCIe links, a standard for serial expansion buses and devices.] and a controller [Fig.1, item 107 and 102] configured to: detect a transition of the wired data link from an active state to a standby state; [[0031], [0033] PCIe link to enter a lower power state (e.g., L1, L2, L3),] [0052] This distributive capability of the control unit's functions ensures that dynamic power management can be effectively implemented throughout the PCIe-based interconnect architecture 100, optimizing energy efficiency and system performance.] initiate a timeout period in response to the transition of the wired data link to the standby state, [[0034], wake-up time corresponds to timeout period, which stats after the PCIe link transition into lower power state] the timeout period being determined based on a predicted link idle time of the wired data link; [[0034] leverage historical link usage information and predicted future link usage information associated with the PCIe link to implement an adaptive wake-up mechanism to preemptively wake a PCIe link from a deep sleep or idle state (e.g., the L3 state). In this regard, an earlier wake-up time for the PCIe link may be scheduled based on predictions indicating the duration of inactivity. In other words, embodiments of the disclosure may calculate an optimal wake-up time that precedes the actual need for the PCIe link based on the predicted idle duration. ] and configure system resources in response to an expiration of the timeout period with the wired data link remained in the standby state. [[0034] wake-up time that precedes the actual need for the PCIe link based on the predicted idle duration. [[0051] control unit 102 may further be configured to adjust the standby entrance timers based on similar predictive and historical bandwidth usage data, allowing for more efficient transitions into and out of low power states, such as L1, L2, or L3, depending on the expected period of inactivity. Additionally, the control unit 102 may be configured to implement an adaptive wake-up mechanism for the signal conductors 103 from idle states, such as the L3 state, scheduling wake-ups based on the predicted duration of inactivity to balance the need for responsiveness with energy conservation.] Regrading Claim 2 Weiner discloses: the controller is further configured to: track at least one of a wakeup time or a link idle time of the wired data link; determine the predicted link idle time based on at least one of the wakeup time or the link idle time; and determine a duration of the timeout period based on the predicted link idle time. [[0031]-[0034] Leverage historical link usage information and predicted future link usage information associated with the PCIe link to dynamically adjust the L0p timers. For instance, if the predictions suggest an imminent decrease in link usage, the L0p timers can be shortened to allow quicker transitions to energy-saving states. Similarly, if an increase in usage is anticipated, the L0p timers can be shortened to allow quicker transitions to high performance states to accommodate the expected demand. In instances where the historical link usage information and predicted future link usage information conflict, the L0p timers may either be maintained at their default values or adjusted upwards, thereby extending the transition waiting time.] Regrading Claim 3 Weiner discloses: in response to the predicted link idle time being greater than a first predetermined value, minimize the timeout period; and in response to the predicted link idle time being less than a second predetermined value that is less than the first predetermined value, set the timeout period equal to a sum of the predicted link idle time plus an offset. [[0034] leverage historical link usage information and predicted future link usage information associated with the PCIe link to implement an adaptive wake-up mechanism to preemptively wake a PCIe link from a deep sleep or idle state (e.g., the L3 state). In this regard, an earlier wake-up time for the PCIe link may be scheduled based on predictions indicating the duration of inactivity. the goal is to find a middle ground for the wake-up timing that avoids the extremes of waking too early. In essence, timeout period can be adjusted based on historical link uses and predicated link usages. [[0041] Determining may also include ascertaining that a parameter matches a predetermined criterion, including that a threshold has been met, passed, exceeded, satisfied, etc] Regrading Claim 5 Weiner discloses: determine the plurality of link idle times based on a plurality of past link wakeup times. [[0034] leverage historical link usage information and predicted future link usage information associated with the PCIe link to implement an adaptive wake-up mechanism to preemptively wake a PCIe link from a deep sleep or idle state (e.g., the L3 state). In this regard, an earlier wake-up time for the PCIe link may be scheduled based on predictions indicating the duration of inactivity. the goal is to find a middle ground for the wake-up timing that avoids the extremes of waking too early. In essence, timeout period can be adjusted based on historical link uses and predicated link usages. [[0041] Determining may also include ascertaining that a parameter matches a predetermined criterion, including that a threshold has been met, passed, exceeded, satisfied, etc] Regrading Claim 6 Weiner discloses: the controller is further configured to configure the system resources by adjusting at least one of a clock frequency or a voltage of the apparatus to support a bandwidth of the wired data link in the standby state. [[0030] reductions in power via decreased clock speeds (the L0s state) to more substantial power cuts by powering down the link entirely (transitioning into the L1, L2, or L3 states) [0027] PCIe specification includes various low power standby states—L1, L2, and L3—that are designed to regulate power consumption in PCIe] Regrading Claim 7 Weiner discloses: the controller is further configured to: detect a first transition of the wired data link from the active state to the standby state; initiate a first timeout period in response to the first transition of the wired data link to the standby state; detect a second transition of the wired data link from the active state to the standby state; and initiate a second timeout period in response to the second transition of the wired data link to the standby state, the first timeout period and the second timeout period being different in duration. [[0032], leverage historical link usage information and predicted future link usage information associated with the PCIe link to dynamically adjust the L0p timers, [0033] leverage historical link usage information and predicted future link usage information associated with the PCIe link to adjust stand-by entrance timers. If predictions suggest an extended period of low or no traffic in the PCIe link, the standby entrance timers to transition to a lower state may be dynamically shortened. This allows the PCIe link to quickly enter a lower power state (e.g., L1, L2, L3), thereby saving energy during periods of inactivity., [0034] leverage historical link usage information and predicted future link usage information associated with the PCIe link to implement an adaptive wake-up mechanism to preemptively wake a PCIe link from a deep sleep or idle state (e.g., the L3 state)] Claims 8 and 15 are having similar limitations to that of the apparatus of claim 1. Accordingly, claims 8 and 15 are rejected under a similar rational as that of claim 1 above. Claims 9 and 16 are having similar limitations to that of the apparatus of claim 2. Accordingly, claims 9 and 16 are rejected under a similar rational as that of claim 2 above. Claims 10 and 17 are having similar limitations to that of the apparatus of claim 3. Accordingly, claims 10 and 17 are rejected under a similar rational as that of claim 3 above. Claims 12 and 19 are having similar limitations to that of the apparatus of claim 5. Accordingly, claims 12 and 19 are rejected under a similar rational as that of claim 5 above. Claims 13 and 20 are having similar limitations to that of the apparatus of claim 6. Accordingly, claims 13 and 20 are rejected under a similar rational as that of claim 6 above. Claims 14 having similar limitations to that of the apparatus of claim 7. Accordingly, claim 14 is rejected under a similar rational as that of claim 7 above. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 4, 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over anticipated (Weiner et al. (Weiner) (Pub No. US 2026/0133615) in view of Eckert et al. (Pub No. US 2014/0181553). Regrading Claim 4 Weiner discloses: determine an average link idle time of a plurality of link idle times tracked by the apparatus; [[0034] [[0034] leverage historical link usage information and predicted future link usage information associated with the PCIe link to implement an adaptive wake-up mechanism to preemptively wake a PCIe link from a deep sleep or idle state (e.g., the L3 state). In this regard, an earlier wake-up time for the PCIe link may be scheduled based on predictions indicating the duration of inactivity. the goal is to find a middle ground for the wake-up timing that avoids the extremes of waking too early. In essence, timeout period can be adjusted based on historical link uses and predicated link usages. Weiner does not teach set the predicted link idle time based on the average link idle time. However, Eckert teaches: set the predicted link idle time based on the average link idle time. [[0023] computing an average idle state duration and basing a prediction] Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to use average idle time to set the predicated link idle time as taught by Eckert in Weiner’s system . A person with ordinary skill in the art would have been motivated to combine Weiner and Eckert to precisely predict the length of upcoming link idle periods and improve system throughputs by reducing wakeup latency. Claims 11 and 18 are having similar limitations to that of the apparatus of claim 4. Accordingly, claims 11 and 18 are rejected under a similar rational as that of claim 4 above. Citation of Relevant Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: -Prior art Wang et al. (Patent NO. US, 9,256,268) teaches a data communication comprising an interface circuit providing an interconnect link between upstream and downstream port and a controller configured to detect when the link become idle and initiating entry into a low-power state. The link state change timeout value should be adaptively adjusted at run time, based on traffic pattern. Upon the timeout/decision block firing, the input clock signal rate could be reduced or the clock signals could be shutoff. -Prior art Bircher et al. (Patent No. US 9,110,671) teaches a prediction unit that generate a predication of idle state duration based on a history of duration of intervals in which the functional unit was in the idle state. -Prior art PCI Express® Base Specification Revision 4.0 Version 0.3 (PDF) by Bill Haffner discloses (with regard to claim 1) an apparatus for data communication, comprising: page 49/fig. 1-1: component A or B (section 1.2); page 50/fig. 1-2: CPU or PCle endpoint (section 1.3); an interface circuit configured to provide an interface with a wired data link connected with a link partner; and page 50/fig. 1-2: root complex or interface to PCle link on endpoint side; a controller implicit: each PCle interface needs a controller; configured to: - detect a transition of the wired data link from an active state to a standby state; page 259/par. 1: an idle state may be indicated by an EIOS (electrical idle ordered set) by the transmitter (section 4.2.4.2); initiate a timeout period in response to the transition of the wired data link to the standby state, the timeout period being determined based on a predicted link idle time of the wired data link; and pages 328-333, in particular page 329 (section 4.2.6.6.1.1): entering Rx_L0s.Idle after TTX-IDLE-MIN, page. 333 (section 4.2.6.7.1): analogue; As no clear technical limitation can be associated with the term "predicted" (see statements under section VIII), that attribute can assigned to every timeout time; - configure system resources in response to an expiration of the timeout period with the wired data link remained in the standby state pages 271-272 (sections 4.2.5.6 - 4.2.5.8) and pages 328-335 (4.2.6.6 - 4.2.6.8): states LOs, L1 and L2 are standby states. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZAHID CHOUDHURY whose telephone number is (571)270-5153. The examiner can normally be reached Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ZAHID CHOUDHURY/Primary Examiner, Art Unit 2175
Read full office action

Prosecution Timeline

Nov 13, 2024
Application Filed
Jul 13, 2026
Non-Final Rejection mailed — §102, §103
Aug 12, 2026
Interview Requested

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
94%
With Interview (+8.8%)
2y 8m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 749 resolved cases by this examiner. Grant probability derived from career allowance rate.

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