Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
The IDS, filed 11/13/24, has been considered.
Claim Rejections - 35 USC § 112
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claim 1/12/20, it is not clear of what “a second number of the second bit in the first data” or “first number of the first bit in the first data” represent. The claim does not define what these numbers represent. The only information known is the first data including first and second bits. According to the claim limitations, the first data only contain the first and second bits. Does the first data include the first number and second number (also third number and fourth number in claim 2)? Is so, this information needs to be added to the claim language for clarification.
It is unclear what a second number of the second bit in the first data represent. Is the second number a part of the second bit? Is the second number a number derived from an operation on the data? It is unclear what a first number of the first bit in the first data represent. Is the first number a part of the first bit? Is the first number a number derived from an operation on the data? Applicant should amend the claim to define what the second number and first number represent, such as “wherein a first bit number representing the number/count of bits in the first data in a first state, and a second bit number representing the number/count of bits in the first data in a second state”. This would clarify what the first/second bit number represents.
For purposes of examination, the Examiner will broadly interpret that the claim data is inverted when one parameter/variable related to the data is greater than another parameter/variable.
In claim 2, it is not clear what “a third number” and a “fourth number” represent. The same reasoning applied to claim 1 is applicable here. Clarification is required.
In claim 2, the limitation “a third number of the first bit in the second data is larger than a fourth number of the second bit in the second data” is vague and indefinite. It is unclear as what the third number and fourth numbers are and how they contribute the invention.
As to claim 8, it is unclear what a “second difference” represent. Is there a first difference? What is this difference of parameters/variables?
Dependent claims 2-11, 13-19 are rejected as including the deficiencies of the parent claim 1/12.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 6-12, and 16-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4, 5, 8-10, 12, 13, 16, and 17 of U.S. Patent No. 12,175,100.
Claim(s) 1, 2, 4, 5, 8-10, 12, 13, 16, and 17 of patent # 12,175,100 contain(s) every element of claim(s) of the instant application and as such anticipate(s) claim(s) 1, 6-12, and 16-20 of the instant application.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Below is an example claim mapping between the current application and patent:
Current Application
A memory system, comprising:
a memory device comprising memory cells, a memory cell being configured to be programmed to one of a first state and a second state, the first state corresponding to a first bit, and the second state corresponding to a second bit, and a memory controller coupled to the memory device and configured to: receive first data including bits, the bits of the first data including the first bit and the second bit; in response to a second number of the second bit in the first data being larger than a first number of the first bit in the first data, perform a first flipping operation to the first data to obtain a second data including the bits; and store the second data to the memory device.
Patent 12,175,100
A memory system, comprising:
a memory device comprising memory cells, and a memory controller comprising circuitry configured to: receive data that is to be written into the memory device, each memory cell having a first state and a second state, the data including bits each corresponding to one of the first state and the second state; count a first bit number of the bits corresponding to the first state and a second bit number of the bits corresponding to the second state in the received data; in response to the second bit number of the bits corresponding to the second state being larger than the first bit number of the bits corresponding to the first state, perform a first flipping operation to flip the bits in the received data; and store the received data with the flipped bits to the memory device.
As can be seen above, claim 1 of the instant application is a broadening claim of claim 9 of the patent. Claim 9 of the patent includes all of the limitations of claim 1 of the instant application, and further limitations, anticipating claim 1 of the instant application.
Independent claim 12 is similarly anticipated by claim 1 of the patent for the same reason.
Independent claim 20 is similarly anticipated by claim 17 of the patent for the same reason.
Dependent claims 16-19 are similarly anticipated by claims 1, 2, 4, 5, or 8 of patent 12,175,100.
Depending claims 6-11 are similarly anticipated by claims 9, 10, 12, 13, or 16 of patent 12,175,100.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8, 9, 11-17, 19, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ahn (US20100302856).
As to claim 1, 12, 20:
Ahn teaches a memory system (device 100; Fig. 1; 0002, 0007, 0008), associated method of operation (0002, 0007, 0009, 0010), and associated instructions in memory for performing the method (0002, 0007, 0009, 0010); comprising:
a memory device comprising memory cells, a memory cell being configured to be programmed to one of a first state and a second state, the first state corresponding to a first bit, and the second state corresponding to a second bit (flash memory device having cells; 0005, 0006, 0010, 0030; data bit having state 0 or 1; 0021, 0029, 0030), and a memory controller (control circuit, 0008, 0011, 0030, 0031) coupled to the memory device and configured to: receive first data including bits, the bits of the first data including the first bit and the second bit (receive input data to be written to memory cells; 0005, 0007, 0008, 0009, 0011); in response to a second number of the second bit in the first data being larger than a first number of the first bit in the first data, perform a first flipping operation to the first data to obtain a second data including the bits; and store the second data to the memory device (if the count of a first data is greater than a specific amount, invert data and store in memory cells; 0008, 0009, 0030, 0031).
As to claim 2, 13:
Ahn teaches a third number of the first bit in the second data is larger than a fourth number of the second bit in the second data (count of a first data is greater thana specific amount, invert data and store in memory cells; 0008, 0009, 0030, 0031.
As to claim 3, 4, 14, 15:
Ahn teaches wherein a portion/all of the bits in the second data are from flipped bits that the first flipping operation is performed (portion or all of bits can be inverted based on the count of a first data being greater than a specific amount, invert data and store in memory cells; 0008, 0009, 0030, 0031).
As to claim 5:
Ahn teaches the memory controller is configured with an inverter to perform the first flipping operation (data is inverted; 0009, 0031).
As to claim 8, 16:
Ahn teaches the memory controller is further configured to: perform the first flipping operation in response to the second number being larger than the first number by a second difference that is greater than a threshold (interpretation: flip data when a parameter is greater than a threshold; if the count of a first data is greater than a specific amount, invert data and store in memory cells; 0008, 0009, 0030, 0031).
As to claim 9, 17:
Ahn teaches the memory controller is further configured to: store a flipping flag to the memory device, the flipping flag indicating whether the first flipping operation has been performed to the first data (flag cell stores information if inverter operation has been performed; 0031-0032).
As to claim 11, 19:
Ahn teaches the memory device is a phase change memory (PCM) device, and the first state and the second state correspond to a crystalline state and an amorphous state, respectively (nonvolatile memory having logic 0/1 states; 0004-0005, 0030).
Allowable Subject Matter
Claims 6, 7, 10, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 6-7, the prior art of record does not further suggest the memory system of claim 1, wherein the memory controller is further configured to count the first number of the first bit in the first data and the second number of the second bit in the first data.
As to claim 10/18, the prior art of record does not further suggest the memory system of claim 9/17, wherein the memory controller is further configured to: read, from the memory device, the second data and the flipping flag; and in response to the flipping flag indicating that the first flipping operation has been performed on the first data, perform a second flipping operation to flip the flipped bits in the second data.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAN NGUYEN whose telephone number is (571)272-4198. The examiner can normally be reached M-F 7:00am -4:00pm.
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/THAN NGUYEN/Primary Examiner, Art Unit 2138