Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the communication, filed 9/14/26.
Claims 1-8, 11-16, and 19-24 are pending.
The terminal disclaimer filed on 9/14/26 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of the US 12,175,100 patent has been reviewed and is accepted. The terminal disclaimer has been recorded.
In view of the terminal disclaimer, filed 9/14/26, the previous double patenting rejection to claims 1, 6-8, 12, 16, 19, and 20-23 is withdrawn.
The indicated allowability of claims 2-5, 11, 13-15, and 24 is withdrawn in view of the newly discovered reference(s) to Cho et al (US20090091991A1). Rejections based on the newly cited reference(s) follow.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 12-16, 20, and 23-24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al ((US20090091991A1, “Cho”).
As to claim 1, 12, 20:
Cho teaches a memory system ([0006], [0007], [0050]-[0052]; multi-bit programming apparatus 200 is identified; page-programming operations and programming of multi-bit data), associated method of operation ([0006]-[0009], [0015]-[0019]), and non-transitory computer-readable medium storing instructions performing the method ([0006, [0018]-[0019]) comprising comprising :
a memory device comprising memory cells ([0003], [0004], [0050]-[0052], [0061]; memory cell storing logic 1 or 0),
one memory cell of the memory cells being configured to be programmed to one of a first state and a second state ([0003], [0020], [0071], [0101]-[0103] cell values of"1" and "0" associated with different programmed threshold-voltage ranges).
the first state corresponding to a first bit, and the second state corresponding to a second bit ([0020], [0051], [0071], first value = 1 and second value = 0, or vice versa), and
a memory controller ([0045], [0050], [0057], [0061], input control unit determining inversion and generating second data; programming the generated data into cell array) coupled to the memory device and configured to:
receive first data including bits the bits of the first data including the first bit and the second bit ([0046], [0051], [0057], [0160]; page buffer 110 stores first data including at least one bit. [0051] states that page buffer 210 stores first data including a plurality of bits),
in response to a second number of the second bit in the first data being larger than a first number of the first bit in the first data ([0063], [0084], [0168]-[0169]; For the N-th programming operation, when the number of 0s is greater than the number of 1s, the input control unit inverts the first data),
perform a first flipping operation on the first data ([0047], [0063], [0084], [0169]; inverting first data to generate second data; when #0 > #1 during the N-th operation, the first data is inverted)
to obtain second data including the bits ([0046]-[0047], [0057], [0063], [0161], second data is generated from first data and that inversion produces second data),
wherein the first number indicates a count of the first bit in the first data, and the second number indicates a count of the second bit in the first data ([0057], [0062]-[0063], [0081], [0084], [0160], [0166], [0168], counts numbers of 1s and 0s among the first data);
store the second data and a flipping flag to the memory device ([0061], [0082]-[0085], [0091]-[0093], generated second data is programmed into page 250 of multi-bit cell array 240),
the flipping flag indicating whether the first flipping operation has been performed on the first data ([0082], [0085], [0093], flag 493 is generated based on whether second data is an inverted version of first data);
read, from the memory device, the second data and the flipping flag ([0093]-[0095], control unit 560 receives the flag from flag storage unit 550 and second data from the multi-bit cell); and
in response to the flipping flag indicating that the first flipping operation has been performed on the first data ([0093], [0095], flag = 1 indicates that second data is an inverted version of first data. [0095] states that the output control unit acts based on the received flag),
perform a second flipping operation to flip flipped bits in the second data ([0095], when the received flag is in the first logic state (1), output control unit 560 inverts the received second data to recover the first data).
As to claim 2, 13:
Cho teaches a third number count of the first bit in the second data is larger than a fourth number count of the second bit in the second data ([0063], [0084], [0168]-[0169]; For the N-th programming operation, when the number of 0s is greater than the number of 1s, the input control unit inverts the first data),
As to claim 3, 14:
Cho teaches a portion of the bits in the second data are the flipped bits resulting from the first flipping operation is performed ([0047], [0063], [0084], [0169], generates second data by inverting bits of first data).
As to claim 4, 15:
Cho teaches the second data is obtained based on the first flipping operation being performed to flip all the bits in the first data ([0047], [0084], second data is generated from inverting first data, bit inversion changes each 0 to 1 and each 1 to 0).
As to claim 5:
Cho teaches the memory controller is configured with an inverter configured to perform the first flipping operation ([0047], [0063], [0084], invert data bit to generate second data).
As to claim 6:
Cho teaches the memory controller is further configured to count the first number of the first bit in the first data and the second number of the second bit in the first data ([0057], [0062]–[0063], [0081], [0084], [0166], [0168], count number of 0s and 1s in data).
As to claim 7:
Cho teaches the memory controller is configured with a counter that is configured to count the first number of the first bit in the first data and the second number of the second bit in the first data ([0057], [0062]–[0063], [0081], [0084], [0166], [0168], count number of 0s and 1s in data).
As to claim 8, 16:
Cho teaches the memory controller is further configured to: perform the first flipping operation in response to a difference between the second number being larger than and the first number by a second difference that is being greater than a threshold ([0063], [0084], [0168]-[0169]; For the N-th programming operation, when the number of 0s is greater than the number of 1s, the input control unit inverts the first data),
As to claim 23:
Cho teaches the second data is included in user data of a codeword ([0047], [0061] second data generated from first data and programmed into the multi-bit cell array).
As to claim 24:
Cho teaches the flipping flag is stored in spare data associated with the user data ([0082], [0085], [0091]–[0093], flag generated and stored in a flag storage unit).
Allowable Subject Matter
Claims 11, 19, and 21-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 11/19, the prior art does not further suggest the invention of claim 1/12, wherein the memory device is a phase change memory (PCM) device, and the first state and the second state correspond to a crystalline state and an amorphous state, respectively.
As to claim 21-22, the prior art does not further suggest the invention of claim 1/21, wherein the memory controller is configured to: encode the second data to generate error correction code (ECC) parity information; and store the ECC parity information to the memory device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAN NGUYEN whose telephone number is (571)272-4198. The examiner can normally be reached M-F 7:00am -4:00pm.
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/THAN NGUYEN/Primary Examiner, Art Unit 2138
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