DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-18 are pending. Claims 1 and 13 have been amended as per Applicants' request.
Papers Submitted
It is hereby acknowledged that the following papers have been received and placed of record in the file:
Amended Claims as filed on September 14, 2026
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on September 14, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5-9, and 12-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Winterfeld (US 2023/0229340) (hereinafter Winterfeld) (published July 20, 2023) in view of FUKUTOMI et al. (US 2013/0238838) (hereinafter Fukutomi) (published September 12, 2013).
Regarding Claims 1 and 13, taking claim 1 as exemplary, Winterfeld discloses a storage system comprising: a storage device including first and second memory blocks; and
“Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single-level cells (SLC) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLCs) can store multiple bits per cell” (Winterfeld [0027])
a controller configured to perform: a control operation of controlling, in response to a request, the storage device to program a requested data unit into the second memory block, the control operation including a programming operation and a movement operation, the programming operation being an operation of programming the requested data unit into the first memory block corresponding to a logical address included in the request and updating a mapping relationship between the logical address and a physical address indicating the first memory block, and the movement operation being an operation of moving the programmed data unit to the second memory block,
“Other memory sub-systems utilize the SLC as a cache to initially (e.g., prior to a coarse programming pass of the QLC) program the SLC with the data to be written to the QLC. Accordingly, the data is immediately readable from the SLC. Thereafter, the data may be moved from the SLC cache to other memory, such as QLC memory for longer-term storage (e.g., coarse and fine programming pass)… The L2P mapping table maintains, for a number of logical addresses, a one-to-one mapping to respective physical addresses (e.g., a physical location of the SLC and/or QLC). Accordingly, prior to coarse programming of the QLC, the L2P mapping table will include the physical address of the SLC cache storing the data to be written to the QLC” (Winterfeld [0015] programming to SLC/first memory block according to logical address in the L2p table, the move operation is from SLC to QLC/second memory block)
“Aspects of the present disclosure address the above and other deficiencies by maintaining a mapping of the SLC cache to the QLC (e.g., quad-to-single (Q2S) mapping table) while the data is undergoing copyback to facilitate the reading of the data from the SLC cache until fine programming of the QLC (e.g., copyback)” (Winterfeld [0016] mapping physical address of the blocks in the move from SLC to QLC)
a meta operation of recording the logical address and the physical address in a meta data unit corresponding to the requested data unit, and
“To read data from the SLC cache until the fine programming of the QLC, a logical-to-physical (L2P) mapping data structure (e.g., L2P mapping table) is maintained. The L2P mapping table maintains, for a number of logical addresses, a one-to-one mapping to respective physical addresses (e.g., a physical location of the SLC and/or QLC). Accordingly, prior to coarse programming of the QLC, the L2P mapping table will include the physical address of the SLC cache storing the data to be written to the QLC. Once the QLC is finely programmed, the L2P mapping table is updated to replace the physical address of the SLC cache with the physical address of the QLC” (Winterfeld [0015] addresses of the L2P mapping is updated)
But does not explicitly state a verification operation of verifying integrity of the mapping relationship for the moved data unit based on whether the physical address included in the meta data unit corresponding to the moved data unit matches the physical address included in the mapping relationship.
Winterfeld and Fukutomi discloses a verification operation of verifying integrity of the mapping relationship for the moved data unit based on whether the physical address included in the meta data unit corresponding to the moved data unit matches the physical address included in the mapping relationship.
“Once the QLC is finely programmed, the L2P mapping table is updated to replace the physical address of the SLC cache with the physical address of the QLC. In some instances, the L2P mapping table stores both the physical address of the SLC and the physical address of the QLC until the QLC is finely programmed, and then the physical address of the SLC is removed” (Winterfeld [0015])
“The update unit 115-2 instructs the first access control unit 151 to read the physical address information (hereinafter, referred to as physical address information before update) of the storage medium 121 corresponding to the acquired logical address information in the address mapping table and acquires the physical address information before update in the address mapping table. The update unit 115-2 compares the physical address information of the transfer source with the physical address information before update” (Fukutomi [0150])
“As a result of the comparison, when the pieces of physical address information are not identical to each other, the process of writing data which is requested to be written by the host apparatus to data with the same logical address and the transfer process overlap each other and a process of updating the address mapping table which is performed in the process of writing the data requested to be written by the host apparatus ends at least at the comparison time” (Fukutomi [0151])
“On the other hand, as a result of the comparison, when the pieces of physical address information are identical to each other, the process of updating the address mapping table which is performed in the process of writing the data requested to be written by the host apparatus does not start at least at the comparison time even when the process of writing the data which is requested to be written by the host apparatus to the data with the same logical address and the transfer process overlap each other” (Fukutomi [0152])
Fukutomi addresses the corresponding circumstance in which a transfer operation overlaps a subsequent write to the same logical address by obtaining the physical address of the transfer source, obtaining the physical address presently associated with the logical address in the mapping table, and comparing the two addresses. A mismatch indicates that the mapping has been changed by the intervening write, whereas a match indicates that the mapping remains associated with the data being transferred. Thus, although Fukutomi does not expressly label the comparison a “verification operation” or use the phrase “verifying integrity,” the comparison functions as a verification of the integrity/consistency of the mapping relationship because it verifies whether the physical address associated with the moved data continues to match the physical address maintained in the mapping relationship.
It would have been obvious before the effective filing date of the invention to a person of ordinary skill in the art to modify Winterfeld’s L2P mapping and SLC-to-QLC movement process in view of Fukutomi to include a verification operation that compares the physical address associated with the data being moved with the physical address currently associated with the same logical address in the mapping table. The motivation to make this modification would have been to prevent a movement operation involving stale data from improperly updating or replacing a newer logical-to-physical mapping created by an intervening write, thereby maintaining consistency and accuracy of the mapping information during concurrent programming and movement operations. A skilled artisan would have recognized that Winterfeld’s SLC-to-QLC movement and L2P-table update operations can occur in a system in which subsequent host writes may change the physical address associated with the same logical address. Incorporating Fukutomi’s address comparison would provide a straightforward verification operation for detecting that condition before the movement-related mapping update is applied and applying verification-by-comparison technique to L2P-controlled SLC-to-QLC movement would have produced the expected result of preserving mapping integrity when movement of previously programmed data overlaps a subsequent programming operation.
Regarding Claims 2 and 14, Winterfeld further discloses wherein the first memory block is a single-level cell (SLC) block and the second memory block is a quadruple-level cell (QLC) block.
“Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single-level cells (SLC) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLCs) can store multiple bits per cell” (Winterfeld [0027])
Regarding Claim 5, Winterfeld further discloses wherein the physical address included in the mapping relationship in the programming operation includes source offset information representing offset information of the programmed data unit in the first memory block.
“To read data from the SLC cache until the fine programming of the QLC, a logical-to-physical (L2P) mapping data structure (e.g., L2P mapping table) is maintained. The L2P mapping table maintains, for a number of logical addresses, a one-to-one mapping to respective physical addresses (e.g., a physical location of the SLC and/or QLC). Accordingly, prior to coarse programming of the QLC, the L2P mapping table will include the physical address of the SLC cache storing the data to be written to the QLC” (Winterfeld [0015])
“the table management component 113 may traverse the linked list associated with the entry of the Q2S corresponding to the physical address of the QLC to determine which physical address of the SLCs associated with the QLC to return to the host system 120. To determine which physical address of the SLCs associated with the QLC to return to the host system 120, the table management component 113 identifies a page number of the physical address of the QLC and, based on the page number of the physical address of the QLC determines which physical address of the SLCs to return to the host system 120” (Winterfeld [0042])
“Accordingly, based on the page number of the physical address of the QLC (e.g., 825), the table management component 113 can determine that the physical address of the second SLC in the linked list should be returned to the host system 120 instead of the physical address of the QLC since the QLC is not programmed” (Winterfeld [0043] the page number is the offset information that indicates where the data of SLC block is to be stored on the QLC block)
Regarding Claim 6, Winterfeld further discloses wherein the controller performs the movement operation according to a blind data copy scheme of sequentially moving a plurality of data units from a single first memory block to the second memory block.
“Aspects of the present disclosure address the above and other deficiencies by maintaining a mapping of the SLC cache to the QLC (e.g., quad-to-single (Q2S) mapping table) while the data is undergoing copyback to facilitate the reading of the data from the SLC cache until fine programming of the QLC (e.g., copyback)” (Winterfeld [0016] copyback is a type of blind data copy)
Regarding Claim 7, Winterfeld further discloses wherein the controller performs the movement operation on each of the plurality of data units so that target offset information representing offset information of the moved data unit in the second memory block and the source offset information corresponding to the moved data unit have a relationship of an equation below:
[Equation]
Osource=Otarget mod Nsource_offsets, where
“Osource” represents the source offset information, “Otarget” represents the target offset information and “Nsource_offsets” represents a number of offsets allowable or allowed in the first memory block.
“For example, each SLC contains a page number between 0-699 (e.g., 700 pages), and each QLC contains a page number between 0-2799 (e.g., 2800 pages). Thus, since each programmed SLC is sequentially appended to the linked list, a first SLC of the SLCs having a page number between 0-699 corresponds to a first portion of the QLC having a page number between 0-699, a second SLC of the SLCs having a page number between 0-699 corresponds to a second portion of the QLC having a page number between 700-1399, a third SLC of the SLCs having a page number between 0-699 corresponds to a third portion of the QLC having a page number between 1400-2099, and a fourth SLC of the SLCs having a page number between 0-699 corresponds to a fourth portion of the QLC having a page number between 2100-2799. Accordingly, based on the page number of the physical address of the QLC (e.g., 825), the table management component 113 can determine that the physical address of the second SLC in the linked list should be returned to the host system 120 instead of the physical address of the QLC since the QLC is not programmed” (Winterfeld [0043] the Osource is the page number of the SLC and Otarget is the page number of the QLC and the Nsource_offset is 700)
Regarding Claim 8, Winterfeld and Fukutomi further discloses wherein the verification operation includes an acquisition operation of acquiring, based on the equation and from the target offset information, the source offset information corresponding to the moved data unit.
“Accordingly, based on the page number of the physical address of the QLC (e.g., 825), the table management component 113 can determine that the physical address of the second SLC in the linked list should be returned to the host system 120 instead of the physical address of the QLC since the QLC is not programmed” (Winterfeld [0043] the page number is the offset information that indicates where the data of SLC block is to be stored on the QLC block)
“In addition, the update unit 115-2 calculates the page offset to which one or more pieces of data transferred to the acquired page is transferred. In this way, the update unit 115-2 acquires logical address information, the physical address information of the transfer source, and the physical address information of the transfer destination for the transferred one or more pieces of data” (Fukutomi [0149])
Regarding Claim 9, Winterfeld and Fukutomi further discloses wherein the controller performs the verification operation based on whether the physical address included in the mapping relationship matches a combination of the physical address included in the meta data unit and the source offset information acquired in the acquisition operation.
“Accordingly, based on the page number of the physical address of the QLC (e.g., 825), the table management component 113 can determine that the physical address of the second SLC in the linked list should be returned to the host system 120 instead of the physical address of the QLC since the QLC is not programmed” (Winterfeld [0043] the physical address of the SLC is a combination of the QLC physical address and page number to identify the mapping)
“The update unit 115-2 instructs the first access control unit 151 to read the physical address information (hereinafter, referred to as physical address information before update) of the storage medium 121 corresponding to the acquired logical address information in the address mapping table and acquires the physical address information before update in the address mapping table. The update unit 115-2 compares the physical address information of the transfer source with the physical address information before update” (Fukutomi [0150])
“As a result of the comparison, when the pieces of physical address information are not identical to each other, the process of writing data which is requested to be written by the host apparatus to data with the same logical address and the transfer process overlap each other and a process of updating the address mapping table which is performed in the process of writing the data requested to be written by the host apparatus ends at least at the comparison time” (Fukutomi [0151])
“On the other hand, as a result of the comparison, when the pieces of physical address information are identical to each other, the process of updating the address mapping table which is performed in the process of writing the data requested to be written by the host apparatus does not start at least at the comparison time even when the process of writing the data which is requested to be written by the host apparatus to the data with the same logical address and the transfer process overlap each other” (Fukutomi [0152])
Regarding Claim 12, Winterfeld and Fukutomi further discloses wherein the controller is further configured to perform, between the meta operation and the verification operation, a repetition operation of repeating the control operation and the meta operation with respect to each of a plurality of requested data units, and wherein the controller performs the repetition operation on a predetermined number or rows included in the second memory block and subsequently performs the verification operation when the controller reads the data unit moved to the second memory block and determines that the read data unit to include no error.
“Certain memory sub-systems implementing QLC memory use a standard 16-16 coarse-fine, two-pass programming algorithm. Since a QLC memory cell stores four bits of data, there are 16 possible programming levels (i.e., 2.sup.4) representing the possible values of those four bits of data. Programming a wordline begins by coarsely programming all 16 levels in a first pass. The objective, of this “coarse,” first pass is to program all cells rapidly to slightly below their final target programming levels. During the slower, “fine,” second pass, the memory cells are programmed to a slightly higher final target programmed voltage. Such two-pass programming minimizes cell to cell (C2C) interference, as every cell and its neighbors are nearly at their final target programmed voltage when the fine programming pass is performed, and need only be “touched-up.” The combination of not requiring precision programming in the first pass, and the minimized C2C coupling, leads to fast programming with high read window budget (RWB). Such standard 16-16 coarse-fine programming, however, requires all data to be first written to single-level cell (SLC) memory (i.e., memory cells storing one bit of data per cell) before the first pass to protect against asynchronous power loss (APL)” (Winterfeld [0013] the second pass is the repetition operation)
“Accordingly, prior to coarse programming of the QLC, the L2P mapping table will include the physical address of the SLC cache storing the data to be written to the QLC. Once the QLC is finely programmed, the L2P mapping table is updated to replace the physical address of the SLC cache with the physical address of the QLC” (Winterfeld [0015])
“The update unit 115-2 instructs the first access control unit 151 to read the physical address information (hereinafter, referred to as physical address information before update) of the storage medium 121 corresponding to the acquired logical address information in the address mapping table and acquires the physical address information before update in the address mapping table. The update unit 115-2 compares the physical address information of the transfer source with the physical address information before update” (Fukutomi [0150])
“On the other hand, as a result of the comparison, when the pieces of physical address information are identical to each other, the process of updating the address mapping table which is performed in the process of writing the data requested to be written by the host apparatus does not start at least at the comparison time even when the process of writing the data which is requested to be written by the host apparatus to the data with the same logical address and the transfer process overlap each other. Therefore, the update unit 115-2 performs the following process which is the same as a portion of the process performed by the update unit 115” (Fukutomi [0152])
Regarding Claim 15, Winterfeld further discloses wherein the physical address included in the mapping relationship in the programming operation includes a block address of the first memory block and source offset information representing offset information of the programmed data unit in the first memory block.
“To read data from the SLC cache until the fine programming of the QLC, a logical-to-physical (L2P) mapping data structure (e.g., L2P mapping table) is maintained. The L2P mapping table maintains, for a number of logical addresses, a one-to-one mapping to respective physical addresses (e.g., a physical location of the SLC and/or QLC). Accordingly, prior to coarse programming of the QLC, the L2P mapping table will include the physical address of the SLC cache storing the data to be written to the QLC” (Winterfeld [0015])
“the table management component 113 may traverse the linked list associated with the entry of the Q2S corresponding to the physical address of the QLC to determine which physical address of the SLCs associated with the QLC to return to the host system 120. To determine which physical address of the SLCs associated with the QLC to return to the host system 120, the table management component 113 identifies a page number of the physical address of the QLC and, based on the page number of the physical address of the QLC determines which physical address of the SLCs to return to the host system 120” (Winterfeld [0042])
“Accordingly, based on the page number of the physical address of the QLC (e.g., 825), the table management component 113 can determine that the physical address of the second SLC in the linked list should be returned to the host system 120 instead of the physical address of the QLC since the QLC is not programmed” (Winterfeld [0043] the page number is the offset information that indicates where the data of SLC block is to be stored on the QLC block)
Regarding Claim 16, Winterfeld further discloses wherein the movement operation is performed on each of a plurality of data units so that target offset information representing offset information of the moved data unit in the second memory block is identical to the source offset information corresponding to the moved data unit.
“the table management component 113 may traverse the linked list associated with the entry of the Q2S corresponding to the physical address of the QLC to determine which physical address of the SLCs associated with the QLC to return to the host system 120. To determine which physical address of the SLCs associated with the QLC to return to the host system 120, the table management component 113 identifies a page number of the physical address of the QLC and, based on the page number of the physical address of the QLC determines which physical address of the SLCs to return to the host system 120” (Winterfeld [0042])
“Accordingly, based on the page number of the physical address of the QLC (e.g., 825), the table management component 113 can determine that the physical address of the second SLC in the linked list should be returned to the host system 120 instead of the physical address of the QLC since the QLC is not programmed” (Winterfeld [0043] the page number is the offset information that indicates where the data of SLC block is to be stored on the QLC block)
Regarding Claim 17, Winterfeld and Fukutomi further discloses wherein the verification operation includes an acquisition operation of acquiring, from the target offset information, the source offset information corresponding to the moved data unit.
“Accordingly, based on the page number of the physical address of the QLC (e.g., 825), the table management component 113 can determine that the physical address of the second SLC in the linked list should be returned to the host system 120 instead of the physical address of the QLC since the QLC is not programmed” (Winterfeld [0043] the page number is the offset information that indicates where the data of SLC block is to be stored on the QLC block)
“In addition, the update unit 115-2 calculates the page offset to which one or more pieces of data transferred to the acquired page is transferred. In this way, the update unit 115-2 acquires logical address information, the physical address information of the transfer source, and the physical address information of the transfer destination for the transferred one or more pieces of data” (Fukutomi [0149])
Regarding Claim 18, Winterfeld and Fukutomi further discloses wherein the verification operation is performed based on whether the physical address included in the mapping relationship matches a combination of the physical address included in the meta data unit and the source offset information acquired in the acquisition operation.
“Accordingly, based on the page number of the physical address of the QLC (e.g., 825), the table management component 113 can determine that the physical address of the second SLC in the linked list should be returned to the host system 120 instead of the physical address of the QLC since the QLC is not programmed” (Winterfeld [0043] the physical address of the SLC is a combination of the QLC physical address and page number to identify the mapping)
“The update unit 115-2 instructs the first access control unit 151 to read the physical address information (hereinafter, referred to as physical address information before update) of the storage medium 121 corresponding to the acquired logical address information in the address mapping table and acquires the physical address information before update in the address mapping table. The update unit 115-2 compares the physical address information of the transfer source with the physical address information before update” (Fukutomi [0150])
“As a result of the comparison, when the pieces of physical address information are not identical to each other, the process of writing data which is requested to be written by the host apparatus to data with the same logical address and the transfer process overlap each other and a process of updating the address mapping table which is performed in the process of writing the data requested to be written by the host apparatus ends at least at the comparison time” (Fukutomi [0151])
“On the other hand, as a result of the comparison, when the pieces of physical address information are identical to each other, the process of updating the address mapping table which is performed in the process of writing the data requested to be written by the host apparatus does not start at least at the comparison time even when the process of writing the data which is requested to be written by the host apparatus to the data with the same logical address and the transfer process overlap each other” (Fukutomi [0152])
Claims 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Winterfeld (published July 20, 2023) and Fukutomi (published September 12, 2013) as applied to claim 2 above, and further in view of Inbar et al. (US 2016/0124668) (hereinafter Inbar) (published May 05, 2016).
Regarding Claim 3, the combination of Winterfeld and Fukutomi disclosed the system of claim 2 but does not explicitly state wherein the controller performs the movement operation according to a valid data copy scheme of moving a single data unit from a single first memory block to the second memory block.
Inbar discloses wherein the controller performs the movement operation according to a valid data copy scheme of moving a single data unit from a single first memory block to the second memory block.
“Before moving or copying the data from one or more source SLC blocks 148 to a destination MLC block 150, a scan of an address data structure that tracks addressing of the data may be performed to identify which of the data in the source SLC blocks 148 is valid and which is invalid. The determination may be made on a unit basis. That is, each data unit in the source SLC blocks 148 may be identified as either valid or invalid. Subsequently, a source-to-destination mapping (otherwise referred to as a folding vector) may be generated that identifies where each of the data units are to be stored in the destination MLC block 150” (Inbar [0071])
It would have been obvious before the effective filing date of the invention to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the copyback operation in the system of the combination of Winterfeld and Fukutomi to incorporate Inbar’s valid data copy scheme. Inbar provides a known technique for selectively copying only valid data during a data movement operation. By applying this technique to the copyback operation of Winterfeld and Fukutomi it would have involved the use of a known data-selection and mapping technique for its known purpose, avoiding the unnecessary movement of invalid data, and would have predictably resulted in the controller moving only valid data units from the source memory block to the destination memory block. The motivation would be that copying invalid data during a memory management or data folding operation unnecessarily consumes programming bandwidth, memory resources, and time. By identifying valid data units before the movement operation and copying only those valid data units, as taught by Inbar, the resulting system would avoid unnecessary data transfers and reduce the amount of data that must be copied during the operation. This would also reduce the amount of data involved in subsequent folding operations and thereby reduce write amplification and associated memory management overhead.
Regarding Claim 4, Winterfeld and Fukutomi further discloses wherein the controller performs the verification operation based on whether the physical address included in the meta data unit matches the physical address included in the mapping relationship.
“Once the QLC is finely programmed, the L2P mapping table is updated to replace the physical address of the SLC cache with the physical address of the QLC. In some instances, the L2P mapping table stores both the physical address of the SLC and the physical address of the QLC until the QLC is finely programmed, and then the physical address of the SLC is removed” (Winterfeld [0015])
“The update unit 115-2 instructs the first access control unit 151 to read the physical address information (hereinafter, referred to as physical address information before update) of the storage medium 121 corresponding to the acquired logical address information in the address mapping table and acquires the physical address information before update in the address mapping table. The update unit 115-2 compares the physical address information of the transfer source with the physical address information before update” (Fukutomi [0150])
“As a result of the comparison, when the pieces of physical address information are not identical to each other, the process of writing data which is requested to be written by the host apparatus to data with the same logical address and the transfer process overlap each other and a process of updating the address mapping table which is performed in the process of writing the data requested to be written by the host apparatus ends at least at the comparison time” (Fukutomi [0151])
“On the other hand, as a result of the comparison, when the pieces of physical address information are identical to each other, the process of updating the address mapping table which is performed in the process of writing the data requested to be written by the host apparatus does not start at least at the comparison time even when the process of writing the data which is requested to be written by the host apparatus to the data with the same logical address and the transfer process overlap each other” (Fukutomi [0152])
Claim 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Winterfeld (published July 20, 2023) and Fukutomi (published September 12, 2013) as applied to claim 1 above, and further in view of Yun et al. (US 2014/0059275) (hereinafter Yun) (published February 27, 2014).
Regarding Claim 10, the combination of Winterfeld and Fukutomi disclosed the system of claim 1 but does not explicitly state wherein the storage device further includes a working memory, and wherein the meta operation includes: a temporary storage operation of temporarily storing the logical address and the physical address in the working memory; and a recording operation of recording the temporarily stored logical address and physical address into a metadata unit corresponding to the requested data unit.
Yun discloses wherein the storage device further includes a working memory, and
“The RAM 1220 may be a working memory of the memory controller 1200” (Yun [0049])
wherein the meta operation includes: a temporary storage operation of temporarily storing the logical address and the physical address in the working memory; and
“The RAM 1220 may include a mapping table 1221. The mapping table 1221 may include information for a translation operation of the FTL. The mapping table 1221 may include information on mapping relationship between a logical address of a file organized by a file system described in FIG. 2 and a physical address of the flash memory 1300. In some embodiments, in the case that a free memory block is assigned as a write memory block, the memory controller 1200 may update the mapping table 1221” (Yun [0049])
a recording operation of recording the temporarily stored logical address and physical address into a metadata unit corresponding to the requested data unit.
“the mapping table 1221 in the RAM 1220 needs to be flushed to the main mapping table 1321 in the flash memory 1300 whenever the mapping table 1221 is updated, so that the mapping table 1221 can be recovered from the main mapping table 1321” (Yun [0054])
It would have been obvious to one of ordinary skill in the art to combine the working memory and cached mapping table of Yun with the system in the combination of Winterfeld and Fukutomi. The motivation for doing so would be to improve efficiency by providing quicker address translation to request so the memory may be accessed quicker.
It would have been obvious before the effective filing date of the invention to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the system of the combination of Winterfeld and Fukutomi to include Yun’s working memory and mapping table arrangement. By applying working memory and mapping table arrangement to the system of Winterfeld and Fukutomi it would have provided a predictable implementation in which logical-to-physical address information associated with a requested data unit can first be temporarily maintained in working memory and subsequently recorded in persistent metadata storage. The motivation would be that maintaining frequently accessed mapping information in working memory provides faster access to logical-to-physical address information than repeatedly retrieving such information from nonvolatile storage. This arrangement would therefore reduce the latency and overhead associated with address translation operations and allow the storage device to more efficiently process data access and data management requests and furthermore, subsequently flushing the mapping information from working memory to persistent storage provides a mechanism for retaining the updated address mappings while avoiding the need to perform every mapping update directly in the relatively slower nonvolatile storage.
Claim 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Winterfeld (published July 20, 2023), Fukutomi (published September 12, 2013), and Yun (published February 27, 2014) as applied to claim 10 above, and further in view of Rogers et al. (US 2007/0300037) (hereinafter Rogers) (published December 27, 2007).
Regarding Claim 11, the combination of Winterfeld, Fukutomi, and Yun disclosed the system of claim 10 but does not explicitly state wherein the meta operation further includes a deletion operation of deleting, after the recording operation, the temporarily stored logical address and physical address from the working memory.
Yun and Rogers discloses wherein the meta operation further includes a deletion operation of deleting, after the recording operation, the temporarily stored logical address and physical address from the working memory.
“the mapping table 1221 in the RAM 1220 needs to be flushed to the main mapping table 1321 in the flash memory 1300 whenever the mapping table 1221 is updated, so that the mapping table 1221 can be recovered from the main mapping table 1321” (Yun [0054])
“Secondary mapping tables are cached to facilitate accessing the flash memory. In an example embodiment, a limited amount of working memory is allocated for storage of secondary mapping tables. When all of the cache slots are full and a new secondary table is to be loaded from flash memory, a secondary table is evicted to allow loading of another secondary mapping table” (Rogers [0022] the secondary mapping table with the logical address and physical address is deleted from working memory to make room for another secondary mapping table)
It would have been obvious before the effective filing date of the invention to a person of ordinary skill in the art to modify the system in the combination of Winterfeld, Fukutomi, and Yun to further incorporate Rogers’s cache-management technique for evicting a cached mapping table after the mapping information has been recorded in persistent storage. By applying Rogers’s cache-eviction technique to the working-memory mapping table it would have predictably resulted in deleting or evicting the temporarily stored logical-address and physical-address information from working memory after that information had been recorded in persistent storage, thereby freeing the corresponding working-memory resources for subsequent mapping information. The motivation would be that the amount of working memory available for caching mapping information is limited and once the updated mapping information has been flushed from working memory to persistent storage, retaining the same mapping information indefinitely in working memory would unnecessarily consume cache capacity that could otherwise be used for other mapping tables or address information. Evicting the cached mapping information after it has been persistently recorded would therefore allow the available working memory to be reused for subsequent data-access and mapping operations and would improve cache utilization while permit the storage device to accommodate additional or more frequently needed mapping information without requiring an increase in the amount of working memory.
Response to Arguments
Claim Rejections Under 35 U.S.C. §103
Applicant’s arguments, see pages 11-16, filed September 14, 2026, with respect to the rejection(s) of claim(s) 1, 2, 5-9, and 12-18 under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Winterfeld (US 2023/0229340) in view of FUKUTOMI et al. (US 2013/0238838).
Applicant’s arguments are focused on the amendment of the limitation with regards to the verification operation and the specifically the requirement of matching of the physical address. The new reference Fukutomi discloses the matching of the physical address and furthermore shows similarity to the applicant’s invention as described in paragraphs [0096]-[0100] and corresponding Fig. 4.
With respect to the response of claims 3, 4, 10, and 11 they do not provide any further arguments and just refers to the features of claim 1 which is addressed above.
Conclusion
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/S.L./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
