DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-18 are pending. Claim 7 has been amended as per Applicants' request.
Papers Submitted
It is hereby acknowledged that the following papers have been received and placed of record in the file:
Amended Claims as filed on March 30, 2026
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5-9, and 12-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Winterfeld (US 2023/0229340) (hereinafter Winterfeld) (published July 20, 2023) in view of Sharma et al. (US 2021/0382652) (hereinafter Sharma) (published December 09, 2021).
Regarding Claims 1 and 13, taking claim 1 as exemplary, Winterfeld discloses a storage system comprising: a storage device including first and second memory blocks; and
“Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single-level cells (SLC) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLCs) can store multiple bits per cell” (Winterfeld [0027])
a controller configured to perform: a control operation of controlling, in response to a request, the storage device to program a requested data unit into the second memory block, the control operation including a programming operation and a movement operation, the programming operation being an operation of programming the requested data unit into the first memory block corresponding to a logical address included in the request and updating a mapping relationship between the logical address and a physical address indicating the first memory block, and the movement operation being an operation of moving the programmed data unit to the second memory block,
“Other memory sub-systems utilize the SLC as a cache to initially (e.g., prior to a coarse programming pass of the QLC) program the SLC with the data to be written to the QLC. Accordingly, the data is immediately readable from the SLC. Thereafter, the data may be moved from the SLC cache to other memory, such as QLC memory for longer-term storage (e.g., coarse and fine programming pass)… The L2P mapping table maintains, for a number of logical addresses, a one-to-one mapping to respective physical addresses (e.g., a physical location of the SLC and/or QLC). Accordingly, prior to coarse programming of the QLC, the L2P mapping table will include the physical address of the SLC cache storing the data to be written to the QLC” (Winterfeld [0015] programming to SLC/first memory block according to logical address in the L2p table, the move operation is from SLC to QLC/second memory block)
“Aspects of the present disclosure address the above and other deficiencies by maintaining a mapping of the SLC cache to the QLC (e.g., quad-to-single (Q2S) mapping table) while the data is undergoing copyback to facilitate the reading of the data from the SLC cache until fine programming of the QLC (e.g., copyback)” (Winterfeld [0016] mapping physical address of the blocks in the move from SLC to QLC)
a meta operation of recording the logical address and the physical address in a meta data unit corresponding to the requested data unit, and
“To read data from the SLC cache until the fine programming of the QLC, a logical-to-physical (L2P) mapping data structure (e.g., L2P mapping table) is maintained. The L2P mapping table maintains, for a number of logical addresses, a one-to-one mapping to respective physical addresses (e.g., a physical location of the SLC and/or QLC). Accordingly, prior to coarse programming of the QLC, the L2P mapping table will include the physical address of the SLC cache storing the data to be written to the QLC. Once the QLC is finely programmed, the L2P mapping table is updated to replace the physical address of the SLC cache with the physical address of the QLC” (Winterfeld [0015] addresses of the L2P mapping is updated)
But does not explicitly state a verification operation of verifying integrity of the mapping relationship for the moved data unit based on the physical address included in the meta data unit corresponding to the moved data unit and the physical address included in the mapping relationship.
Winterfeld and Sharma discloses a verification operation of verifying integrity of the mapping relationship for the moved data unit based on the physical address included in the meta data unit corresponding to the moved data unit and the physical address included in the mapping relationship.
“Once the QLC is finely programmed, the L2P mapping table is updated to replace the physical address of the SLC cache with the physical address of the QLC. In some instances, the L2P mapping table stores both the physical address of the SLC and the physical address of the QLC until the QLC is finely programmed, and then the physical address of the SLC is removed” (Winterfeld [0015])
“Similarly in header verification, after programming data 119 in SLCs, the controller 123 may fold the data from the SLCs to MLCs along with header data that is read/verified after folding for use in subsequent updating of the L2P mapping table 120, 205” (Sharma [0064] after folding data from SLCs the header data/mapping information would be verified and used to update the L2P table)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the verification after programming and folding in Sharma with the system in Winterfeld. The motivation for doing so would be improve data integrity by making sure the data is the same and stored without errors at the correct location.
Regarding Claims 2 and 14, Winterfeld further discloses wherein the first memory block is a single-level cell (SLC) block and the second memory block is a quadruple-level cell (QLC) block.
“Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single-level cells (SLC) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLCs) can store multiple bits per cell” (Winterfeld [0027])
Regarding Claim 5, Winterfeld further discloses wherein the physical address included in the mapping relationship in the programming operation includes source offset information representing offset information of the programmed data unit in the first memory block.
“To read data from the SLC cache until the fine programming of the QLC, a logical-to-physical (L2P) mapping data structure (e.g., L2P mapping table) is maintained. The L2P mapping table maintains, for a number of logical addresses, a one-to-one mapping to respective physical addresses (e.g., a physical location of the SLC and/or QLC). Accordingly, prior to coarse programming of the QLC, the L2P mapping table will include the physical address of the SLC cache storing the data to be written to the QLC” (Winterfeld [0015])
“the table management component 113 may traverse the linked list associated with the entry of the Q2S corresponding to the physical address of the QLC to determine which physical address of the SLCs associated with the QLC to return to the host system 120. To determine which physical address of the SLCs associated with the QLC to return to the host system 120, the table management component 113 identifies a page number of the physical address of the QLC and, based on the page number of the physical address of the QLC determines which physical address of the SLCs to return to the host system 120” (Winterfeld [0042])
“Accordingly, based on the page number of the physical address of the QLC (e.g., 825), the table management component 113 can determine that the physical address of the second SLC in the linked list should be returned to the host system 120 instead of the physical address of the QLC since the QLC is not programmed” (Winterfeld [0043] the page number is the offset information that indicates where the data of SLC block is to be stored on the QLC block)
Regarding Claim 6, Winterfeld further discloses wherein the controller performs the movement operation according to a blind data copy scheme of sequentially moving a plurality of data units from a single first memory block to the second memory block.
“Aspects of the present disclosure address the above and other deficiencies by maintaining a mapping of the SLC cache to the QLC (e.g., quad-to-single (Q2S) mapping table) while the data is undergoing copyback to facilitate the reading of the data from the SLC cache until fine programming of the QLC (e.g., copyback)” (Winterfeld [0016] copyback is a type of blind data copy)
Regarding Claim 7, Winterfeld further discloses wherein the controller performs the movement operation on each of the plurality of data units so that target offset information representing offset information of the moved data unit in the second memory block and the source offset information corresponding to the moved data unit have a relationship of an equation below:
[Equation]
Osource=Otarget mod Nsource_offsets, where
“Osource” represents the source offset information, “Otarget” represents the target offset information and “Nsource_offsets” represents a number of offsets allowable or allowed in the first memory block.
“For example, each SLC contains a page number between 0-699 (e.g., 700 pages), and each QLC contains a page number between 0-2799 (e.g., 2800 pages). Thus, since each programmed SLC is sequentially appended to the linked list, a first SLC of the SLCs having a page number between 0-699 corresponds to a first portion of the QLC having a page number between 0-699, a second SLC of the SLCs having a page number between 0-699 corresponds to a second portion of the QLC having a page number between 700-1399, a third SLC of the SLCs having a page number between 0-699 corresponds to a third portion of the QLC having a page number between 1400-2099, and a fourth SLC of the SLCs having a page number between 0-699 corresponds to a fourth portion of the QLC having a page number between 2100-2799. Accordingly, based on the page number of the physical address of the QLC (e.g., 825), the table management component 113 can determine that the physical address of the second SLC in the linked list should be returned to the host system 120 instead of the physical address of the QLC since the QLC is not programmed” (Winterfeld [0043] the Osource is the page number of the SLC and Otarget is the page number of the QLC and the Nsource_offset is 700)
Regarding Claim 8, Winterfeld and Sharma further discloses wherein the verification operation includes an acquisition operation of acquiring, based on the equation and from the target offset information, the source offset information corresponding to the moved data unit.
“Accordingly, based on the page number of the physical address of the QLC (e.g., 825), the table management component 113 can determine that the physical address of the second SLC in the linked list should be returned to the host system 120 instead of the physical address of the QLC since the QLC is not programmed” (Winterfeld [0043])
“For instance, in EPWR, after each program operation, the controller 123 may sense the data 119 that is programmed to verify whether programming is successful. Similarly in header verification, after programming data 119 in SLCs, the controller 123 may fold the data from the SLCs to MLCs along with header data that is read/verified after folding for use in subsequent updating of the L2P mapping table 120, 205” (Sharma [0064] based on the page number data is read from the blocks to verified if the programming is successful)
Regarding Claim 9, Winterfeld and Sharma further discloses wherein the controller performs the verification operation based on whether the physical address included in the mapping relationship matches a combination of the physical address included in the meta data unit and the source offset information acquired in the acquisition operation.
“Accordingly, based on the page number of the physical address of the QLC (e.g., 825), the table management component 113 can determine that the physical address of the second SLC in the linked list should be returned to the host system 120 instead of the physical address of the QLC since the QLC is not programmed” (Winterfeld [0043] the physical address of the SLC is a combination of the QLC physical address and page number to identify the mapping)
“For instance, in EPWR, after each program operation, the controller 123 may sense the data 119 that is programmed to verify whether programming is successful. Similarly in header verification, after programming data 119 in SLCs, the controller 123 may fold the data from the SLCs to MLCs along with header data that is read/verified after folding for use in subsequent updating of the L2P mapping table 120, 205” (Sharma [0064] based on the page number data is read from the blocks to verified if the programming is successful)
Regarding Claim 12, Winterfeld and Sharma further discloses wherein the controller is further configured to perform, between the meta operation and the verification operation, a repetition operation of repeating the control operation and the meta operation with respect to each of a plurality of requested data units, and wherein the controller performs the repetition operation on a predetermined number or rows included in the second memory block and subsequently performs the verification operation when the controller reads the data unit moved to the second memory block and determines that the read data unit to include no error.
“Certain memory sub-systems implementing QLC memory use a standard 16-16 coarse-fine, two-pass programming algorithm. Since a QLC memory cell stores four bits of data, there are 16 possible programming levels (i.e., 2.sup.4) representing the possible values of those four bits of data. Programming a wordline begins by coarsely programming all 16 levels in a first pass. The objective, of this “coarse,” first pass is to program all cells rapidly to slightly below their final target programming levels. During the slower, “fine,” second pass, the memory cells are programmed to a slightly higher final target programmed voltage. Such two-pass programming minimizes cell to cell (C2C) interference, as every cell and its neighbors are nearly at their final target programmed voltage when the fine programming pass is performed, and need only be “touched-up.” The combination of not requiring precision programming in the first pass, and the minimized C2C coupling, leads to fast programming with high read window budget (RWB). Such standard 16-16 coarse-fine programming, however, requires all data to be first written to single-level cell (SLC) memory (i.e., memory cells storing one bit of data per cell) before the first pass to protect against asynchronous power loss (APL)” (Winterfeld [0013] the second pass is the repetition operation)
“Accordingly, prior to coarse programming of the QLC, the L2P mapping table will include the physical address of the SLC cache storing the data to be written to the QLC. Once the QLC is finely programmed, the L2P mapping table is updated to replace the physical address of the SLC cache with the physical address of the QLC” (Winterfeld [0015])
“For instance, in EPWR, after each program operation, the controller 123 may sense the data 119 that is programmed to verify whether programming is successful. Similarly in header verification, after programming data 119 in SLCs, the controller 123 may fold the data from the SLCs to MLCs along with header data that is read/verified after folding for use in subsequent updating of the L2P mapping table 120, 205” (Sharma [0064] based on the page number data is read from the blocks to verified if the programming/folding is successful and that the L2P mappings are correct)
Regarding Claim 15, Winterfeld and Sharma further discloses wherein the physical address included in the mapping relationship in the programming operation includes a block address of the first memory block and source offset information representing offset information of the programmed data unit in the first memory block.
“To read data from the SLC cache until the fine programming of the QLC, a logical-to-physical (L2P) mapping data structure (e.g., L2P mapping table) is maintained. The L2P mapping table maintains, for a number of logical addresses, a one-to-one mapping to respective physical addresses (e.g., a physical location of the SLC and/or QLC). Accordingly, prior to coarse programming of the QLC, the L2P mapping table will include the physical address of the SLC cache storing the data to be written to the QLC” (Winterfeld [0015])
“the table management component 113 may traverse the linked list associated with the entry of the Q2S corresponding to the physical address of the QLC to determine which physical address of the SLCs associated with the QLC to return to the host system 120. To determine which physical address of the SLCs associated with the QLC to return to the host system 120, the table management component 113 identifies a page number of the physical address of the QLC and, based on the page number of the physical address of the QLC determines which physical address of the SLCs to return to the host system 120” (Winterfeld [0042])
“Accordingly, based on the page number of the physical address of the QLC (e.g., 825), the table management component 113 can determine that the physical address of the second SLC in the linked list should be returned to the host system 120 instead of the physical address of the QLC since the QLC is not programmed” (Winterfeld [0043] the page number is the offset information that indicates where the data of SLC block is to be stored on the QLC block)
Regarding Claim 16, Winterfeld further discloses wherein the movement operation is performed on each of a plurality of data units so that target offset information representing offset information of the moved data unit in the second memory block is identical to the source offset information corresponding to the moved data unit.
“the table management component 113 may traverse the linked list associated with the entry of the Q2S corresponding to the physical address of the QLC to determine which physical address of the SLCs associated with the QLC to return to the host system 120. To determine which physical address of the SLCs associated with the QLC to return to the host system 120, the table management component 113 identifies a page number of the physical address of the QLC and, based on the page number of the physical address of the QLC determines which physical address of the SLCs to return to the host system 120” (Winterfeld [0042])
“Accordingly, based on the page number of the physical address of the QLC (e.g., 825), the table management component 113 can determine that the physical address of the second SLC in the linked list should be returned to the host system 120 instead of the physical address of the QLC since the QLC is not programmed” (Winterfeld [0043] the page number is the offset information that indicates where the data of SLC block is to be stored on the QLC block)
Regarding Claim 17, Winterfeld and Sharma further discloses wherein the verification operation includes an acquisition operation of acquiring, from the target offset information, the source offset information corresponding to the moved data unit.
“Accordingly, based on the page number of the physical address of the QLC (e.g., 825), the table management component 113 can determine that the physical address of the second SLC in the linked list should be returned to the host system 120 instead of the physical address of the QLC since the QLC is not programmed” (Winterfeld [0043])
“For instance, in EPWR, after each program operation, the controller 123 may sense the data 119 that is programmed to verify whether programming is successful. Similarly in header verification, after programming data 119 in SLCs, the controller 123 may fold the data from the SLCs to MLCs along with header data that is read/verified after folding for use in subsequent updating of the L2P mapping table 120, 205” (Sharma [0064] based on the page number data is read from the blocks to verified if the programming is successful)
Regarding Claim 18, Winterfeld and Sharma further discloses wherein the verification operation is performed based on whether the physical address included in the mapping relationship matches a combination of the physical address included in the meta data unit and the source offset information acquired in the acquisition operation.
“Accordingly, based on the page number of the physical address of the QLC (e.g., 825), the table management component 113 can determine that the physical address of the second SLC in the linked list should be returned to the host system 120 instead of the physical address of the QLC since the QLC is not programmed” (Winterfeld [0043] the physical address of the SLC is a combination of the QLC physical address and page number to identify the mapping)
“For instance, in EPWR, after each program operation, the controller 123 may sense the data 119 that is programmed to verify whether programming is successful. Similarly in header verification, after programming data 119 in SLCs, the controller 123 may fold the data from the SLCs to MLCs along with header data that is read/verified after folding for use in subsequent updating of the L2P mapping table 120, 205” (Sharma [0064] based on the page number data is read from the blocks to verified if the programming is successful)
Claims 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Winterfeld (published July 20, 2023) and Sharma (published December 09, 2021) as applied to claim 2 above, and further in view of Inbar et al. (US 2016/0124668) (hereinafter Inbar) (published May 05, 2016).
Regarding Claim 3, the combination of Winterfeld and Sharma disclosed the system of claim 2 but does not explicitly state wherein the controller performs the movement operation according to a valid data copy scheme of moving a single data unit from a single first memory block to the second memory block.
Inbar discloses wherein the controller performs the movement operation according to a valid data copy scheme of moving a single data unit from a single first memory block to the second memory block.
“Before moving or copying the data from one or more source SLC blocks 148 to a destination MLC block 150, a scan of an address data structure that tracks addressing of the data may be performed to identify which of the data in the source SLC blocks 148 is valid and which is invalid. The determination may be made on a unit basis. That is, each data unit in the source SLC blocks 148 may be identified as either valid or invalid. Subsequently, a source-to-destination mapping (otherwise referred to as a folding vector) may be generated that identifies where each of the data units are to be stored in the destination MLC block 150” (Inbar [0071])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to substitute the copyback of data in the combination of Winterfeld and Sharma with the valid data copy scheme of Inbar to yield the predictable results of only copying valid data. The motivation for doing so would be to reduce write amplification and the amount of data needed to be folded.
Regarding Claim 4, Winterfeld and Sharma further discloses wherein the controller performs the verification operation based on whether the physical address included in the meta data unit matches the physical address included in the mapping relationship.
“Once the QLC is finely programmed, the L2P mapping table is updated to replace the physical address of the SLC cache with the physical address of the QLC. In some instances, the L2P mapping table stores both the physical address of the SLC and the physical address of the QLC until the QLC is finely programmed, and then the physical address of the SLC is removed” (Winterfeld [0015])
“Once an entry of the Q2S corresponding to an index that matches the physical address of the QLC is identified, the table management component 113 determines whether the QLC is programmed based on the bit flag of the entry of the Q2S. If the bit flag is cleared or not set, indicating that the QLC is programmed, the table management component 113 returns the physical address of the QLC to the host system 120 to perform the memory access operation” (Winterfeld [0042] based on the bit flag it is determined if the QLC is programed (data is moved) or not and thus verifies if the L2P mapping to a QLC block address is valid)
“Similarly in header verification, after programming data 119 in SLCs, the controller 123 may fold the data from the SLCs to MLCs along with header data that is read/verified after folding for use in subsequent updating of the L2P mapping table 120, 205” (Sharma [0064])
Claim 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Winterfeld (published July 20, 2023) and Sharma (published December 09, 2021) as applied to claim 1 above, and further in view of Yun et al. (US 2014/0059275) (hereinafter Yun) (published February 27, 2014).
Regarding Claim 10, the combination of Winterfeld and Sharma disclosed the system of claim 1 but does not explicitly state wherein the storage device further includes a working memory, and wherein the meta operation includes: a temporary storage operation of temporarily storing the logical address and the physical address in the working memory; and a recording operation of recording the temporarily stored logical address and physical address into a metadata unit corresponding to the requested data unit.
Yun discloses wherein the storage device further includes a working memory, and
“The RAM 1220 may be a working memory of the memory controller 1200” (Yun [0049])
wherein the meta operation includes: a temporary storage operation of temporarily storing the logical address and the physical address in the working memory; and
“The RAM 1220 may include a mapping table 1221. The mapping table 1221 may include information for a translation operation of the FTL. The mapping table 1221 may include information on mapping relationship between a logical address of a file organized by a file system described in FIG. 2 and a physical address of the flash memory 1300. In some embodiments, in the case that a free memory block is assigned as a write memory block, the memory controller 1200 may update the mapping table 1221” (Yun [0049])
a recording operation of recording the temporarily stored logical address and physical address into a metadata unit corresponding to the requested data unit.
“the mapping table 1221 in the RAM 1220 needs to be flushed to the main mapping table 1321 in the flash memory 1300 whenever the mapping table 1221 is updated, so that the mapping table 1221 can be recovered from the main mapping table 1321” (Yun [0054])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the working memory and cached mapping table of Yun with the system in the combination of Winterfeld and Sharma. The motivation for doing so would be to improve efficiency by providing quicker address translation to request so the memory may be accessed quicker.
Claim 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Winterfeld (published July 20, 2023), Sharma (published December 09, 2021), and Yun (published February 27, 2014) as applied to claim 10 above, and further in view of Rogers et al. (US 2007/0300037) (hereinafter Rogers) (published December 27, 2007).
Regarding Claim 11, the combination of Winterfeld, Sharma, and Yun disclosed the system of claim 10 but does not explicitly state wherein the meta operation further includes a deletion operation of deleting, after the recording operation, the temporarily stored logical address and physical address from the working memory.
Yun and Rogers discloses wherein the meta operation further includes a deletion operation of deleting, after the recording operation, the temporarily stored logical address and physical address from the working memory.
“the mapping table 1221 in the RAM 1220 needs to be flushed to the main mapping table 1321 in the flash memory 1300 whenever the mapping table 1221 is updated, so that the mapping table 1221 can be recovered from the main mapping table 1321” (Yun [0054])
“Secondary mapping tables are cached to facilitate accessing the flash memory. In an example embodiment, a limited amount of working memory is allocated for storage of secondary mapping tables. When all of the cache slots are full and a new secondary table is to be loaded from flash memory, a secondary table is evicted to allow loading of another secondary mapping table” (Rogers [0022] the secondary mapping table with the logical address and physical address is deleted from working memory to make room for another secondary mapping table)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the evicting/deleting of the cached mapping table disclosed in Rogers with the system in the combination of Winterfeld, Sharma, and Yun. The motivation for doing so would be to efficiently manage the cached mapping tables with respect to the amount of resources available.
Response to Arguments
Applicant's arguments filed March 30, 2026 have been fully considered but they are not persuasive.
Applicant Argues:
a) Thus, even assuming, arguendo, that as the Office Action asserts it would have been
obvious to modify Winterfield in view of Sharma to combine the verification after programming and folding in Sharma with the system in Winterfeld to improve data integrity by making sure the data is the same and stored without errors at the correct location, the resulting combination would not disclose or suggest the features of claim 1. Verifying data integrity does not correspond to verifying mapping integrity. As set forth in MPEP 2141, "[t]he key to supporting any rejection under 35 U.S.C. 103 is the clear articulation of the reason(s) why the claimed invention would have been obvious." Here, the Office Action has not clearly articulated reasons for modifying Winterfield with the proposed header verification of Sharma to be utilized in Winterfield in the manner of claim 1, or how benefits of any such utility of the proposed modification in Winterfield outweigh the added redundancy and processing workload that would result from such proposed modification. Therefore, it is respectfully submitted that the Office Action fails to establish a prima facie case of obviousness.
With respect to (a), applicant's arguments are not persuasive because they are premised on an inaccurate characterization of Sharma. Applicant asserts that paragraph [0064] of Sharma merely describes verification of physical data, i.e., comparing programmed data against source data. However, paragraph [0064] expressly discloses verification operations beyond verification of user data contents. Specifically, Sharma teaches that sense operations may include "header verification" and reads of "control information/L2P" data. Sharma further discloses that, after data is folded from SLCs to MLCs, "header data" is read and verified for use in subsequent updating of the L2P mapping table. A person of ordinary skill in the art would have understood that such header data is associated with control information used to maintain logical-to-physical address mappings. In this regard, Sharma expressly explains that flash storage devices maintain control tables that include mappings of logical addresses to physical addresses and that such control tables are used to track the physical location of logical sectors or blocks in flash memory in paragraph [0003] of Sharma. Thus, Sharma directly associates control information with physical address information used for L2P mapping. Accordingly, Applicant's characterization that Sharma only verifies user data is inconsistent with Sharma's express teachings. Rather, Sharma discloses verification of header data and control information that is utilized in connection with updating and maintaining the L2P mapping table. Because the L2P mapping table stores logical-to-physical address relationships, verification of the associated header/control information necessarily pertains to the integrity and correctness of mapping-related information, including physical location information corresponding to stored data.
Applicant further argues that Sharma fails to disclose the claimed "verifying integrity of the mapping relationship for the moved data unit based on the physical address included in the meta data unit corresponding to the moved data unit and the physical address included in the mapping relationship." However, Sharma need not disclose the claim language verbatim. Sharma teaches verification of header data and control information associated with updating L2P mappings, where such mappings are expressly based on physical address information maintained in control tables. A person of ordinary skill in the art would have recognized that verification of header/control information used to update L2P mappings entails verifying the correctness of physical location information associated with moved or folded data relative to the mapping information maintained by the controller. Therefore, Applicant's argument improperly disregards Sharma's explicit disclosures regarding header verification, control information, physical-address-based L2P mappings, and verification performed in connection with updating the L2P mapping table.
Accordingly, Applicant's argument is unpersuasive because it overlooks Sharma's express disclosure that verified header and control information is used in connection with maintaining and updating L2P mappings, thereby evidencing verification directed to mapping-related information and not merely user data integrity.
With respect to the dependent claims 3, 4, 10, and 11, Applicant’s arguments do not identify any additional limitation alleged to distinguish the cited prior art, but instead incorporates the arguments presented for the independent claims. For reasons discussed above regarding the independent claims, those arguments are not persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.L./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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