DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to Application 18/946971 filed on November 14, 2024 in which Claims 1-15 are presented for examination.
Status of Claims
Claims 1-1 are pending, of which Claims 2, 3, 6, 7 and 11-13 are rejected under 112b. Claims 1, 10 and 15 are allowed. Claims 4, 5, 8, 9 and 14 are objected to.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 3, 6, 7 and 11-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the ECS command” in Lines 20, 21, 24, 28 and 29. There is insufficient antecedent basis for this limitation in the claim.
Claim 2 recites the limitation "the ECS operation cycle” in Lines 20, 21, 24, 28 and 29. There is insufficient antecedent basis for this limitation in the claim.
Claim 2 recites the limitation "the current ECS operation” in Lines 20, 21, 24, 28 and 29. There is insufficient antecedent basis for this limitation in the claim.
Claim 2 recites the limitation "the storage addresses” in Lines 20, 21, 24, 28 and 29. There is insufficient antecedent basis for this limitation in the claim.
Claim 3 recites the limitation "the ECS operation cycle” in Lines 20, 21, 24, 28 and 29. There is insufficient antecedent basis for this limitation in the claim.
Claim 6 recites the limitation "the refresh command” in Lines 20, 21, 24, 28 and 29. There is insufficient antecedent basis for this limitation in the claim.
Claim 7 recites the limitation "the refresh command” in Lines 20, 21, 24, 28 and 29. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the ECS command” in Lines 20, 21, 24, 28 and 29. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the ECS operation cycle” in Lines 20, 21, 24, 28 and 29. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the storage addresses” in Lines 20, 21, 24, 28 and 29. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the ECS operation cycle” in Lines 20, 21, 24, 28 and 29. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the refresh command” in Lines 20, 21, 24, 28 and 29. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites the limitation "the refresh command” in Lines 20, 21, 24, 28 and 29. There is insufficient antecedent basis for this limitation in the claim.
Allowable Subject Matter
Claims 4, 5, 8, 9 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Allowable Subject Matter
Claims 1, 10 and 15 are allowable in light of the Applicant's argument and in light of the prior art made of record.
Reasons for Indicating Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter: Upon searching a variety of databases, the examiner considers “the memory controller being connected to the memory chip, and being configured to: receive the ECS finish flag signal, generate an ECS start flag signal based on the ECS finish flag signal, and send the ECS start flag signal to the memory chip, so that the memory chip enters a new ECS operation cycle based on the ECS start flag signal”, in Claim 1 and “the control circuit being configured to: generate an ECS finish flag signal and send the ECS finish flag signal to an outside after a current ECS operation cycle is completed; and receive an ECS start flag signal from the outside, and enter a new ECS operation cycle based on the ECS start flag signal”, in Claims 10 and 15; in conjunction with all other limitations of the dependent and independent claims are not taught or suggested by the prior art of record (PTO-892). Therefore, claims 1, 10 and 15 are hereby allowed.
Prior Art Made of Record
From a search of the prior art, one reference was found and considered by the Examiner to be the most-related prior art with regards to the claimed invention of the instant application:
Chao et al. (U.S. Patent Application Publication No. 2019/0340063 A1), hereinafter “Chao”. Chao is cited on PTO-892 filed 4/29/2026.
Chao: Paragraph 31 teaches the operating system may need to know whether the full memory scrubbing operation is completed or not. In order for the operating system to determine whether the full memory scrubbing operation is completed, the operating system may wait to receive a persistent memory device root device notification, which is provided by the BIOS to the operating system when either an uncorrectable error is detected during the full memory scrubbing operation, or the full memory scrubbing operation has completed. When the operating system receives the persistent memory device root device notification, then the operating system may issue a start command to start the full memory scrubbing operation. That start command may either start the full memory scrubbing operation if the full memory scrubbing operation is not in progress, or may cause the BIOS to return a notification that the full memory scrubbing operation is already in progress if the full memory scrubbing operation is running in the background during the runtime environment. If the full memory scrubbing operation can be started, the operating system sets a full memory scrubbing operation completion flag. The operating system can call start the full memory scrubbing operation with a full memory scrubbing operation completion flag bit set. When the flag bit is set, the operating system just wants to read the memory scrub error list, instead of starting new memory scrubbing operation. However, if the operating system really wants to start a new memory scrubbing operation, the operating system can may issue a start command to start the full memory scrubbing operation without the flag bit set.
Although conceptually similar to the claimed invention of the instant application, Chao does not teach the memory controller being connected to the memory chip, and being configured to: receive the ECS finish flag signal, generate an ECS start flag signal based on the ECS finish flag signal, and send the ECS start flag signal to the memory chip, so that the memory chip enters a new ECS operation cycle based on the ECS start flag signal or the control circuit being configured to: generate an ECS finish flag signal and send the ECS finish flag signal to an outside after a current ECS operation cycle is completed; and receive an ECS start flag signal from the outside, and enter a new ECS operation cycle based on the ECS start flag signal.
Additional Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure:
Campbell et al. (U.S. Patent Application 2014/0229766); teaches the reset address flag determines the behaviour of the scrubbing handler when the scrubbing operation is resumed after having been interrupted, in particular whether, when the scrubbing operation starts again, it issues scrubbing access requests to the next memory address after the point at which it was interrupted, or whether it must begin again from the first memory address within the application region.
Ayyapureddi et al. (U.S. Patent Application 2023/0315568); teaches once the controller has performed the scrub operation on each of the rows (e.g., and stored the quantity of errors detected in each of the rows), the controller may additionally store the quantity of errors detected in the memory array during the scrub operation (e.g., based on the quantity indicated by the counter). Then, the controller may reset the counter. Thus, when the controller initiates another scrub operation at the memory array, the counter may be initialized to indicate no errors detected in the memory array.
Yang et al. (U.S. Patent Application 2011/0289386); teaches the external circuitry can further activate a scrub signal that commands the scrub machine to eliminate errors from the memory array and the ECC array regardless of the level of error in the memory array and the ECC array. The scrub signal may indicate a complete scrubbing of errors in the memory array and the ECC array or have an encoded address range that indicate a portion of the memory array and the ECC array to be scrubbed of errors. The scrub machine will then generate an address for the initial location to be scrubbed. The read signal is activated and the data from the location is extracted from the memory array and the ECC array.
Kim et al. (U.S. Patent Application 2018/0018219); teaches the latch circuit may generate a pre-scrub signal PSCR which is enabled in response to the flag signal EFLAG and which is disabled in response to the internal reset signal IR or an external reset signal RST. The latch circuit may generate the pre-scrub signal PSCR which is enabled to have a logic “high” level if the flag signal EFLAG having a logic “high” level is inputted. The latch circuit may generate the pre-scrub signal PSCR which is disabled to have a logic “low” level if the internal reset signal IR having a logic “low” level or the external reset signal RST having a logic “low” level is inputted. The external reset signal RST may be provided from an external device to initialize the latch circuit.
Cochran et al. (U.S. Patent Application 2006/0129899); teaches the active monitoring function would typically operate in the following manner. With N ranks of memory, the monitoring/scrubbing process would march through memory starting with rank 0 and ending with rank N-1, proceeding through each memory address in each rank. When completed, the process would begin all over again. When the monitor function is enabled, typically the write back to memory after each scrub command would be enabled by default (as opposed to conventional scrub operations which typically write back corrected data when incorrect data is read during the operation).
Reed et al. (U.S. Patent Application 2017/0161143); teaches the operation of a DRAM that can perform an ECC scrub during a refresh cycle as initiated by the memory controller in accordance with an embodiment of the present invention. In one embodiment, the DRAM can perform an ECC scrub of the memory array during a regular refresh cycle. Similar to the self-refresh embodiment discussed above, the ECC scrub is performed for each column and is repeated for all the columns across all pages to correct for bit errors. In other words, the controller periodically instructs the DRAM to perform a refresh cycle and during that cycle the DRAM performs a scrub operation. As subsequent refresh cycles are executed as is required by the standard DRAM operation, the internal counters perform a scrub across all the rows in all banks. Then, subsequently, the DRAM advances the column counter by one word (or multiple words) and performs the same action for the next column (or set of columns) and keeps repeating this process until the entire memory is updated for all banks, rows and columns. Like the self-refresh embodiment, DRAM can implement a column counter internally.
Kim et al. (U.S. Patent Application 2023/0012525); teaches the memory device may perform a data scrubbing operation. The data scrubbing operation of the memory device may include reading of the data of the memory cell array, and writing-back of the data, in which an error detected from the read data is corrected, to the memory cell array. In example embodiments, the data scrubbing operation of the memory device may be instructed by an external command such as a multi-purpose command from the memory controller. In example embodiments, the data scrubbing operation of the memory device may be performed at regular cycles in an automatic mode, without a command from the memory controller.
Conclusion
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/SARAI E BUTLER/Primary Examiner, Art Unit 2114
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