DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feeley (US 2010/0177564) in view of Lee (US 2024/0361954).
Regarding claim(s) 1, 8 and 16, Feeley teaches:
A storage device comprising: a memory controller configured to generate at least one of a chip enable signal and a command/address signal; a buffer chip configured to receive the chip enable signal, the command/address signal, and a data signal from the memory controller; Fig. 2 and [0027] a data bus 32, address bus 34, command bus 36, and various discrete lines representing a NAND flash interface 38 coupled to the control logic 40. [0030] To access the memory array 46, an address register 48 may receive memory address signals using the address bus 34. A row decoder 50 may receive and decode row addresses from address values received by the address register 48. [0031] The NAND flash memory device 30 may also include a column decoder 52 for receiving and decoding column address signals provided to the address register 48. [0032] A command register 56 may store incoming commands received on the command bus 36 which are then executed by the control logic 40, which includes the above-discussed read/write logic 44. As will be appreciated, the execution of commands received on the command bus 36 may be based upon the state of the control signals 38 provided by the processor 12.
and a memory device including at least one storage area, the at least one storage area configured to perform at least one of a write operation and a read operation, based on the command/address signal and the data signal received by the buffer chip, Fig. 2 and [0032] Program and read operations to the memory array 46 may be determined based on commands received on the command bus 36. A command register 56 may store incoming commands received on the command bus 36 which are then executed by the control logic 40, which includes the above-discussed read/write logic 44. As will be appreciated, the execution of commands received on the command bus 36 may be based upon the state of the control signals 38 provided by the processor 12.
wherein the buffer chip […] comprises a first channel configured to receive the chip enable signal or the command/address signal, and a second channel configured to receive the data signal, [0030] To access the memory array 46, an address register 48 may receive memory address signals using the address bus 34. A row decoder 50 may receive and decode row addresses from address values received by the address register 48. [0032] A command register 56 may store incoming commands received on the command bus 36 which are then executed by the control logic 40. [0034] The data I/O circuitry 60 may also include one or more buffers for delaying, regenerating, and storing data signals communicated between the processor 12 and the NAND flash memory device 30.
wherein the first channel and the second channel are configured to transmit signals received through separate paths to respective ones of the at least one storage area. Fig. 2 and [0027] a data bus 32, address bus 34, command bus 36, and various discrete lines representing a NAND flash interface 38 coupled to the control logic 40. [0030] To access the memory array 46, an address register 48 may receive memory address signals using the address bus 34. A row decoder 50 may receive and decode row addresses from address values received by the address register 48. [0034] The data I/O circuitry 60 may also include various caches 62 and registers 64 which may serve as page buffers for reading data from and writing data to the memory array 46.
Feeley does not explicitly teach, but Lee teaches wherein the buffer chip is physically distinct from the memory controller and the memory device and the buffer chip Fig. 2 and [0036] The buffer chip 220 may be disposed on the package substrate 210. The buffer chip 220 may communicate with the memory interface 115 (FIG. 1) through the package balls 211 of the package substrate 210. The buffer chip 220 may further communicate with the memory chips 231 to 234 through the bonding pads 213 of the package substrate 210.
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention to combine the memory system of Feeley with the memory system structure taught by Lee. The motivation for doing so would have been to reduce loading between memory package and memory interface to enable high-speed operation. This is taught by Lee in [0038].
Regarding claim(s) 2, 9, 10 and 17, Feeley teaches:
wherein the buffer chip further comprises a decoder for decoding the command/address signal, and wherein the buffer chip is configured to determine a first storage area with which the first channel communicates based on a result of decoding the command/address signal. [0030] To access the memory array 46, an address register 48 may receive memory address signals using the address bus 34. A row decoder 50 may receive and decode row addresses from address values received by the address register 48. The row decoder 50 typically includes a word line driver, an address decoder tree, and circuitry which translates a given row address received on the address bus 34 and selectively activates an appropriate word line or word lines by way of the word line drivers. [0031] The NAND flash memory device 30 may also include a column decoder 52 for receiving and decoding column address signals provided to the address register 48. In some implementations, the column decoder 52 may also determine when a column within the memory array 46 is defective, as well as the address of a replacement column. The column decoder 52 is coupled to sense amplifiers 54, each of which may be coupled to complementary pairs of bit lines of the memory array 46.
Regarding claim(s) 3, 11 and 18, Feeley teaches:
wherein the buffer chip is configured to determine a second storage area with which the second channel communicates based on a result of decoding the command/address signal. [0031] The NAND flash memory device 30 may also include a column decoder 52 for receiving and decoding column address signals provided to the address register 48. In some implementations, the column decoder 52 may also determine when a column within the memory array 46 is defective, as well as the address of a replacement column. The column decoder 52 is coupled to sense amplifiers 54, each of which may be coupled to complementary pairs of bit lines of the memory array 46. [0034] The sense amplifiers 54 receive the data from the data I/O circuitry 60 and store the data to corresponding cells or pages in the memory array 46. Fig. 4B and [0041] During the programming operation, the memory cells corresponding to the data values in the data pattern having a binary value of 0 have changed state. In the illustrated example, the successfully programmed page 74 may include 32 occurrences of a binary value of 0 in the page and 32 occurrences of a binary value of 1 in the page.
Regarding claim(s) 4, 12 and 19, Feeley teaches:
wherein the buffer chip is configured to communicate the data signal with a second storage area through the second channel [0034] during a write operation, the data bus 32 provides data to the data I/O circuitry 60. The sense amplifiers 54 receive the data from the data I/O circuitry 60 and store the data to corresponding cells or pages in the memory array 46. In some embodiments, the data bus 32 may include an 8-bit or 16-bit data bus. The data I/O circuitry 60 may also include various caches 62 and registers 64 which may serve as page buffers for reading data from and writing data to the memory array 46.
while the command/address signal is transmitted to a first storage area through the first channel. [0030] To access the memory array 46, an address register 48 may receive memory address signals using the address bus 34. A row decoder 50 may receive and decode row addresses from address values received by the address register 48.
Regarding claim(s) 5, 13 and 20, Feeley teaches:
wherein the memory device comprises a plurality of chips, and wherein the buffer chip is configured to independently exchange signals with each of the plurality of chips. [0027] the aforementioned inputs are represented separately in the present figure by a data bus 32, address bus 34, command bus 36, and various discrete lines representing a NAND flash interface 38 coupled to the control logic 40. [0047] a separate error correction algorithm may be executed by the ECC logic 42 to perform error correction on the expected count value data independently of the program data.
Regarding claim(s) 6 and 14, Feeley teaches:
wherein the first channel comprises a first switch configured to control transmission of the command/address signal and a second switch configured to control transmission of the data signal, and wherein the second channel comprises a third switch configured to control transmission of the command/address signal and a fourth switch configured to control transmission of the data signal. Fig. 2 and [0028] The processor 12 may provide a number of control signals to the NAND flash memory device 30 using the NAND flash interface 38. In the illustrated embodiment, the control signals may include the following input signals: a chip enable signal (CE#), a command latch enable signal (CLE), an address latch enable signal (ALE), a write enable signal (WE#), a read enable signal (RE#), and a write-protect signal (WP#).
Regarding claim(s) 7 and 15, Feeley teaches:
wherein the first channel is configured to transmit the command/address signal to a plurality of dies included in the memory device. Fig. 2 and [0027] a data bus 32, address bus 34, command bus 36, and various discrete lines representing a NAND flash interface 38 coupled to the control logic 40. [0030] To access the memory array 46, an address register 48 may receive memory address signals using the address bus 34. A row decoder 50 may receive and decode row addresses from address values received by the address register 48. [0031] The NAND flash memory device 30 may also include a column decoder 52 for receiving and decoding column address signals provided to the address register 48. [0032] A command register 56 may store incoming commands received on the command bus 36 which are then executed by the control logic 40, which includes the above-discussed read/write logic 44. As will be appreciated, the execution of commands received on the command bus 36 may be based upon the state of the control signals 38 provided by the processor 12.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES J CHOI whose telephone number is (571)270-0605. The examiner can normally be reached MON-FRI: 9AM-5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ROCIO DEL MAR PEREZ-VELEZ can be reached at 571-270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHARLES J CHOI/Primary Examiner, Art Unit 2133
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