DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office action is in response to the Preliminary Amendment dated 4/16/2025.
Claims 1 and 20 are amended.
Claims 1-20 are pending.
Claims 1-20 are rejected.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 1 recites “…where the control circuitry is configured to control writing of a group of data units for which the memory addresses associated with those data units have a predetermined relationship and for which a given set of cache storage data units are applicable to those memory addresses, to the same storage sector of the at least two storage sectors” (independent claim 1, lines 18-21). The Examiner is uncertain if “those data units” refer to “a group of data units” and if “those memory addresses” refer to “the memory addresses associated with those data units.” For the sake of examination, the Examiner has interpreted “…where the control circuitry is configured to control writing of a group of data units for which the memory addresses associated with those data units have a predetermined relationship and for which a given set of cache storage data units are applicable to those memory addresses, to the same storage sector of the at least two storage sectors” to read “…where the control circuitry is configured to control writing of a group of data units for which memory addresses associated with the group of data units have a predetermined relationship and for which a given set of cache storage data units are applicable to the memory addresses associated with the group of data units, to the same storage sector of the at least two storage sectors.” Dependent claims 1-19, which ultimately depend from independent claim 1, are rejected for carrying the same deficiencies.
Claims 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 20 recites “…where the controlling step comprises controlling writing of a group of data units for which the memory addresses associated with those data units have a predetermined relationship and for which a given set of cache storage data units are applicable to those memory addresses, to the same storage sector of the at least storage sectors” (independent claim 20, lines 16-19). The Examiner is uncertain if “those data units” refer to “a group of data units” and if “those memory addresses” refer to “the memory addresses associated with those data units.” For the sake of examination, the Examiner has interpreted “…where the controlling step comprises controlling writing of a group of data units for which the memory addresses associated with those data units have a predetermined relationship and for which a given set of cache storage data units are applicable to those memory addresses, to the same storage sector of the at least storage sectors” to read “…where the controlling step comprises controlling writing of a group of data units for which the memory addresses associated with the group of data units have a predetermined relationship and for which a given set of cache storage data units are applicable to the memory addresses associated with the group of data units, to the same storage sector of the at least two storage sectors.”
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1 and 20 of the instant application are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 20 of U.S. Patent No. 12,174,738 (“Tune”). The following tables, in which similarities between independent claims 1 and 20 of the instant application and independent claims 1 and 20 of Tune are highlighted in bold, and accompanying reasoning illustrate that independent claims 1 and 20 of the instant application are not patentably distinct from independent claims 1 and 20 of Tune:
Instant Application, Independent Claim 1
Tune, Independent Claim 1
1. Circuitry, comprising: control circuitry to control access to cache storage in an array of random access memory storage elements of a random access memory, the cache storage being configured to store data as cache storage data units, the random access memory comprising m cache storage data units, the random access memory being configured so that following access to a given cache storage data unit within a given storage sector of the multiple storage sectors, when a next access is to another cache storage data unit within the given storage sector, an energy requirement or latency for that next access is lower than the energy requirement of latency when that next access is instead to a cache storage data unit within a storage sector of the multiple storage sectors, that is different from the given storage sector; the control circuitry being configured to control the storage of a data unit having an associated memory address to a cache storage data unit selected from a set of n cache storage data units applicable to that memory address, where n is equal to an integer multiple of at least two times m, and the set of n cache storage data units comprises at least two storage sectors of the multiple storage sectors; where the control circuitry is configured to control writing of a group of data units for which the memory addresses associated with those data units have a predetermined relationship and for which a given set of cache storage data units are applicable to those memory addresses, to the same storage sector of the at least two storage sectors.
1. Circuitry, comprising: control circuitry configured to control access to cache storage in an array of random access memory storage elements of a static random access memory, the cache storage being configured to store data as cache storage data units, the static random access memory comprising multiple storage sectors, where each storage sector of the multiple storage sectors comprises m cache storage data units, where m is an integer greater than 1, the static random access memory being configured so that following access to a given cache storage data unit within a given storage sector of the multiple storage sectors, when a next access is to another cache storage data unit within the given storage sector, an energy requirement or latency for that next access is lower than the energy requirement or latency when that next access is instead to a cache storage data unit within a storage sector of the multiple storage sectors, that is different from the given storage sector; the control circuitry being configured to control storage of a data unit having an associated memory address to a cache storage data unit selected from a set of n cache storage data units applicable to that memory address, where n is equal to an integer multiple of at least two times m, and the set of n cache storage data units comprises at least two storage sectors of the multiple storage sectors; where the control circuitry is configured to control writing of a group of data units for which the memory addresses associated with those data units have a predetermined relationship and for which a given set of cache storage data units are applicable to those memory addresses, to the same storage sector of the at least two storage sectors.
Claim 1 of the instant application claims “a random access memory,” whereas claim 1 of Tune claims “a static random access memory.” The Examiner notes that “a static random access memory” is “a random access memory,” which means that independent claim 1 of Tune anticipates independent claim 1 of the instant application. Independent claim 1 of the instant application is thus not patentably distinct from independent claim 1 of Tune.
Instant Application, Independent Claim 20
Tune, Independent Claim 20
20. A method, comprising: storing cache data as cache data storage units by an array of random access memory storage elements of a random access memory, the random access memory comprises m cache storage data units, where m is an integer greater than 1, and configured so that following access to a given cache storage data unit within a given storage sector of the multiple storage sectors, when a next access is to another cache storage data unit within the given storage sector, an energy requirement or latency for that next access is lower than the energy requirements or latency when that nest access is instead to a cache storage data unit within a storage sector different to the given storage sectir; and controlling access to the cache storage, comprising controlling the storage of a data unit having an associated memory address to a cache storage data unit selected from a set of n cache storage data units applicable to that memory address, where n is equal to an integer multiple of at least two time m, and the set of n cache storage data units comprises at least two storage sectors of the multiple storage sectors; where the controlling step comprises controlling writing of a group of data units for which the memory addresses associated with those data units have a predetermined relationship an for which a given set of cache storage data units are applicable to those memory addresses, to the same storage sector of the at least storage sectors.
20. A method, comprising: storing cache data as cache data storage units by an array of random access memory storage elements of a static random access memory, the static random access memory comprising multiple storage sectors, where each storage sector of the multiple storage sectors comprises m cache storage data units, where m is an integer greater than 1, and configured so that following access to a given cache storage data unit within a given storage sector of the multiple storage sectors, when a next access is to another cache storage data unit within the given storage sector, an energy requirement or latency for that next access is lower than the energy requirement or latency when that next access is instead to a cache storage data unit within a storage sector of the multiple storage sectors different from the given storage sector; and controlling access to the cache storage, comprising controlling storage of a data unit having an associated memory address to a cache storage data unit selected from a set of n cache storage data units applicable to that memory address, where n is equal to an integer multiple of at least two times m, and the set of n cache storage data units comprises at least two storage sectors multiple storage sectors of the multiple storage sectors; where the controlling step comprises controlling writing of a group of data units for which the memory addresses associated with those data units have a predetermined relationship and for which a given set of cache storage data units are applicable to those memory addresses, to the same storage sector of the given at least two storage sectors.
Claim 20 of the instant application claims “a random access memory,” whereas claim 20 of Tune claims “a static random access memory.” The Examiner notes that “a static random access memory” is “a random access memory,” which means that independent claim 20 of Tune anticipates independent claim 20 of the instant application. Independent claim 20 of the instant application is thus not patentably distinct from independent claim 20 of Tune.
Conclusion
The following prior art is made of record and is not relied upon for any rejection but is considered pertinent to Applicant's disclosure:
U.S. Patent 10,055,228: teaches techniques for reducing power consumption in systems that use cache architectures with high clock frequency.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daniel C. Chappell whose telephone number is (571)272-5003. The examiner can normally be reached 1000-1800, Eastern.
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Daniel C. Chappell
Primary Examiner
Art Unit 2135
/Daniel C. Chappell/Primary Examiner, Art Unit 2135