DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 18 and 20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lin et al (US Publication No. 20170346405).
Regarding claim 1, Lin discloses a current sensing circuit (i.e., such as current sensing circuit fig. 1; see for example fig. 1, para. [0023]- [0037]) comprising: a current sensing (CS) pin (i.e., such as current sensing (CS) pin CS; see for example fig. 1, para. [0023]- [0037]); a first switch (i.e., such as first switch SW1; see for example fig. 1, para. [0023]- [0037]); a second switch (i.e., such as second switch SW2; see for example fig. 1, para. [0023]- [0037]), wherein the second switch (i.e., such as second switch SW2; see for example fig. 1, para. [0023]- [0037]) is connected between the first switch (i.e., such as first switch SW1; see for example fig. 1, para. [0023]- [0037]) and ground (i.e., such as ground GND; see for example fig. 1, para. [0023]- [0037]); a plurality of resistors (i.e., such as plurality of resistors RS, RA, RB; see for example fig. 1, para. [0023]- [0037]) connected between the second switch (i.e., such as second switch SW2; see for example fig. 1, para. [0023]- [0037]) and ground (i.e., such as ground GND; see for example fig. 1, para. [0023]- [0037]); and a resonant circuit (i.e., such as resonant circuit TR, Co; see for example fig. 1, para. [0023]- [0037]); wherein the plurality of resistors (i.e., such as plurality of resistors RS, RA, RB; see for example fig. 1, para. [0023]- [0037]) is configured (i.e., such as configured to; for instance, the dual-mode operation controller, which can have but will not be limited to having 5 exemplary pins: VDD pin (supply voltage input), GND pin (reference ground), Gate pin (gate driver output), CS pin (current sense input), and VS pin (voltage sense input), has its VDD pin connected to the input capacitor through a voltage regulator and the gate of the first primary-side switch; its GND pin connected to the low side of the input capacitor, the low side of the voltage divider, the low side of the voltage damper, the low side of the voltage regulator, and the low side of the current-sensing resistor; its Gate pin connected to the gate of the second primary-side switch; its CS pin connected to the source of the second primary-side switch and the high side of the current-sensing resistor; and its VS pin connected to the high side of the voltage damper and the midpoint of the voltage divider; see for example fig. 1, para. [0023]- [0037]) to detect (i.e., such as detect; for instance, more specifically, the dual-mode operation controller 10 would drive the second primary-side switch SW2 in response to the voltage sense signal from the voltage-sensing unit 20 and the current sense signal from the current-sensing resistor RS. The combination of the voltage sense signal from the voltage-sensing unit 20 and the current sense signal from the current-sensing resistor RS would clue the dual-mode operation controller 10 in on what the loading status is; see for example fig. 1, para. [0023]- [0037]) positive and/or negative (i.e., such as positive and/or negative; for instance, when both the first primary-side switch SW1 and the second primary-side switch SW2 are switched on to store energy, the current sense signal, fetched from the high side of the current-sensing resistor RS, is fed to the CS pin. Meanwhile, the VS pin receives no voltage sense signal because of being clamped at a slightly negative/positive potential (−0.3V/0.15V typical) due to the functioning voltage damper DA, activated by the induced negative voltage across the auxiliary winding N.sub.A and protecting the VS pin against an excessively negative voltage. The VS pin would sense a scaled-down reflected output voltage which is used for PSR, when both the first primary-side switch and the second primary-side switch switches off to release energy and the auxiliary winding induces a positive voltage; see for example fig. 1, para. [0023]- [0037]) over-currents (i.e., such as over-currents as high RMS current that reflects higher conduction loss; for instance, the flyback transformer can be downsized using DCM because the average energy storage is low compared to that in CCM. However, DCM causes high RMS current, which increases the conduction loss of the primary Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) severely for low-line condition. Thus, DCM, enabling valley switching and reducing switching loss within a relatively light load range, would get the short end of the stick within a relatively heavy load range, where CCM has the upper hand. In order to kill two birds with one stone, the present invention proposes a dual-mode operation controller, which can dynamically control a flyback converter to operate in QR-DCM within a relatively light load range to optimize the light-load conversion efficiencies by means of minimizing the dominant switching loss and in CCM within a relatively heavy load range to optimize the heavy-load conversion efficiencies by means of minimizing the dominant conduction loss, for the conversion efficiency to stay high throughout the entire load range, leading to significant improvement on the high/low-line average efficiencies, averaged over 25%, 50%, 75%, and 100% loadings at 115 Vac and 230 Vac; see for example fig. 1, para. [0023]- [0037]) in the CS pin (i.e., such as current sensing (CS) pin CS; see for example fig. 1, para. [0023]- [0037]).
Regarding claim 2, Lin discloses the current sensing circuit (i.e., such as current sensing circuit fig. 1; see for example fig. 1, para. [0023]- [0037]); wherein detecting (i.e., such as detect; for instance, More specifically, the dual-mode operation controller 10 would drive the second primary-side switch SW2 in response to the voltage sense signal from the voltage-sensing unit 20 and the current sense signal from the current-sensing resistor RS. The combination of the voltage sense signal from the voltage-sensing unit 20 and the current sense signal from the current-sensing resistor RS would clue the dual-mode operation controller 10 in on what the loading status is; see for example fig. 1, para. [0023]- [0037]) the positive and/or negative (i.e., such as positive and/or negative; for instance, when both the first primary-side switch SW1 and the second primary-side switch SW2 are switched on to store energy, the current sense signal, fetched from the high side of the current-sensing resistor RS, is fed to the CS pin. Meanwhile, the VS pin receives no voltage sense signal because of being clamped at a slightly negative/positive potential (−0.3V/0.15V typical) due to the functioning voltage damper DA, activated by the induced negative voltage across the auxiliary winding N.sub.A and protecting the VS pin against an excessively negative voltage. The VS pin would sense a scaled-down reflected output voltage which is used for PSR, when both the first primary-side switch and the second primary-side switch switches off to release energy and the auxiliary winding induces a positive voltage; see for example fig. 1, para. [0023]- [0037]) over-currents (i.e., such as over-currents as high RMS current that reflects higher conduction loss; for instance, the flyback transformer can be downsized using DCM because the average energy storage is low compared to that in CCM. However, DCM causes high RMS current, which increases the conduction loss of the primary Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) severely for low-line condition. Thus, DCM, enabling valley switching and reducing switching loss within a relatively light load range, would get the short end of the stick within a relatively heavy load range, where CCM has the upper hand. In order to kill two birds with one stone, the present invention proposes a dual-mode operation controller, which can dynamically control a flyback converter to operate in QR-DCM within a relatively light load range to optimize the light-load conversion efficiencies by means of minimizing the dominant switching loss and in CCM within a relatively heavy load range to optimize the heavy-load conversion efficiencies by means of minimizing the dominant conduction loss, for the conversion efficiency to stay high throughout the entire load range, leading to significant improvement on the high/low-line average efficiencies, averaged over 25%, 50%, 75%, and 100% loadings at 115 Vac and 230 Vac; see for example fig. 1, para. [0023]- [0037]) comprises: detecting (i.e., such as detect; for instance, more specifically, the dual-mode operation controller 10 would drive the second primary-side switch SW2 in response to the voltage sense signal from the voltage-sensing unit 20 and the current sense signal from the current-sensing resistor RS. The combination of the voltage sense signal from the voltage-sensing unit 20 and the current sense signal from the current-sensing resistor RS would clue the dual-mode operation controller 10 in on what the loading status is.; see for example fig. 1, para. [0023]- [0037]) if a voltage (i.e., such as voltage to be sensed via VS pin; for instance, when both the first primary-side switch SW1 and the second primary-side switch SW2 are switched on to store energy, the current sense signal, fetched from the high side of the current-sensing resistor RS, is fed to the CS pin. Meanwhile, the VS pin receives no voltage sense signal because of being clamped at a slightly negative/positive potential (−0.3V/0.15V typical) due to the functioning voltage damper DA, activated by the induced negative voltage across the auxiliary winding N.sub.A and protecting the VS pin against an excessively negative voltage. The VS pin would sense a scaled-down reflected output voltage which is used for PSR, when both the first primary-side switch and the second primary-side switch switches off to release energy and the auxiliary winding induces a positive voltage; see for example fig. 1, para. [0023]- [0037]) across the CS pin (i.e., such as current sensing (CS) pin CS; see for example fig. 1, para. [0023]- [0037]) is lower (i.e., such as lower; for instance, for instance, the flyback converter would be ushered into QR-DCM to optimize light-load conversion efficiencies by means of reducing dominant switching loss when the output load goes below the preset BCM level and into CCM to optimize heavy-load conversion efficiencies by means of reducing dominant conduction loss when the output load goes above the preset BCM level. Alternatively, another possible way for stably switching between QR-DCM and CCM with strengthened interference/noise immunity is to preset a hysteresis window with a lower threshold level and a higher threshold level instead of a single threshold level; see for example fig. 1, para. [0023]- [0037]) than a negative threshold (i.e., such as negative threshold; for instance, the flyback converter would be ushered into QR-DCM to optimize light-load conversion efficiencies by means of reducing dominant switching loss when the output load goes below the preset BCM level and into CCM to optimize heavy-load conversion efficiencies by means of reducing dominant conduction loss when the output load goes above the preset BCM level. Alternatively, another possible way for stably switching between QR-DCM and CCM with strengthened interference/noise immunity is to preset a hysteresis window with a lower threshold level and a higher threshold level instead of a single threshold level; see for example fig. 1, para. [0023]- [0037]) ; and/or detecting (i.e., such as detect; for instance, More specifically, the dual-mode operation controller 10 would drive the second primary-side switch SW2 in response to the voltage sense signal from the voltage-sensing unit 20 and the current sense signal from the current-sensing resistor RS. The combination of the voltage sense signal from the voltage-sensing unit 20 and the current sense signal from the current-sensing resistor RS would clue the dual-mode operation controller 10 in on what the loading status is; see for example fig. 1, para. [0023]- [0037]) if a voltage (i.e., such as voltage to be sensed via VS pin; for instance, for instance, when both the first primary-side switch SW1 and the second primary-side switch SW2 are switched on to store energy, the current sense signal, fetched from the high side of the current-sensing resistor RS, is fed to the CS pin. Meanwhile, the VS pin receives no voltage sense signal because of being clamped at a slightly negative/positive potential (−0.3V/0.15V typical) due to the functioning voltage damper DA, activated by the induced negative voltage across the auxiliary winding N.sub.A and protecting the VS pin against an excessively negative voltage. The VS pin would sense a scaled-down reflected output voltage which is used for PSR, when both the first primary-side switch and the second primary-side switch switches off to release energy and the auxiliary winding induces a positive voltage; see for example fig. 1, para. [0023]- [0037]) across the CS pin (i.e., such as current sensing (CS) pin CS; see for example fig. 1, para. [0023]- [0037]) is higher (i.e., such as higher; for instance, for instance, the flyback converter would be ushered into QR-DCM to optimize light-load conversion efficiencies by means of reducing dominant switching loss when the output load goes below the preset BCM level and into CCM to optimize heavy-load conversion efficiencies by means of reducing dominant conduction loss when the output load goes above the preset BCM level. Alternatively, another possible way for stably switching between QR-DCM and CCM with strengthened interference/noise immunity is to preset a hysteresis window with a lower threshold level and a higher threshold level instead of a single threshold level; see for example fig. 1, para. [0023]- [0037]) than a positive threshold (i.e., such as positive threshold; for instance, the flyback converter would be ushered into QR-DCM to optimize light-load conversion efficiencies by means of reducing dominant switching loss when the output load goes below the preset BCM level and into CCM to optimize heavy-load conversion efficiencies by means of reducing dominant conduction loss when the output load goes above the preset BCM level. Alternatively, another possible way for stably switching between QR-DCM and CCM with strengthened interference/noise immunity is to preset a hysteresis window with a lower threshold level and a higher threshold level instead of a single threshold level; see for example fig. 1, para. [0023]- [0037]).
Regarding claim 3, Lin discloses the current sensing circuit (i.e., such as current sensing circuit fig. 1; see for example fig. 1, para. [0023]- [0037]); wherein when it is detected (i.e., such as detect; for instance, more specifically, the dual-mode operation controller 10 would drive the second primary-side switch SW2 in response to the voltage sense signal from the voltage-sensing unit 20 and the current sense signal from the current-sensing resistor RS. The combination of the voltage sense signal from the voltage-sensing unit 20 and the current sense signal from the current-sensing resistor RS would clue the dual-mode operation controller 10 in on what the loading status is; see for example fig. 1, para. [0023]- [0037]) that the voltage (i.e., such as voltage to be sensed via VS pin; for instance, when both the first primary-side switch SW1 and the second primary-side switch SW2 are switched on to store energy, the current sense signal, fetched from the high side of the current-sensing resistor RS, is fed to the CS pin. Meanwhile, the VS pin receives no voltage sense signal because of being clamped at a slightly negative/positive potential (−0.3V/0.15V typical) due to the functioning voltage damper DA, activated by the induced negative voltage across the auxiliary winding N.sub.A and protecting the VS pin against an excessively negative voltage. The VS pin would sense a scaled-down reflected output voltage which is used for PSR, when both the first primary-side switch and the second primary-side switch switches off to release energy and the auxiliary winding induces a positive voltage; see for example fig. 1, para. [0023]- [0037]) across the CS pin (i.e., such as current sensing (CS) pin CS; see for example fig. 1, para. [0023]- [0037]) is lower (i.e., such as lower; for instance, for instance, the flyback converter would be ushered into QR-DCM to optimize light-load conversion efficiencies by means of reducing dominant switching loss when the output load goes below the preset BCM level and into CCM to optimize heavy-load conversion efficiencies by means of reducing dominant conduction loss when the output load goes above the preset BCM level. Alternatively, another possible way for stably switching between QR-DCM and CCM with strengthened interference/noise immunity is to preset a hysteresis window with a lower threshold level and a higher threshold level instead of a single threshold level; see for example fig. 1, para. [0023]- [0037]) than the negative threshold (i.e., such as negative threshold; for instance, the flyback converter would be ushered into QR-DCM to optimize light-load conversion efficiencies by means of reducing dominant switching loss when the output load goes below the preset BCM level and into CCM to optimize heavy-load conversion efficiencies by means of reducing dominant conduction loss when the output load goes above the preset BCM level. Alternatively, another possible way for stably switching between QR-DCM and CCM with strengthened interference/noise immunity is to preset a hysteresis window with a lower threshold level and a higher threshold level instead of a single threshold level; see for example fig. 1, para. [0023]- [0037]), it is determined (i.e., such as determined based upon certain detection; for instance, in general, DCM provides better switching conditions for the rectifier diodes, since the diodes are operating at zero current just before becoming reverse biased and the reverse recovery loss is minimized. Also in DCM, the primary-side switching component has the chance of being switched on at a certain detected voltage valley with the benefit of reduction in the switching loss and alleviation of Electromagnetic Interference (EMI) in the course of Quasi-Resonance between the primary inductor and the drain-source capacitor, when the primary inductor is set free from the clamping voltage −nV.sub.o and throws itself into the Quasi-Resonance with the drain-source capacitor after the complete flyback transformer demagnetization. The flyback transformer can be downsized using DCM because the average energy storage is low compared to that in CCM; see for example fig. 1, para. [0023]- [0037]) that there is a negative (i.e., such as negative; for instance, the flyback converter would be ushered into QR-DCM to optimize light-load conversion efficiencies by means of reducing dominant switching loss when the output load goes below the preset BCM level and into CCM to optimize heavy-load conversion efficiencies by means of reducing dominant conduction loss when the output load goes above the preset BCM level. Alternatively, another possible way for stably switching between QR-DCM and CCM with strengthened interference/noise immunity is to preset a hysteresis window with a lower threshold level and a higher threshold level instead of a single threshold level; see for example fig. 1, para. [0023]- [0037]) over-current (i.e., such as over-currents as high RMS current that reflects higher conduction loss; for instance, the flyback transformer can be downsized using DCM because the average energy storage is low compared to that in CCM. However, DCM causes high RMS current, which increases the conduction loss of the primary Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) severely for low-line condition. Thus, DCM, enabling valley switching and reducing switching loss within a relatively light load range, would get the short end of the stick within a relatively heavy load range, where CCM has the upper hand. In order to kill two birds with one stone, the present invention proposes a dual-mode operation controller, which can dynamically control a flyback converter to operate in QR-DCM within a relatively light load range to optimize the light-load conversion efficiencies by means of minimizing the dominant switching loss and in CCM within a relatively heavy load range to optimize the heavy-load conversion efficiencies by means of minimizing the dominant conduction loss, for the conversion efficiency to stay high throughout the entire load range, leading to significant improvement on the high/low-line average efficiencies, averaged over 25%, 50%, 75%, and 100% loadings at 115 Vac and 230 Vac; see for example fig. 1, para. [0023]- [0037]) and the second switch (i.e., such as second switch SW2; see for example fig. 1, para. [0023]- [0037]) is turned off (i.e., such as SW2 is OFF; for instance, for the sake of simplifying the description of the present invention, both the first primary-side switch and the second primary-side switch would be assumed hereafter to be a power MOSFET. The first primary-side switch is termed source-driven while the second primary-side switch is termed gate-driven because the former has its gate clamped at a nearly constant Zener breakdown voltage as a reference potential and its source driven by the drain of the second primary-side switch while the latter has its gate driven by the Gate pin of the dual-mode operation controller and its source clamped at a negligibly low current sense voltage as a reference potential. The first primary-side switch would get switched on if its source is connected to the primary-side ground when the second primary-side switch gets switched on. The first primary-side switch would get switched off if its source is disconnected from the primary-side ground when the second primary-side switch gets switched off. In other words, the switch-on/off of the first primary-side switch would be in sync with the switch-on/off of the second primary-side switch; see for example fig. 1, para. [0023]- [0037]).
Regarding claim 4, Lin discloses the current sensing circuit (i.e., such as current sensing circuit fig. 1; see for example fig. 1, para. [0023]- [0037]); wherein when a positive or negative (i.e., such as positive and/or negative; for instance, when both the first primary-side switch SW1 and the second primary-side switch SW2 are switched on to store energy, the current sense signal, fetched from the high side of the current-sensing resistor RS, is fed to the CS pin. Meanwhile, the VS pin receives no voltage sense signal because of being clamped at a slightly negative/positive potential (−0.3V/0.15V typical) due to the functioning voltage damper DA, activated by the induced negative voltage across the auxiliary winding N.sub.A and protecting the VS pin against an excessively negative voltage. The VS pin would sense a scaled-down reflected output voltage which is used for PSR, when both the first primary-side switch and the second primary-side switch switches off to release energy and the auxiliary winding induces a positive voltage; see for example fig. 1, para. [0023]- [0037]) over-current (i.e., such as over-currents as high RMS current that reflects higher conduction loss; for instance, the flyback transformer can be downsized using DCM because the average energy storage is low compared to that in CCM. However, DCM causes high RMS current, which increases the conduction loss of the primary Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) severely for low-line condition. Thus, DCM, enabling valley switching and reducing switching loss within a relatively light load range, would get the short end of the stick within a relatively heavy load range, where CCM has the upper hand. In order to kill two birds with one stone, the present invention proposes a dual-mode operation controller, which can dynamically control a flyback converter to operate in QR-DCM within a relatively light load range to optimize the light-load conversion efficiencies by means of minimizing the dominant switching loss and in CCM within a relatively heavy load range to optimize the heavy-load conversion efficiencies by means of minimizing the dominant conduction loss, for the conversion efficiency to stay high throughout the entire load range, leading to significant improvement on the high/low-line average efficiencies, averaged over 25%, 50%, 75%, and 100% loadings at 115 Vac and 230 Vac; see for example fig. 1, para. [0023]- [0037]) is detected (i.e., such as detect; for instance, more specifically, the dual-mode operation controller 10 would drive the second primary-side switch SW2 in response to the voltage sense signal from the voltage-sensing unit 20 and the current sense signal from the current-sensing resistor RS. The combination of the voltage sense signal from the voltage-sensing unit 20 and the current sense signal from the current-sensing resistor RS would clue the dual-mode operation controller 10 in on what the loading status is.; see for example fig. 1, para. [0023]- [0037]), the first switch (i.e., such as first switch SW1; see for example fig. 1, para. [0023]- [0037]) and the second switch (i.e., such as second switch SW2; see for example fig. 1, para. [0023]- [0037]) are controlled (i.e., such as controlled via IC 10; for instance, the dual-mode operation controller 10 in the first embodiment, lying at the heart of a PSR flyback converter, can be used in collocation with an input capacitor C1, a flyback transformer TR, a first primary-side switch SW1, a second primary-side switch SW2, a current-sensing resistor RS, a primary-side voltage-sensing unit 20, a secondary-side rectifier So, and an output capacitor Co for converting a unregulated DC input voltage source V.sub.IN into a regulated DC output voltage source V.sub.o some DC-powered devices can operate off of. The dual-mode operation controller 10 dynamically controls the PSR flyback converter to operate in two operating modes, QR-DCM and CCM, in accordance with the loading condition. The first primary-side switch SW1 and the second primary-side switch SW2, connected in series with the current-sensing resistor RS and placed at the low side of the primary-side winding N.sub.P, can be but will not be limited to a power MOSFET or a power BJT. The secondary-side rectifier So, which can be placed either at the secondary low side or at the secondary high side, can be but will not be limited to a diode rectifier or a synchronous rectifier; see for example fig. 1, para. [0023]- [0037]) to turn off (i.e., such as SW1 and SW2 are controlled to be OFF; for instance, for the sake of simplifying the description of the present invention, both the first primary-side switch and the second primary-side switch would be assumed hereafter to be a power MOSFET. The first primary-side switch is termed source-driven while the second primary-side switch is termed gate-driven because the former has its gate clamped at a nearly constant Zener breakdown voltage as a reference potential and its source driven by the drain of the second primary-side switch while the latter has its gate driven by the Gate pin of the dual-mode operation controller and its source clamped at a negligibly low current sense voltage as a reference potential. The first primary-side switch would get switched on if its source is connected to the primary-side ground when the second primary-side switch gets switched on. The first primary-side switch would get switched off if its source is disconnected from the primary-side ground when the second primary-side switch gets switched off. In other words, the switch-on/off of the first primary-side switch would be in sync with the switch-on/off of the second primary-side switch; see for example fig. 1, para. [0023]- [0037]).
Regarding claim 5, Lin discloses the current sensing circuit (i.e., such as current sensing circuit fig. 1; see for example fig. 1, para. [0023]- [0037]); wherein the resonant circuit (i.e., such as resonant circuit TR, Co; see for example fig. 1, para. [0023]- [0037]) comprises: an inductor (i.e., such as inductor TR; see for example fig. 1, para. [0023]- [0037]) and a capacitor (i.e., such as capacitor Co; see for example fig. 1, para. [0023]- [0037]); or an inductor.
Regarding claim 18, Lin discloses the current sensing circuit (i.e., such as current sensing circuit fig. 1; see for example fig. 1, para. [0023]- [0037]); wherein the first switch (i.e., such as first switch SW1; see for example fig. 1, para. [0023]- [0037]) is a main switch (i.e., such as SW1 is main switch as the primary switch to pass on the regulated energy to the load; see for example fig. 1, para. [0023]- [0037]); and wherein the second switch (i.e., such as second switch SW2; see for example fig. 1, para. [0023]- [0037]) is a reset switch (i.e., such as SW2 is reset switch as the secondary switch to reset/preset/adjust/set dynamically controlling the two operating modes, Quasi-Resonant-Discontinuous Conduction Mode (QR-DCM) and Continuous Conduction Mode (CCM), with respect to a loading condition so as to convert an unregulated DC input voltage source into a regulated DC output voltage source; see for example fig. 1, para. [0023]- [0037]).
Regarding claim 20, is rejected for the same reasons that have already been stated/discussed above in rejected claim 1. {See rejection of claim 1}
Allowable Subject Matter
Claims 6-17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, Lin teaches the invention set forth above. However, Lin does not particularly teach wherein the plurality of resistors comprises: first and second sensor resistors; and first and second configuration resistors.
Hence claim 6 will be deemed allowable if rewritten in an independent form.
Claims 7-17 and 19 depend on objected claim 6, consequently claims 7-17 and 19 will also be deemed allowable.
Conclusion
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/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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