Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-2 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,174,683 in view of Kandula(US 2019/0205042).
The elements in claims 1-2 of the current application and the corresponding elements in claims 1-20 of U.S. Patent No. 12,174,683 are substantially the same except the lower-power mode of the memory comprises a self-refresh mode. However, self-refresh mode is well known mode used in the art and is taught by Kandula(Paragraph 18, When the storage 120 is in the self-refresh state, the storage 120 may refresh the data on its own, e.g., without any intervention or facilitation from the memory controller. Thus, when the storage 120 is in the self-refresh state, the memory controller may be powered down, in a low power mode, in a power gated and/or a clock gated state, disabled, undergoing a reset cycle, etc). It would have been obvious to one of ordinary skill in the art at the time of filing to combine the teachings of U.S. Patent No. 12,174,683 and Kandula to use a self-refresh mode. The motivation to do so would be to use a well-known mode used in the art to main data in the memory and conserve power.
Claims 3-5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,174,683. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims 3-5 fall entirely within the scope of claims 1-20 of U.S. Patent No. 12,174,683. The elements in claims 3-5 of the current application and the corresponding elements in claims 1-20 of U.S. Patent No. 12,174,683 are substantially the same and therefore the instant claims 3-5 are obvious over claims 1-20 of U.S. Patent No. 12,174,683.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated Kocev(US 2012/0102344).
Regarding claim 1, Kocev discloses a system on chip (SoC) comprising: a plurality of circuitries(Figure 1, Cores 11) configured to access a memory(Figure 1, memory 6); a system interconnect circuit(Figure 2, hub 25) configured to operate based on a first clock signal(Figure 2, Clk) and provide a data transmission path between the plurality of circuitries and the memory(Figure 2, hub provides a path between Cores 21 and the memory 6 of Figure 1); and a power controller configured to receive an activity request signal from each of the plurality of circuitries(Paragraph 49, It is noted that each Core1Act, Core2Act, etc., may each represent multiple signals, although for the sake of simplicity only a single signal path is shown here for each. These signals may indicate whether or not there is activity in the corresponding processor cores 11. The received signals may indicate cache access attempts, cache misses, instructions issued, executed, or retired, memory access requests, and so on), control gating and ungating of the first clock signal of the system interconnect circuit based on a plurality of activity request signals received from the plurality of circuitries(Paragraphs 44-45, if NBFE power manager 220 does not receive an indication of an I/O DMA request for a time exceeding a first time threshold, and receives a signal indicating that all processor cores 11 are idle, it may cause I/O north bridge interface 23 to be clock-gated. Clock-gating of the I/O north bridge interface may be accomplished responsive to the assertion of the signal CG1. NBFE power manager 220 may continue monitoring I/O north bridge interface 23 for an extra amount of time up to a second time threshold. If the amount of time since the most recent DMA request from the I/O domain exceeds the second time threshold, NBFE power manager 220 may assert the CG2 signal to cause the clock-gating of communication hub 25), and control the memory to operate in a lower-power mode during a period in which the first clock signal is gated, wherein the power controller is further configured to control the first clock signal to be gated in response to all of the plurality of activity request signals having respective inactive levels, wherein the lower-power mode of the memory comprises a self-refresh mode(Paragraph 53, Memory controller power manager 205 may monitor each of processor cores 11, GPU 14, and I/O interface 13 for memory access requests and if no requests for certain time, memory controller power manager 205 may respond by asserting the low power state signal. This signal may be received by memory controller 18, and may cause it to place memory 6 into a low power state (e.g., a self-refresh state)).
Regarding claim 2, Kocev discloses SoC claim 1, wherein the system interconnect circuit comprises a plurality of routers connected in a form of network(Paragraph 39, communication hub 25, which may serve as an intersection point for communications between the I/O domain, processor cores 11, the memory, and GPU 14. Communications hub 25 may also be an intersection point for communications between and among processor cores 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kocev.
Regarding claim 3, Kocev discloses application processor comprising: a plurality of circuitries(Figure 1, Cores 11); a shared module(Figure 1, Memory 6) shared by the plurality of circuitries; an interconnect circuit(Figure 2, hub 25) configured to operate based on a first clock signal(Figure 2, Clk) to connect the plurality of circuitries and the shared module(Figure 2, hub provides a path for Cores 21 and shared module); and a power controller configured to generate a gating control signal controlling the first clock signal to be periodically gated to provide the gating control signal to the interconnect circuit, and based on a plurality of state signals received from the plurality of circuitries, adjust the gating control signal to maintain a state in which the first clock signal is gated or a state in which the first clock signal is used in the interconnect circuit(Paragraphs 44-45, if NBFE power manager 220 does not receive an indication of an I/O DMA request for a time exceeding a first time threshold, and receives a signal indicating that all processor cores 11 are idle, it may cause I/O north bridge interface 23 to be clock-gated. Clock-gating of the I/O north bridge interface may be accomplished responsive to the assertion of the signal CG1. NBFE power manager 220 may continue monitoring I/O north bridge interface 23 for an extra amount of time up to a second time threshold. If the amount of time since the most recent DMA request from the I/O domain exceeds the second time threshold, NBFE power manager 220 may assert the CG2 signal to cause the clock-gating of communication hub 25).
Kocev does not specifically disclose the power controller is further configured to provide the gating control signal to at least one circuitry among the plurality of circuitries. However, Kocev discloses, Paragraph 43, Power management unit 20 is configured to generate a number of clock-gating signals (e.g., CG1-CG4, CGCI1, etc.) that may cause corresponding functional units of north bridge 12 to be clock gated. These signals may be provided from power management unit 20 to PLL 4 (or another type of clock control or clock network control block) as part of the group of signals SetF[M:0]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the power controller configured to provide the gating control signal to at least one circuitry among the plurality of circuitries. The motivation to do so would be to use the gating signal to gate circuitry that is not needed for conserving power.
Regarding claim 4, Kocev discloses application processor of claim 3, but does not specifically the at least one circuitry among the plurality of circuitries comprises a first block related to access to the shared module; and a second block independent of the access to the shared module, wherein the at least one circuitry is configured to gate and ungate a reference clock signal used in the first block based on the gating control signal. However, Kocev disclose Power management unit 20 is configured to generate a number of clock-gating signals (e.g., CG1-CG4, CGCI1, etc.) that may cause corresponding functional units within a circuit be clock gated(Paragraph 43). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have at least one circuitry among the plurality of circuitries comprises a first block related to access to the shared module; and a second block independent of the access to the shared module, wherein the at least one circuitry is configured to gate and ungate a reference clock signal used in the first block based on the gating control signal. The motivation to do so would be to gate only portions of the circuitry that are needed.
Regarding claim 5, Kocev discloses application processor of claim 3, wherein the shared module comprises a static random access memory (SRAM)(Paragraph 84, SRAM).
Conclusion
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/NIMESH G PATEL/ Primary Examiner, Art Unit 2187
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