DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Email Communication
Applicant is encouraged to authorize the Examiner to communicate with applicant via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.03, 502.05.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim(s) 15 is/are objected to because of the following informalities: claim 15 should depend on claim 14 as it further defines the limitation of claim 14 not claim 11. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 10, & 14-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Uchida (US 2020/0312569).
In regards to claim 1, Uchida ‘569 discloses
A multilayer electronic component comprising:
a body (10 & 41-42 – fig. 1-4; [0049]) including a dielectric layer (20 – fig. 2-4; [0029]) and internal electrodes (21-22 – fig. 3-4; [0029]) alternately disposed with the dielectric layer; and
external electrodes (51-52 – fig. 1 & 3; [0025]) disposed on length-wise opposing surfaces of the body,
wherein, when a widthwise central portion of the dielectric layer is a first region and widthwise end portions of the dielectric layer are second regions, the first region has a higher permittivity than the second regions (fig. 5; [0072] – it is noted that the larger diameter area will have a higher permittivity than the smaller diameter area).
In regards to claim 2, Uchida ‘569 discloses
The multilayer electronic component of claim 1, wherein the body includes first and second surfaces opposing each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction (fig. 1-4), and
includes a capacitance formation portion (30 – fig. 3-4; [0049]) in which the dielectric layer and the internal electrodes are alternately disposed in the first direction, cover portions (31 & 32 – fig. 3-4; [0049]) disposed above and below the capacitance formation portion in the first direction, and margin portions (41 & 42 – fig. 4; [0049]) disposed at both sides of the capacitance formation portion in the third direction,
wherein the width direction is the third direction (fig. 5).
In regards to claim 3, Uchida ‘569 discloses
The multilayer electronic component of claim 2, wherein the first region is disposed to connect the third surface and the fourth surface in the second direction, and the second region is disposed to connect the third surface and the fourth surface in the second direction (fig. 5; [0072]).
In regards to claim 4, Uchida ‘569 discloses
The multilayer electronic component of claim 2, wherein at least a portion of the second region is disposed to overlap the internal electrodes in the first direction (fig. 4).
In regards to claim 10, Uchida ‘569 discloses
The multilayer electronic component of claim 2, wherein 0.3 ≤ Wc/Wi ≤ 0.9 in which when Wc is a width of the first region in the third direction and Wi is a width of the internal electrode in the third direction (fig. 5; [0072-0078] – the examiner is taking Wc to be 90% of Wi).
In regards to claim 14, Uchida ‘569 discloses
The multilayer electronic component of claim 2, wherein the cover portion includes the dielectric layer (fig. 3; [0049]).
In regards to claim 15, Uchida ‘569 discloses
The multilayer electronic component of claim 11, wherein the first region of the dielectric layer included in the cover portion is disposed to connect the third surface and the fourth surface in the second direction, and the second region of the dielectric layer included in the cover portion is disposed to connect the third surface and the fourth surface in the second direction (fig. 5; [0049] & [0072]).
In regards to claim 16, Uchida ‘569 discloses
A multilayer electronic component, comprising:
a dielectric layer (20 – fig. 2-4; [0029]) disposed in a length-width plane of a body of the component, and comprising a first region disposed in a width-wise central portion of the dielectric layer (fig. 5; [0072]), and a second region disposed in width-wise peripheral portions of the dielectric layer (fig. 5; [0072]); and
an internal electrode (21-22 – fig. 3-4; [0029]) disposed over the dielectric layer,
wherein the first region of the dielectric layer has a higher permittivity than the second region (fig. 5; [0072] – it is noted that the larger diameter area will have a higher permittivity than the smaller diameter area).
In regards to claim 17, Uchida ‘569 discloses
The multilayer electronic component of claim 16, wherein width-wise end portions of the second region do not overlap with the internal electrode (fig. 5).
In regards to claim 18, Uchida ‘569 discloses
The multilayer electronic component of claim 16, wherein a width of the first region is in a range from 0.3 to 0.9 times a width of the dielectric layer (fig. 5; [0072-0078] – the examiner is taking the width of the first region to be 90% a width of the dielectric layer).
In regards to claim 19, Uchida ‘569 discloses
The multilayer electronic component of claim 16, wherein a dielectric grain size in the first region is different from a dielectric grain size in the second region (fig. 5; [0072]).
Claim(s) 1-4, 9, 11, 16-17 & 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2021/0027947).
In regards to claim 1, Kim ‘947 discloses
A multilayer electronic component comprising:
a body (110 – fig. 1; [0041]) including a dielectric layer (111 – fig. 2B & 3; [0046]) and internal electrodes (121-122 – fig. 2B & 3; [0047]) alternately disposed with the dielectric layer; and
external electrodes (131-132 – fig. 3; [0038]) disposed on length-wise opposing surfaces of the body,
wherein, when a widthwise central portion of the dielectric layer is a first region (A regions) and widthwise end portions of the dielectric layer are second regions (B regions), the first region has a higher permittivity than the second regions (fig. 2B).
In regards to claim 2, Kim ‘947 discloses
The multilayer electronic component of claim 1, wherein the body includes first and second surfaces opposing each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction (fig. 2B-3), and
includes a capacitance formation portion (115) in which the dielectric layer and the internal electrodes are alternately disposed in the first direction, cover portions (112-113) disposed above and below the capacitance formation portion in the first direction, and margin portions disposed at both sides of the capacitance formation portion in the third direction (fig. 2B-3; [0039),
wherein the width direction is the third direction (fig. 2B-3).
In regards to claim 3, Kim ‘947 discloses
The multilayer electronic component of claim 2, wherein the first region is disposed to connect the third surface and the fourth surface in the second direction, and the second region is disposed to connect the third surface and the fourth surface in the second direction (fig. 2-4; [0043-0045]).
In regards to claim 4, Kim ‘947 discloses
The multilayer electronic component of claim 2, wherein at least a portion of the second region is disposed to overlap the internal electrodes in the first direction (fig. 2B).
In regards to claim 9, Kim ‘947 discloses
The multilayer electronic component of claim 2, wherein an average permittivity of the first region is in a range from 1.05 times to 1.6 times an average permittivity of the second region (table 1).
In regards to claim 11, Kim ‘947 discloses
The multilayer electronic component of claim 2, wherein the dielectric layer has a maximum change in permittivity at a point at which the first region and the second region meet (fig. 2B).
In regards to claim 16, Kim ‘947 discloses
A multilayer electronic component, comprising:
a dielectric layer (111 – fig. 2B & 3; [0046]) disposed in a length-width plane of a body of the component, and comprising a first region (A regions) disposed in a width-wise central portion of the dielectric layer, and a second region regions (B regions) disposed in width-wise peripheral portions of the dielectric layer (fig. 2B; [0045]); and
an internal electrode (121-122 – fig. 2B & 3; [0047]) disposed over the dielectric layer,
wherein the first region of the dielectric layer has a higher permittivity than the second region (table 1).
In regards to claim 17, Kim ‘947 discloses
The multilayer electronic component of claim 16, wherein width-wise end portions of the second region do not overlap with the internal electrode (fig. 2B).
In regards to claim 19, Kim ‘947 discloses
The multilayer electronic component of claim 16, wherein a dielectric grain size in the first region is different from a dielectric grain size in the second region ([0081]).
In regards to claim 20, Kim ‘947 discloses
The multilayer electronic component of claim 16, wherein a ratio of permittivity of the first region to that of the second region is in a range from 1.05 to 1.6 (table 1).
Claim(s) 1-8 & 10-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2022/0139625).
In regards to claim 1, Lee ‘625 discloses
A multilayer electronic component comprising:
a body (110 – fig. 1; [0032]) including a dielectric layer (111/113 – fig. 2-3; [0036]) and internal electrodes (121-122 – fig. 2-3; [0032]) alternately disposed with the dielectric layer; and
external electrodes (131-132 – fig. 2; [0035]) disposed on length-wise opposing surfaces of the body,
wherein, when a widthwise central portion of the dielectric layer is a first region (R1 or R1-R2 – fig. 4; [0038]) and widthwise end portions of the dielectric layer are second regions (R2-R4 or R3-R4 – fig. 4; [0038]), the first region has a higher permittivity than the second regions (table 1 – it is noted that the larger diameter area will have a higher permittivity than the smaller diameter area).
In regards to claim 2, Lee ‘625 discloses
The multilayer electronic component of claim 1, wherein the body includes first and second surfaces opposing each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction (fig. 1-3), and
includes a capacitance formation portion (112 – fig. 4; [0038]) in which the dielectric layer and the internal electrodes are alternately disposed in the first direction, cover portions (114 – fig. 4; [0036]) disposed above and below the capacitance formation portion in the first direction, and margin portions (113 – fig. 4; [0038]) disposed at both sides of the capacitance formation portion in the third direction,
wherein the width direction is the third direction.
In regards to claim 3, Lee ‘625 discloses
The multilayer electronic component of claim 2, wherein the first region is disposed to connect the third surface and the fourth surface in the second direction, and the second region is disposed to connect the third surface and the fourth surface in the second direction (fig. 4; [0038]).
In regards to claim 4, Lee ‘625 discloses
The multilayer electronic component of claim 2, wherein at least a portion (R2) of the second region is disposed to overlap the internal electrodes in the first direction (fig. 3-4)
In regards to claim 5, Lee ‘625 discloses
The multilayer electronic component of claim 2, wherein the second region (R2-R4) is disposed in the margin portion and the capacitance formation portion (fig. 3-4)
In regards to claim 6, Lee ‘625 discloses
The multilayer electronic component of claim 2, wherein, when a region of the second region disposed in the capacitance formation portion is a 2a region (R2) and a region thereof disposed in the margin portion is a 2b region (R3-R4), the 2a region has a higher permittivity than the 2b region (table 1 – it is noted that the larger diameter area will have a higher permittivity than the smaller diameter area).
In regards to claim 7, Lee ‘625 discloses
The multilayer electronic component of claim 2, wherein a permittivity gradually decreases from the first region to the second region (table 1 – it is noted that as the diameter of the grain are reduced so will the permittivity be reduced).
In regards to claim 8, Lee ‘625 discloses
The multilayer electronic component of claim 2, wherein the second region has a permittivity that gradually decreases away from the first region (table 1 – it is noted that as the diameter of the grain are reduced so will the permittivity be reduced).
In regards to claim 10, Lee ‘625 discloses
The multilayer electronic component of claim 2, wherein 0.3 ≤ Wc/Wi ≤ 0.9 in which when Wc is a width of the first region in the third direction and Wi is a width of the internal electrode in the third direction (fig. 4; [0038])
In regards to claim 11, Lee ‘625 discloses
The multilayer electronic component of claim 2, wherein the dielectric layer has a maximum change in permittivity at a point at which the first region and the second region meet (table 1 – it is noted that the larger diameter area will have a higher permittivity than the smaller diameter area).
In regards to claim 12, Lee ‘625 discloses
The multilayer electronic component of claim 11, wherein a rate of decrease in permittivity of the second region decreases away from the first region (fig. 4; [0038] & table 1).
In regards to claim 13, Lee ‘625 discloses
The multilayer electronic component of claim 11, wherein a rate of increase in permittivity of the first region decreases away from the second region (fig. 4; [0038] & table 1).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2021/0005382 – fig. 5 US 2022/0208455 – fig. 4
JP2012049449A – fig. 2-3 US 2019/0180936 – abstract
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY J DOLE can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David M Sinclair/Primary Examiner, Art Unit 2847
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