DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Das Sharma et al. (US Pub. No. 2022/0334932), hereinafter referred to as Das Sharma, in view of Raupp Da Rosa et al. (2017/0262389), hereinafter referred to as Raupp, further in view of Aingaran et al. (US Pub. No. 2016/0261513), hereinafter referred to as Aingaran.
Referring to claim 1, Das Sharma discloses a side sideband interface (SSBI) (UCIe , [0068]; sideband connection, [0079]) comprising: a protocol handler configured to convert multiple protocols (logic (e.g., 535, 540) to simultaneously implement and support multiple protocols, [0062]) into a streaming protocol (UCIe also defines a “streaming protocol” which can be used to map any other protocol onto the flit format(s), [0073]) and perform arbitration or demultiplexing on various transactions (an arbitration and multiplexer layer (e.g., 520) may be provided, [0062]; perform arbitration/multiplexing of the multiple sub-protocols of CXL, [0077]; fig. 4, 455a-b); and a link layer (link layer 210, [0039]).
While Das Sharmar teaches a SERDES/transceiver configured to serialize data to be transmitted based on a credit-based flow control and configured to deserialize data being received based on the credit-based flow control (a stand-alone SERDES/transceiver tile, [0068]; data transmitted from a UCIe die to a UCIe retimer may be flow-controlled using credits, [0082-0083]), Das Sharma does not describe the transceiver in terms of separate transmission finite state machine (TX FSM) and receiver finite state machine (RX FSM). As well, while Das Sharma teaches transmissions consume credits and responses restore credits, which in view of the teaching of a SERDES/transceivers would involve being “available to serialize data” and “serializing data”, and “when deserializing data” and “when available to deserialize data”, Das Sharma does not appear to explicitly disclose the credit flow in terms of credits exchanged between the transmitter and receiver sides in the manner that the transmit side “contains a credit when available to serialize data and does not contain the credit when serializing data” and receive “contains the credit when deserializing data and does not contain the credit when available to deserialize data.”
However, Raupp teaches a transmitting and receiving architecture in which the transmitter and receiver are designed in the form of hardware blocks forming finite-state machines (see [0116]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma and Raupp before him or her, to implement the SERDES/transceiver architecture anticipated by Das Sharma as the separate FSMs as taught by Raupp because Das Sharma demonstrates the prior art contained a device (method, product, etc.) which differed from the claimed device by the substitution of the anticipated SERDES/transceiver architecture with a specific FMS arrangement; Raupp demonstrates the substituted TX and RX FSM were known in the art and provide the same functions of transmitting, receiving, serializing, and deserializing; and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable transmitting and receiving architecture for serial communications.
Furthermore, Aingaran teaches a credit-based flow control which exchanges credits between a transmitter and a receiver ([0030], [0044], [0049]), which in combination with the SERDES of Das Sharma and FMS architecture of Raupp, teaches each element of the limitations “wherein the TX FSM contains a credit when available to serialize data and does not contain the credit when serializing data” and “wherein the RX FSM contains the credit when deserializing data and does not contain the credit when available to deserialize data.”
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma, Raupp, and Aingaran before him or her, to implement the credit-based flow control anticipated by Das Sharma in view of Raupp according to the credit exchange scheme taught by Aingaran because Das Sharma demonstrates the prior art contained a device (method, product, etc.) which differed from the claimed device by the substitution of the anticipated credit-based flow control with a specific credit exchange scheme; Aingaran demonstrates the substituted credit exchange scheme was known in the art and provide the same flow control capability; and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable flow control between transmitters and receivers.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (see MPEP 2143.I.B).
Das Sharma, Raupp, and Aingaran are analogous art because they are from the same field of endeavor, managing interconnect fabric communications, and therefore, it would have been obvious to combine Das Sharma, Raupp, and Aingaran to obtain the invention as specified in the instant claim.
As to claim 5, Das Sharma discloses the protocol handler further comprises a protocol arbitrator configured to receive a plurality of data requests and push a data request of the plurality of data requests (an arbitration and multiplexer layer (e.g., 520) may be provided, [0062]; perform arbitration/multiplexing of the multiple sub-protocols of CXL, [0077]; fig. 4, 455a-b) to the link layer via a scheme (CXL link layer logic 510 may interface with CXL arbitration/multiplexing (ARB/MUX) logic 520, which interleaves the traffic from the two logic streams, [0059]).
Das Sharma does not appear to explicitly disclose the interleaving is in a round-robin format. However, one of ordinary skill in the art would recognize that “a round-robin scheme” is one of a finite number of solutions to interleaving and is the simplest of interleaving schemes providing a fixed, cyclic order. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharm to pursue the known potential solutions with reasonable expectation of success because "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103."KSR, 550 U.S. at 421, 82 USPQ2d at 1397. (see MPEP 2143.I.E).
As to claim 6, Das Sharma discloses the protocol handler further comprises a protocol demultiplexer configured to distribute data responses based on their transaction protocol (fig. 4, mux/demux 455a-b; the receiving side the reverse process occurs and packets get transformed, [0040]; CXL multiplexing logic (e.g., 455a-b) may also be provided to enable multiplexing of CXL protocols, [0056]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Das Sharma, Raupp, and Aingaran, as applied to claims 1 and 5-6 above, further in view of Becht et al. (US Pub. No. 2025/0076375), hereinafter referred to as Becht.
As to claim 2, while Das Sharma discloses configuring the protocol handler and link layer (link layer 210…communication protocol stack 200, [0039]), the combination of Das Sharma, Raupp, and Aingaran does not appear to explicitly disclose a control status register (CSR) wrapper containing a plurality of CSRs.
However, Becht discloses a control status register (CSR) wrapper containing a plurality of CSRs (collection of wrapper registers 340 may be an extension to control and status registers (CSRs), [0038]).
Das Sharma, Raupp, Aingaran, and Becht are analogous art because they are from the same field of endeavor, managing interconnect fabric communications.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma, Raupp, Aingaran, and Becht before him or her, to modify the interconnect system of Das Sharma to include the CSRs of Becht because the prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference; one of ordinary skill in the art could have combined the elements as claimed by known methods, and in combination, the combined CSRs elements merely performs the same function as it does separately; and one of ordinary skill in the art would have recognized that the results of the combination were predictable interconnection configuration and control architecture.
The rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. KSR, 550 U.S. at 416, 82 USPQ2d at 1395 (see MPEP 2143.I.A).
Therefore, it would have been obvious to combine Das Sharma, Raupp, Aingaran, and Becht to obtain the invention as specified in the instant claim.
Claims 3-4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Das Sharma, Raupp, and Aingaran as applied to claims 1 and 5-6 above, further in view of Jin et al. (US Pub. No. 2025/0181524), hereinafter referred to as Jin.
Referring to claim 3, Das Sharma discloses the protocol handler further comprises a target interface converter configured to: receive a data request in a first protocol and convert the request into the streaming protocol (UCIe also defines a “streaming protocol” which can be used to map any other protocol onto the flit format(s), [0073]); and receive a data response in the streaming protocol and convert the data response into the first protocol (At the receiving side the reverse process occurs and packets get transformed from their Physical Layer 220 representation to the Data Link Layer 210 representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer 205 of the receiving device, [0040]; a protocol may implement split transactions, i.e. transactions with request and response separated by time, [0042]).
While Das Sharma teaches the target interface converter and is concerned with “when the data response is not received within a predetermined amount of time” (make sure the different UCIe die are in sync and do not timeout waiting for a response, [0100]), Das Sharma does not appear to specifically handle timeouts by asserting “an error interrupt.”
However, Jin teaches a timeout interrupt (an interrupt signal in response to the occurrence of a transaction timeout, [0072]).
Das Sharma, Raupp, Aingaran, and Jin are analogous art because they are from the same field of endeavor, managing interconnect fabric communications.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma, Raupp, Aingaran, and Jin before him or her, to modify the interconnect system of Das Sharma to include the interrupt of Jin in order to signal a transaction timeout.
The suggestion/motivation for doing so would have been to identify operating issues for corrective action (Jin: [0056]).
Therefore, it would have been obvious to combine Das Sharma, Raupp, Aingaran, and Jin to obtain the invention as specified in the instant claim.
As to claim 4, Das Sharma discloses the protocol handler further comprises an initiator interface converter configured to: receive a data request in the streaming protocol and convert the data request into a first protocol; and receive a data response in the first protocol and convert the response into the streaming protocol (At the receiving side the reverse process occurs and packets get transformed from their Physical Layer 220 representation to the Data Link Layer 210 representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer 205 of the receiving device, [0040]; a protocol may implement split transactions, i.e. transactions with request and response separated by time, [0042]; UCIe also defines a “streaming protocol” which can be used to map any other protocol onto the flit format(s), [0073]);
While Das Sharma teaches the initiator interface converter and is concerned with “when the data response is not received within a predetermined amount of time” (make sure the different UCIe die are in sync and do not timeout waiting for a response, [0100]), Das Sharma does not appear to specifically handle timeouts by asserting “an error interrupt.”
However, Jin teaches a timeout interrupt (an interrupt signal in response to the occurrence of a transaction timeout, [0072]).
Das Sharma, Raupp, Aingaran, and Jin are analogous art because they are from the same field of endeavor, managing interconnect fabric communications.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma, Raupp, Aingaran, and Jin before him or her, to modify the interconnect system of Das Sharma to include the interrupt of Jin in order to signal a transaction timeout.
The suggestion/motivation for doing so would have been to identify operating issues for corrective action (Jin: [0056]).
Therefore, it would have been obvious to combine Das Sharma, Raupp, Aingaran, and Jin to obtain the invention as specified in the instant claim.
As to claim 9, as demonstrated above, the combination of Das Sharma, Raupp, Aingaran teaches the instance when the TX FSM does not contain a credit, and while both Das Sharma and Aingaran consider instances “when the TX FSM does not contain the credit for a predetermined amount of time” (Das Sharma: make sure the different UCIe die are in sync and do not timeout waiting for a response, [0100]; Aingaran: any time sender…is awaiting a response from the receiver, [0068]), the combination does not appear to specifically handle timeouts by triggering a timeout error.
However, Jin teaches a triggering a timeout error (an interrupt signal in response to the occurrence of a transaction timeout, [0072]).
Das Sharma, Raupp, Aingaran, and Jin are analogous art because they are from the same field of endeavor, managing interconnect fabric communications.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma, Raupp, Aingaran, and Jin before him or her, to modify the interconnect system of Das Sharma to include the interrupt of Jin in order to signal a transaction timeout.
The suggestion/motivation for doing so would have been to identify operating issues for corrective action (Jin: [0056]).
Therefore, it would have been obvious to combine Das Sharma, Raupp, Aingaran, and Jin to obtain the invention as specified in the instant claim.
Claims 7-8 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Das Sharma, Raupp, and Aingaran as applied to claims 1 and 5-6 above, further in view of Schultz et al. (US Pub. No. 2024/0186999), hereinafter referred to as Schultz.
As to claim 7, while Da Sharma depicts the link layer for data connections in both the source and target direction (fig. 2 and 5; Data Link Layer 210 to carry the information from the transmitting component to the…At the receiving side the reverse process occurs, [0040]) and teaches the use of a clock and data pin (clock pin and a data pin in each direction, [0079]), Da Sharma does not appear to explicitly depict the link layer architecture comprising the clock and data connection.
However, Schultz discloses the link layer of link layer architecture comprising the clock and data connection (fig. 8, [0152], [0157-0158]).
Das Sharma, Raupp, Aingaran, and Schultz are analogous art because they are from the same field of endeavor, chip interconnects.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma, Raupp, Aingaran, and Schultz before him or her, to modify the interconnect system of Das Sharma to include the link layer clock and data connections of Schultz because the prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference; one of ordinary skill in the art could have combined the elements as claimed by known methods, and in combination, the combined data and clock elements merely perform the same function as they do separately; and one of ordinary skill in the art would have recognized that the results of the combination were predictable interconnection configuration and control architecture.
The rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. KSR, 550 U.S. at 416, 82 USPQ2d at 1395 (see MPEP 2143.I.A).
Therefore, it would have been obvious to combine Das Sharma, Raupp, Aingaran, and Schultz to obtain the invention as specified in the instant claim.
As to claim 8, the combination of Das Sharma, Raupp, Aingaran, and Schultz discloses the TX FSM is configured to serialize (Das Sharma: usages such as integrating a stand-alone SERDES/transceiver tile, [0068]; Raupp: [0116]) a data request through the source data pin bit by bit while the source clock pin indicates there is valid data to sample per cycle (Das Sharma: clock pin and a data pin in each direction, [0079]; Schultz: The link layer circuitry 824 receives the clock signal 841 and the data signal 813. The link layer circuitry 824 generates a framing pattern from the data signal 813. Further, the link layer circuitry 824 generates the data signal 825 based on the clock signal 841. In one example, the data signal 813 is transmitted with a framing signal. The framing signal defines areas of valid data within the data signal 813. In one example, the framing signal is used to mask out invalid data within the data signal 813, [0152]). The rationale to combine remains as indicated above.
As to claim 10, while Da Sharma depicts the link layer for data connections in both the source and target direction (fig. 2 and 5; Data Link Layer 210 to carry the information from the transmitting component to the…At the receiving side the reverse process occurs, [0040]) and teaches the use of a clock and data pin (clock pin and a data pin in each direction, [0079]), Da Sharma does not appear to explicitly depict the link layer architecture comprising the clock and data connection.
However, Schultz discloses the link layer of link layer architecture comprising the clock and data connection (fig. 8, [0152], [0157-0158]).
Das Sharma, Raupp, Aingaran, and Schultz are analogous art because they are from the same field of endeavor, chip interconnects.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma, Raupp, Aingaran, and Schultz before him or her, to modify the interconnect system of Das Sharma to include the link layer clock and data connections of Schultz because the prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference; one of ordinary skill in the art could have combined the elements as claimed by known methods, and in combination, the combined data and clock elements merely perform the same function as they do separately; and one of ordinary skill in the art would have recognized that the results of the combination were predictable interconnection configuration and control architecture.
The rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. KSR, 550 U.S. at 416, 82 USPQ2d at 1395 (see MPEP 2143.I.A).
Therefore, it would have been obvious to combine Das Sharma, Raupp, Aingaran, and Schultz to obtain the invention as specified in the instant claim.
As to claim 11, the combination of Das Sharma, Raupp, Aingaran, and Schultz discloses the RX FSM is configured to deserialize (Das Sharma: usages such as integrating a stand-alone SERDES/transceiver tile, [0068]; Raupp: [0116]) a data response through the target data pin bit by bit while the target clock pin indicates there is valid data to sample per cycle (Das Sharma: clock pin and a data pin in each direction, [0079]; Schultz: The link layer circuitry 824 receives the clock signal 841 and the data signal 813. The link layer circuitry 824 generates a framing pattern from the data signal 813. Further, the link layer circuitry 824 generates the data signal 825 based on the clock signal 841. In one example, the data signal 813 is transmitted with a framing signal. The framing signal defines areas of valid data within the data signal 813. In one example, the framing signal is used to mask out invalid data within the data signal 813, [0152]). The rationale to combine remains as indicated above.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Das Sharma, Raupp, Aingaran, and Schultz, as applied to claims 7-8 and 10-11 above, further in view of Jin.
As to claim 12, as demonstrated above, the combination of Das Sharma, Raupp, Aingaran, and Schultz teaches the RX FSM, and Das Sharma is concerned with “when the RX FSM does not receive a data packet within a predetermined amount of time” (make sure the different UCIe die are in sync and do not timeout waiting for a response, [0100]), the combination does not appear to specifically handle timeouts by triggering a timeout error.
However, Jin teaches a triggering a timeout error (an interrupt signal in response to the occurrence of a transaction timeout, [0072]).
Das Sharma, Raupp, Aingaran, Schultz, and Jin are analogous art because they are from the same field of endeavor, managing interconnect fabric communications.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma, Raupp, Aingaran, Schultz, and Jin before him or her, to modify the interconnect system of Das Sharma to include the interrupt of Jin in order to signal a transaction timeout.
The suggestion/motivation for doing so would have been to identify operating issues for corrective action (Jin: [0056]).
Therefore, it would have been obvious to combine Das Sharma, Raupp, Aingaran, Schultz, and Jin to obtain the invention as specified in the instant claim.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Das Sharma, Raupp, Aingaran, and Schultz, as applied to claims 7-8 and 10-11 above, further in view of Farrokhbakht et al. (US Pub. No. 2024/0129260), hereinafter referred to as Farrokhbakht.
As to claim 13, as demonstrated above, the combination of Das Sharma, Raupp, Aingaran teaches a flow control mechanism including credits between a RX FSM and a TX FSM, in which a receive side does “not send the credit to the TX FSM” until after the message from the sender is processed. The combination does not appear to explicitly disclose the step “to drop data of the data packet already received and not send the credit to the TX FSM based on an error being triggered.”
However, Farrokhbakht discloses a step “to drop data of the data packet already received” when processing cannot be completed “based on an error being triggered” (send NACKs to a sender of forward packets when the router drops the forward packets due to at least: forward packets cannot make progress to the next hop due to insufficient credit in F.sub.VN or a fault or flow control cannot reserve the required buffer slots for the corresponding backward packet due to insufficient buffer space in B.sub.VN over the return path, [0084]).
Das Sharma, Raupp, Aingaran, Schultz, and Farrokhbakht are analogous art because they are from the same field of endeavor, managing interconnect fabric communications.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma, Raupp, Aingaran, Schultz, and Farrokhbakht before him or her, to modify the interconnect system of Das Sharma to include the acknowledgement scheme of Farrokhbakht in order to convey the status of packets.
The suggestion/motivation for doing so would have been to remedy congestion (Farrokhbakht: [0058]).
Therefore, it would have been obvious to combine Das Sharma, Raupp, Aingaran, Schultz, and Farrokhbakht to obtain the invention as specified in the instant claim.
Claims 14-15 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Das Sharma in view of Raupp, further in view of Aingaran, and further in view of Schultz.
Referring to claim 14, Das Sharma discloses a method for transmitting data via a side sideband interface (SSBI) (UCIe , [0068]; sideband connection, [0079]) comprising: receiving, by a target interface converter of a protocol handler of the SSBI, a data request in a first protocol (logic (e.g., 535, 540) to simultaneously implement and support multiple protocols, [0062]); converting, by the target interface converter, the data request from the first protocol into a streaming protocol (UCIe also defines a “streaming protocol” which can be used to map any other protocol onto the flit format(s), [0073]); selecting, by a protocol arbiter of the protocol handler, the data request for transmission (an arbitration and multiplexer layer (e.g., 520) may be provided, [0062]; perform arbitration/multiplexing of the multiple sub-protocols of CXL, [0077]; fig. 4, 455a-b); and serializing, by a link layer of the SSBI, the data request (Link layer, [0044-0045]; link layer logic, [0058]; UCIe raw mode is protocol-agnostic and enables other protocols to be mapped ad hoc by a device, while allowing usages such as integrating a stand-alone SERDES/transceiver tile, [0068]).
While Da Sharma depicts the link layer for data connections in both the source and target direction (fig. 2 and 5; Data Link Layer 210 to carry the information from the transmitting component to the…At the receiving side the reverse process occurs, [0040]) and teaches the use of a clock and data pin (clock pin and a data pin in each direction, [0079]), Da Sharma does not appear to explicitly depict the link layer architecture comprising the data connection and the clock connection indicates there is valid data to sample per cycle. Additionally, while Das Sharmar teaches a SERDES/transceiver configured to serialize data to be transmitted based on a credit-based flow control (a stand-alone SERDES/transceiver tile, [0068]; data transmitted from a UCIe die to a UCIe retimer may be flow-controlled using credits, [0082-0083]), Das Sharma does not describe the transceiver in terms of separate transmission finite state machine (TX FSM). As well, while Das Sharma teaches transmissions consume credits and responses restore credits, which in view of the teaching of a SERDES/transceivers would involve being “available to serialize data” and “serializing data”, Das Sharma does not appear to explicitly disclose the credit flow in terms of credits exchanged by the transmitter in the manner that the transmit side “contains a credit when available to serialize data and does not contain the credit when serializing data.”
However, Schultz discloses the link layer of link layer architecture comprising the data connection and the clock connection indicates there is valid data to sample per cycle (fig. 8, The link layer circuitry 824 receives the clock signal 841 and the data signal 813. The link layer circuitry 824 generates a framing pattern from the data signal 813. Further, the link layer circuitry 824 generates the data signal 825 based on the clock signal 841. In one example, the data signal 813 is transmitted with a framing signal. The framing signal defines areas of valid data within the data signal 813. In one example, the framing signal is used to mask out invalid data within the data signal 813, [0152], [0157-0158]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma and Schultz before him or her, to modify the interconnect system of Das Sharma to include the link layer clock and data connections of Schultz because the prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference; one of ordinary skill in the art could have combined the elements as claimed by known methods, and in combination, the combined data and clock elements merely perform the same function as they do separately; and one of ordinary skill in the art would have recognized that the results of the combination were predictable interconnection configuration and control architecture.
The rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. KSR, 550 U.S. at 416, 82 USPQ2d at 1395 (see MPEP 2143.I.A).
Furthermore, Raupp teaches a transmitting and receiving architecture in which the transmitter and receiver are designed in the form of hardware blocks forming finite-state machines (see [0116]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma and Raupp before him or her, to implement the SERDES/transceiver architecture anticipated by Das Sharma as the separate FSMs as taught by Raupp because Das Sharma demonstrates the prior art contained a device (method, product, etc.) which differed from the claimed device by the substitution of the anticipated SERDES/transceiver architecture with a specific FMS arrangement; Raupp demonstrates the substituted TX and RX FSM were known in the art and provide the same functions of transmitting, receiving, serializing, and deserializing; and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable transmitting and receiving architecture for serial communications.
Finally, Aingaran teaches a credit-based flow control which exchanges credits between a transmitter and a receiver ([0030], [0044], [0049]), which in combination with the SERDES of Das Sharma and FMS architecture of Raupp, teaches each element of the limitations “wherein the TX FSM contains a credit when available to serialize data and does not contain the credit when serializing data.”
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma, Raupp, and Aingaran before him or her, to implement the credit-based flow control anticipated by Das Sharma in view of Raupp according to the credit exchange scheme taught by Aingaran because Das Sharma demonstrates the prior art contained a device (method, product, etc.) which differed from the claimed device by the substitution of the anticipated credit-based flow control with a specific credit exchange scheme; Aingaran demonstrates the substituted credit exchange scheme was known in the art and provide the same flow control capability; and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable flow control between transmitters and receivers.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (see MPEP 2143.I.B).
Das Sharma, Raupp, Aingaran, and Schultz are analogous art because they are from the same field of endeavor, managing interconnect fabric communications, and therefore, it would have been obvious to combine Das Sharma, Raupp, Aingaran, and Schultz to obtain the invention as specified in the instant claim.
As to claim 15, Das Sharma discloses receiving, by a target initiator converter of the protocol handler, a data response in the first protocol; converting, by the target initiator converter, the data response from the first protocol into the streaming protocol (At the receiving side the reverse process occurs and packets get transformed from their Physical Layer 220 representation to the Data Link Layer 210 representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer 205 of the receiving device, [0040]; a protocol may implement split transactions, i.e. transactions with request and response separated by time, [0042]; UCIe also defines a “streaming protocol” which can be used to map any other protocol onto the flit format(s), [0073]); selecting, by the protocol arbiter, the data response for transmission (arbitration framework for arbitrating between data of the multiple protocols on the link, [0025]); and serializing the data response (Link layer, [0044-0045]; link layer logic, [0058]; UCIe raw mode is protocol-agnostic and enables other protocols to be mapped ad hoc by a device, while allowing usages such as integrating a stand-alone SERDES/transceiver tile, [0068]).
While Da Sharma depicts the link layer for data connections in both the source and target direction (fig. 2 and 5; Data Link Layer 210 to carry the information from the transmitting component to the…At the receiving side the reverse process occurs, [0040]) and teaches the use of a clock and data pin (clock pin and a data pin in each direction, [0079]), Da Sharma does not appear to explicitly depict the link layer architecture comprising the data connection and the clock connection indicates there is valid data to sample per cycle. Additionally, while Das Sharmar teaches a SERDES/transceiver configured to serialize data to be transmitted based on a credit-based flow control (a stand-alone SERDES/transceiver tile, [0068]; data transmitted from a UCIe die to a UCIe retimer may be flow-controlled using credits, [0082-0083]), Das Sharma does not describe the transceiver in terms of a separate transmission finite state machine (TX FSM).
However, Schultz discloses the link layer of link layer architecture comprising the data connection and the clock connection indicates there is valid data to sample per cycle (fig. 8, The link layer circuitry 824 receives the clock signal 841 and the data signal 813. The link layer circuitry 824 generates a framing pattern from the data signal 813. Further, the link layer circuitry 824 generates the data signal 825 based on the clock signal 841. In one example, the data signal 813 is transmitted with a framing signal. The framing signal defines areas of valid data within the data signal 813. In one example, the framing signal is used to mask out invalid data within the data signal 813, [0152], [0157-0158]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma and Schultz before him or her, to modify the interconnect system of Das Sharma to include the link layer clock and data connections of Schultz because the prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference; one of ordinary skill in the art could have combined the elements as claimed by known methods, and in combination, the combined data and clock elements merely perform the same function as they do separately; and one of ordinary skill in the art would have recognized that the results of the combination were predictable interconnection configuration and control architecture.
The rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. KSR, 550 U.S. at 416, 82 USPQ2d at 1395 (see MPEP 2143.I.A).
Furthermore, Raupp teaches a transmitting and receiving architecture in which the transmitter and receiver are designed in the form of hardware blocks forming finite-state machines (see [0116]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma and Raupp before him or her, to implement the SERDES/transceiver architecture anticipated by Das Sharma as the separate FSMs as taught by Raupp because Das Sharma demonstrates the prior art contained a device (method, product, etc.) which differed from the claimed device by the substitution of the anticipated SERDES/transceiver architecture with a specific FMS arrangement; Raupp demonstrates the substituted TX and RX FSM were known in the art and provide the same functions of transmitting, receiving, serializing, and deserializing; and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable transmitting and receiving architecture for serial communications.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (see MPEP 2143.I.B).
Das Sharma, Raupp, Aingaran, and Schultz are analogous art because they are from the same field of endeavor, managing interconnect fabric communications, and therefore, it would have been obvious to combine Das Sharma, Raupp, Aingaran, and Schultz to obtain the invention as specified in the instant claim.
Referring to claim 18, Das Sharma discloses a method for receiving data via a side sideband interface (SSBI) (UCIe , [0068]; sideband connection, [0079]) comprising: deserializing, by a link layer of the SSBI a data response (transactions with request and response, [0042]; UCIe raw mode is protocol-agnostic and enables other protocols to be mapped ad hoc by a device, while allowing usages such as integrating a stand-alone SERDES/transceiver tile, [0068]); distributing, by a protocol demultiplexer of a protocol handler of the SSBI (perform arbitration/multiplexing of the multiple sub-protocols of CXL, [0077]; fig. 4, 455a-b), the data response based on a transaction protocol of the data response (a protocol may implement split transactions, i.e. transactions with request and response, [0042]); converting, by a target interface converter of the protocol handler, the data response from a streaming protocol into a first protocol; and outputting, by the target interface converter, the data response in the first protocol (A protocol may use packets to communicate information between components. Packets are formed…At the receiving side the reverse process occurs and packets get transformed …and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer 205 of the receiving device, [0040]).
While Da Sharma depicts the link layer for data connections in both the source and target direction (fig. 2 and 5; Data Link Layer 210 to carry the information from the transmitting component to the…At the receiving side the reverse process occurs, [0040]) and teaches the use of a clock and data pin (clock pin and a data pin in each direction, [0079]), Da Sharma does not appear to explicitly depict the link layer architecture comprising the data connection signaling bit by bit and the clock connection indicates there is valid data to sample per cycle. Additionally, while Das Sharmar teaches a SERDES/transceiver configured to deserialize data to be received based on a credit-based flow control (a stand-alone SERDES/transceiver tile, [0068]; data transmitted from a UCIe die to a UCIe retimer may be flow-controlled using credits, [0082-0083]), Das Sharma does not describe the transceiver in terms of a separate receiver finite state machine (RX FSM). As well, while Das Sharma teaches transmissions consume credits and responses restore credits, which in view of the teaching of a SERDES/transceivers would involve “when deserializing data” and “when available to deserialize data”, Das Sharma does not appear to explicitly disclose the credit flow in terms of credits exchanged by the receiver in the manner that the receiver side “contains a credit when deserializing data and does not contain the credit when available to deserializing data.”
However, Schultz discloses the link layer of link layer architecture comprising the data connection signaling bit by bit and the clock connection indicates there is valid data to sample per cycle (fig. 8, The link layer circuitry 824 receives the clock signal 841 and the data signal 813. The link layer circuitry 824 generates a framing pattern from the data signal 813. Further, the link layer circuitry 824 generates the data signal 825 based on the clock signal 841. In one example, the data signal 813 is transmitted with a framing signal. The framing signal defines areas of valid data within the data signal 813. In one example, the framing signal is used to mask out invalid data within the data signal 813, [0152], [0157-0158]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma and Schultz before him or her, to modify the interconnect system of Das Sharma to include the link layer clock and data connections of Becht because the prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference; one of ordinary skill in the art could have combined the elements as claimed by known methods, and in combination, the combined data and clock elements merely perform the same function as they do separately; and one of ordinary skill in the art would have recognized that the results of the combination were predictable interconnection configuration and control architecture.
The rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. KSR, 550 U.S. at 416, 82 USPQ2d at 1395 (see MPEP 2143.I.A).
Furthermore, Raupp teaches a transmitting and receiving architecture in which the transmitter and receiver are designed in the form of hardware blocks forming finite-state machines (see [0116]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma and Raupp before him or her, to implement the SERDES/transceiver architecture anticipated by Das Sharma as the separate FSMs as taught by Raupp because Das Sharma demonstrates the prior art contained a device (method, product, etc.) which differed from the claimed device by the substitution of the anticipated SERDES/transceiver architecture with a specific FMS arrangement; Raupp demonstrates the substituted TX and RX FSM were known in the art and provide the same functions of transmitting, receiving, serializing, and deserializing; and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable transmitting and receiving architecture for serial communications.
Finally, Aingaran teaches a credit-based flow control which exchanges credits between a transmitter and a receiver ([0030], [0044], [0049]), which in combination with the SERDES of Das Sharma and FMS architecture of Raupp, teaches each element of the limitations “wherein the RX FSM contains a credit when deserializing data and does not contain the credit when available to deserialize data.”
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma, Raupp, and Aingaran before him or her, to implement the credit-based flow control anticipated by Das Sharma in view of Raupp according to the credit exchange scheme taught by Aingaran because Das Sharma demonstrates the prior art contained a device (method, product, etc.) which differed from the claimed device by the substitution of the anticipated credit-based flow control with a specific credit exchange scheme; Aingaran demonstrates the substituted credit exchange scheme was known in the art and provide the same flow control capability; and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable flow control between transmitters and receivers.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (see MPEP 2143.I.B).
Das Sharma, Raupp, Aingaran, and Schultz are analogous art because they are from the same field of endeavor, managing interconnect fabric communications, and therefore, it would have been obvious to combine Das Sharma, Raupp, Aingaran, and Schultz to obtain the invention as specified in the instant claim.
As to claim 19, Das Sharma discloses deserializing a data request; distributing, by the protocol demultiplexer (perform arbitration/multiplexing of the multiple sub-protocols of CXL, [0077]; fig. 4, 455a-b), the data request based on a transaction protocol of the data request (transactions with request and response, [0042]; UCIe raw mode is protocol-agnostic and enables other protocols to be mapped ad hoc by a device, while allowing usages such as integrating a stand-alone SERDES/transceiver tile, [0068]); converting, by an initiator interface converter of the protocol handler, the data request from the streaming protocol into the first protocol; and outputting, by the initiator interface converter, the data request in the first protocol (A protocol may use packets to communicate information between components. Packets are formed…At the receiving side the reverse process occurs and packets get transformed …and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer 205 of the receiving device, [0040]).
While Da Sharma depicts the link layer for data connections in both the source and target direction (fig. 2 and 5; Data Link Layer 210 to carry the information from the transmitting component to the…At the receiving side the reverse process occurs, [0040]) and teaches the use of a clock and data pin (clock pin and a data pin in each direction, [0079]), Da Sharma does not appear to explicitly depict the link layer architecture comprising the data connection signaling bit by bit and the clock connection indicates there is valid data to sample per cycle. Additionally, while Das Sharmar teaches a SERDES/transceiver configured to serialize data to be transmitted based on a credit-based flow control (a stand-alone SERDES/transceiver tile, [0068]; data transmitted from a UCIe die to a UCIe retimer may be flow-controlled using credits, [0082-0083]), Das Sharma does not describe the transceiver in terms of a separate receiver finite state machine (TX FSM).
However, Schultz discloses the link layer of link layer architecture comprising the data connection signaling bit by bit and the clock connection indicates there is valid data to sample per cycle (fig. 8, The link layer circuitry 824 receives the clock signal 841 and the data signal 813. The link layer circuitry 824 generates a framing pattern from the data signal 813. Further, the link layer circuitry 824 generates the data signal 825 based on the clock signal 841. In one example, the data signal 813 is transmitted with a framing signal. The framing signal defines areas of valid data within the data signal 813. In one example, the framing signal is used to mask out invalid data within the data signal 813, [0152], [0157-0158]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma and Schultz before him or her, to modify the interconnect system of Das Sharma to include the link layer clock and data connections of Becht because the prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference; one of ordinary skill in the art could have combined the elements as claimed by known methods, and in combination, the combined data and clock elements merely perform the same function as they do separately; and one of ordinary skill in the art would have recognized that the results of the combination were predictable interconnection configuration and control architecture.
The rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. KSR, 550 U.S. at 416, 82 USPQ2d at 1395 (see MPEP 2143.I.A).
Furthermore, Raupp teaches a transmitting and receiving architecture in which the transmitter and receiver are designed in the form of hardware blocks forming finite-state machines (see [0116]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma and Raupp before him or her, to implement the SERDES/transceiver architecture anticipated by Das Sharma as the separate FSMs as taught by Raupp because Das Sharma demonstrates the prior art contained a device (method, product, etc.) which differed from the claimed device by the substitution of the anticipated SERDES/transceiver architecture with a specific FMS arrangement; Raupp demonstrates the substituted TX and RX FSM were known in the art and provide the same functions of transmitting, receiving, serializing, and deserializing; and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable transmitting and receiving architecture for serial communications.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (see MPEP 2143.I.B).
Das Sharma, Raupp, Aingaran, and Schultz are analogous art because they are from the same field of endeavor, managing interconnect fabric communications, and therefore, it would have been obvious to combine Das Sharma, Raupp, Aingaran, and Schultz to obtain the invention as specified in the instant claim.
Claim 16-17 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Das Sharma, Raupp, Aingaran, and Schultz as applied to claims 14-15 and 18-19 above, further in view of Jin.
As to claim 16, while Das Sharma teaches the target interface converter and is concerned with “when the data response is not received within a predetermined amount of time” (make sure the different UCIe die are in sync and do not timeout waiting for a response, [0100]), Das Sharma does not appear to specifically handle timeouts by triggering “a timeout error”
However, Jin teaches a triggering a timeout error (an interrupt signal in response to the occurrence of a transaction timeout, [0072]).
Das Sharma, Raupp, Aingaran, Schultz, and Jin are analogous art because they are from the same field of endeavor, managing interconnect fabric communications.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma, Raupp, Aingaran, Schultz, and Jin before him or her, to modify the interconnect system of Das Sharma to include the interrupt of Jin in order to signal a transaction timeout.
The suggestion/motivation for doing so would have been to identify operating issues for corrective action (Jin: [0056]).
Therefore, it would have been obvious to combine Das Sharma, Raupp, Aingaran, Schultz, and Jin to obtain the invention as specified in the instant claim.
As to claim 17, as demonstrated above, the combination of Das Sharma, Raupp, Aingaran, and Schultz teaches the instance when the TX FSM does not contain the credit, and while both Das Sharma and Aingaran consider instances “when the TX FSM does not contain the credit for a predetermined amount of time” (Das Sharma: make sure the different UCIe die are in sync and do not timeout waiting for a response, [0100]; Aingaran: any time sender…is awaiting a response from the receiver, [0068]), the combination does not appear to specifically handle timeouts by triggering a timeout error.
However, Jin teaches a triggering a timeout error (an interrupt signal in response to the occurrence of a transaction timeout, [0072]).
Das Sharma, Raupp, Aingaran, Schultz, and Jin are analogous art because they are from the same field of endeavor, managing interconnect fabric communications.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma, Raupp, Aingaran, Schultz, and Jin before him or her, to modify the interconnect system of Das Sharma to include the interrupt of Jin in order to signal a transaction timeout.
The suggestion/motivation for doing so would have been to identify operating issues for corrective action (Jin: [0056]).
Therefore, it would have been obvious to combine Das Sharma, Raupp, Aingaran, Schultz, and Jin to obtain the invention as specified in the instant claim.
As to claim 20, as demonstrated above, the combination of Das Sharma, Raupp, Aingaran, and Schultz teaches the RX FSM and deserializing the data response (Das Sharma: a protocol may implement split transactions, i.e. transactions with request and response, [0042]); UCIe raw mode is protocol-agnostic and enables other protocols to be mapped ad hoc by a device, while allowing usages such as integrating a stand-alone SERDES/transceiver tile, [0068]) and is concerned with processing data responses “within a predetermined amount of time” (Das Sharma: make sure the different UCIe die are in sync and do not timeout waiting for a response, [0100]; Aingaran: any time sender…is awaiting a response from the receiver, [0068]), the combination does not appear to specifically handle timeouts by triggering a timeout error.
However, Jin teaches a triggering a timeout error (an interrupt signal in response to the occurrence of a transaction timeout, [0072]).
Das Sharma, Raupp, Aingaran, Schultz, and Jin are analogous art because they are from the same field of endeavor, managing interconnect fabric communications.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma, Raupp, Aingaran, Schultz, and Jin before him or her, to modify the interconnect system of Das Sharma to include the interrupt of Jin in order to signal a transaction timeout.
The suggestion/motivation for doing so would have been to identify operating issues for corrective action (Jin: [0056]).
Therefore, it would have been obvious to combine Das Sharma, Raupp, Aingaran, Schultz, and Jin to obtain the invention as specified in the instant claim.
As to claim 21, as demonstrated above, the combination of Das Sharma, Raupp, Aingaran, and Schultz teaches a TX FSM of the link layer and the RX FSM (Link layer, [0044-0045]; link layer logic, [0058]; a protocol may implement split transactions, i.e. transactions with request and response, [0042]; UCIe raw mode is protocol-agnostic and enables other protocols to be mapped ad hoc by a device, while allowing usages such as integrating a stand-alone SERDES/transceiver tile, [0068]), and is concerned with “a timeout” (required to not send any data to the UCIe retimer if it does not have a credit for the transmission, [0083]; make sure the different UCIe die are in sync and do not timeout waiting for a response, [0100]), Das Sharma does not appear to specifically handle timeouts by triggering a timeout error.
However, Jin teaches a triggering a timeout error (an interrupt signal in response to the occurrence of a transaction timeout, [0072]).
Das Sharma, Raupp, Aingaran, Schultz, and Jin are analogous art because they are from the same field of endeavor, managing interconnect fabric communications.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma, Raupp, Aingaran, Schultz, and Jin before him or her, to modify the interconnect system of Das Sharma to include the interrupt of Jin in order to signal a transaction timeout.
The suggestion/motivation for doing so would have been to identify operating issues for corrective action (Jin: [0056]).
Therefore, it would have been obvious to combine Das Sharma, Raupp, Aingaran, Schultz, and Jin to obtain the invention as specified in the instant claim.
Response to Arguments
Applicant's arguments filed 5/7/2026 have been fully considered but they moot in view of the new grounds of rejection necessitated by the amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The examiner has cited particular column, line, and/or paragraph numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in its entirety as potentially teaching of all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T OBERLY whose telephone number is (571)272-6991. The examiner can normally be reached on M-F 800am-430pm (MT).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC T OBERLY/ Primary Examiner, Art Unit 2184
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