Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: FIG. 2: 222. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5, 9, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 6,201,753 B1 (Akaogi, et al., hereinafter Akaogi) in view of US 6,876,558 (James, et al., hereinafter James).
Regarding claim 1, Akaogi teaches a memory device (Akaogi, FIG. 1-6), comprising: a memory array (“flash memory array”) comprising memory banks; (Akaogi, {3}: “It will be appreciated that while the exemplary devices have two banks of memory cells, devices with more than two banks are contemplated…memory array Banks 0 and 1 denoted as 194 and 196 respectively…”) and a peripheral circuit coupled to the memory array, the peripheral circuit comprising: (“Akaogi, “content addressable memory (CAM) circuit 200”; “FIG. 2 is a prior art content addressable memory (CAM) circuit 200 for storing operational and timing data in the flash memory chip 100 of FIG. 1.”) content addressable memories (CAMs); (Akaogi, “content addressable memory (CAM) cell”; “CAM cell 202) a data path; (Akaogi, FIG. 2; “two input address paths and two output data paths”…”For controlling the data stored in the CAM cell 202…”).
However, although Akaogi teaches multiplexers coupled to storage, Akaogi does not appear to explicitly teach a buffer circuit coupled to the CAMs through the data path, wherein the buffer circuit comprises a multiplexer coupled to a storage unit and a command/address (CA) interface, and the multiplexer is configured to select either the storage unit or the CA interface.
James cures the deficiencies of Akaogi. James (FIG. 1-5B) teaches a buffer circuit coupled to the CAMs through the data path, (James, (24): “According to another aspect of the embodiments, a CAM device may also include two or more first-in-first-out buffer circuits (FIFO).”) wherein the buffer circuit comprises a multiplexer coupled to a storage unit and a command/address (CA) interface, and the multiplexer is configured to select either the storage unit or the CA interface. (James: “(27) According to another aspect of the embodiments, a CAM device may also include a select multiplexer having one input coupled to an input data path and another input coupled to the CAM array.”)
Akaogi and James are both directed to methods and apparatus for content addressable memory loading in semiconductor devices and managing the memory of the same. One of ordinary skill in the art would find it obvious to modify the teachings of Akaogi with the buffer circuit and select multiplexer as described in James with the motivation of adding functionality to the memory device and for improving efficiency of resource utilization related to a content addressable memory device.
Regarding claim 3, Akaogi/James teaches the memory device of claim 1, wherein the multiplexer is coupled to the CA interface through a control circuit, (James, (3-5), col. 1, lines 37-48: “Referring now to FIG. 8, a conventional CAM device 800 will be described in more detail. A conventional CAM device 800 may include a CAM array 802, CAM control circuits 804, and CAM register 806… A CAM control circuit 804 can take CAM control signals as inputs and generate signals that may control the operation of a CAM array 802 and/or registers 806. Registers 806 can include a number of storage locations that may store key and other values used for search and other operations.”) and the control circuit comprises an address and bank decoder (James, col. 10, lines 63-67: “Accordingly, a scheduler 556 may generate control signals that are decoded by control signal decoder 558 to enable signal EN0. This can allow request data from FIFO circuit 564-0 to be output on MUX output 568.”) and a control logic comprising a command decoder. (James, “A command decoder 614 may receive command information from a request received on an input data path 608.”)
Regarding claim 5, Akaogi/James teaches the memory device of claim 1, wherein the CAMs are in a row address decoder of the peripheral circuit. (Akaogi, FIG. 1-6; col. 5, lines 45-49: “The memory device 100 further includes address buffer 104, address multiplexers 106 and 108, address sequencer 110, X logical address decoders 112 and 118, Y logical address decoders 114 and 120,”)
Regarding claim 9, Akaogi/James teaches the memory device of claim 1, wherein the memory device is a dynamic random access memory (DRAM) device, and at least one memory bank of the memory banks comprises DRAM cells. (James, (3): “Such storage circuits may be static random access memory (SRAM) type cells or dynamic random access memory (DRAM) type cells, for example.”)
Regarding claim 20, Akaogi teaches a memory system, (Akaogi, FIG. 1-6) comprising a memory device and a memory controller coupled to the memory device, wherein the memory device comprises: a memory array (“flash memory array”) comprising memory banks; (Akaogi, {3}: “It will be appreciated that while the exemplary devices have two banks of memory cells, devices with more than two banks are contemplated…memory array Banks 0 and 1 denoted as 194 and 196 respectively…”) and a peripheral circuit coupled to the memory array, the peripheral circuit comprising: (“Akaogi, “content addressable memory (CAM) circuit 200”; “FIG. 2 is a prior art content addressable memory (CAM) circuit 200 for storing operational and timing data in the flash memory chip 100 of FIG. 1.”) content addressable memories (CAMs); (Akaogi, “content addressable memory (CAM) cell”; “CAM cell 202) a data path; (Akaogi, FIG. 2; “two input address paths and two output data paths”…”For controlling the data stored in the CAM cell 202…”).
However, although Akaogi teaches multiplexers coupled to storage, Akaogi does not appear to explicitly teach and a buffer circuit coupled to the CAMs through the data path, wherein the buffer circuit comprises a multiplexer coupled to a storage unit and a command/address (CA) interface, and the multiplexer is configured to select either the storage unit or the CA interface.
James cures the deficiencies of Akaogi. James (FIG. 1-5B) teaches a buffer circuit coupled to the CAMs through the data path, (James, (24): “According to another aspect of the embodiments, a CAM device may also include two or more first-in-first-out buffer circuits (FIFO).”) wherein the buffer circuit comprises a multiplexer coupled to a storage unit and a command/address (CA) interface, and the multiplexer is configured to select either the storage unit or the CA interface. (James: “(27) According to another aspect of the embodiments, a CAM device may also include a select multiplexer having one input coupled to an input data path and another input coupled to the CAM array.”)
Akaogi and James are both directed to methods and apparatus for content addressable memory loading in semiconductor devices and managing the memory of the same. One of ordinary skill in the art would find it obvious to modify the teachings of Akaogi with the buffer circuit and select multiplexer as described in James with the motivation of adding functionality to the memory device and for improving efficiency of resource utilization related to a content addressable memory device.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 6,201,753 B1 (Akaogi, et al., hereinafter Akaogi) in view of US 6,876,558 (James, et al., hereinafter James) in view of US 20230377672 (Cho).
Regarding claim 4, Akaogi/James teaches the memory device of claim 1, but does not appear to teach wherein the storage unit is a one-time programmable (OTP) memory configured to store defective row addresses.
Cho cures the deficiencies of Akaogi/James. Cho teaches wherein the storage unit is a one-time programmable (OTP) memory configured to store defective row addresses. (Cho, [0007]: “According to example embodiments, a semiconductor memory device includes a memory cell array, an OTP memory device, an address comparator and a repair address generator. The memory cell array includes a plurality of memory cell rows and each of the plurality of memory cell rows includes a plurality of memory cells. The OTP memory device is configured to store at least one defective address of at least one defective memory cell row including an uncorrectable error that is determined based on testing the plurality of memory cell rows.”)
Akaogi/James and Cho are both directed to semiconductor memory devices and managing the memory of the same. One of ordinary skill in the art would find it obvious to modify the teachings of Akaogi/James with the OTP memory device for storing a defective address of Cho with the motivation of adding functionality to the memory device and for improving reliability and usability.
Claim(s) 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 6,201,753 B1 (Akaogi, et al., hereinafter Akaogi) in view of US 6,876,558 (James, et al., hereinafter James) in view of US 20040120174 A1 (Regev A and Regev Z, hereinafter Regev).
Regarding claim 6, Akaogi/James teaches the memory device of claim 1, but does not appear to teach wherein the peripheral circuit further comprises a shift register coupled to the CAMs.
Regev cures the deficiencies of Akaogi/James. Regev teaches wherein the peripheral circuit further comprises a shift register coupled to the CAMs. (Regev, [0009]: “The present invention provides a recirculating shift register used to store data in the memory storage locations of the CAM, which has a single match circuit at a predetermined bit location.”)
Akaogi/James and Regev are both directed to content addressable memory devices and managing the memory of the same. One of ordinary skill in the art would find it obvious to modify the teachings of Akaogi/James with the shift register for data storage of Regev with the motivation of improving functionality of the device as it relates to storing data at memory storage locations in a CAM device.
Regarding claim 7, Akaogi/James/Regev teaches the memory device of claim 6, wherein the shift register comprises multiple bit storage units, each of the multiple bit storage units is coupled to a respective CAM of the CAMs (Regev, [0019]: “in the CAM of the present invention described herein, each memory storage location in the memory array and the comparand, is constructed of dynamic master/slave flip-flops forming a recirculating serial shift register. The flip-flops work in a “bucket brigade” fashion, wherein an electrical signal is transferred from one stage of the register to the next throughout the register. Each CAM memory storage location has an output at one end of the shift register connected to the input of the shift register.”) and is configured to enable writing data into the respective CAM. (Regev, [0023]: “For a write operation a selected multiplexer receives input data from the write data line 121 and serially loads it into the associated memory storage location to which the selected multiplexer is coupled.”)
Regarding claim 8, Akaogi/James/Regev teaches the memory device of claim 6, wherein the CAMs are coupled to the shift register through CAM selection lines. (Regev, FIG. 1-6; Regev, [0023]: “Data is written into a CAM memory storage location via the multiplexer 110a . . . 110n coupled to a particular CAM memory storage location selected based on the word select line 118.”)
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 6,201,753 B1 (Akaogi, et al., hereinafter Akaogi) in view of US 6,876,558 (James, et al., hereinafter James) in view of US 20110149627 (Kang).
Regarding claim 10, Akaogi/James teaches the memory device of claim 1, but does not appear to explicitly teach wherein the peripheral circuit is configured to: load data from the storage unit to the CAMs in a power on reset process of the memory device.
Kang cures the deficiencies of Akaogi/James. Kang teaches wherein the peripheral circuit is configured to: load data from the storage unit to the CAMs in a power on reset process of the memory device. (Kang, [0007]: “The nonvolatile memory device storing the option information in the CAM cell requires an operation of loading data stored in the CAM cell during a reset operation and storing the loaded data in an internal register after a power-on operation. The operation of loading the data of the CAM cell is performed when a voltage level is stabilized to some extent after supplying a power source.”)
Akaogi/James and Kang are both directed to content addressable memory devices and managing the memory of the same. One of ordinary skill in the art would find it obvious to modify the teachings of Akaogi/James with the loading of data to the CAMs in a reset process with the motivation of improving functionality of the device as it relates to storing data at memory storage locations in a CAM device.
Claim(s) 12-13 and 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Akaogi in view of James.
Regarding claim 12, Kang teaches a method of operating a memory device, (Kang, FIG. 1-3) comprising: loading, by a peripheral circuit (Kang, “peripheral circuit”) of the memory device, data from a storage unit to content addressable memories (CAMs) through a buffer circuit and a data path, (Kang, [0007]: “The nonvolatile memory device storing the option information in the CAM cell requires an operation of loading data stored in the CAM cell during a reset operation and storing the loaded data in an internal register after a power-on operation. The operation of loading the data of the CAM cell is performed when a voltage level is stabilized to some extent after supplying a power source.”).
Kang does not appear to explicitly set forth wherein the peripheral circuit comprises the CAMs, the buffer circuit, and the data path, and the buffer circuit comprises a multiplexer coupled to the storage unit; and receiving, by the peripheral circuit, an address from a command/address (CA) interface through the buffer circuit and the data path, wherein the CA interface is coupled to the multiplexer.
Akaogi teaches wherein the peripheral circuit (“Akaogi, “content addressable memory (CAM) circuit 200”; “FIG. 2 is a prior art content addressable memory (CAM) circuit 200 for storing operational and timing data in the flash memory chip 100 of FIG. 1.”) comprises the CAMs, (Akaogi, “content addressable memory (CAM) cell”; “CAM cell 202) and the data path, (Akaogi, FIG. 2; “two input address paths and two output data paths”…”For controlling the data stored in the CAM cell 202…”). Kang and Akaogi are both directed to content addressable memory devices and managing the memory of the same. One of ordinary skill in the art would find it obvious to modify the teachings of Kang with the peripheral circuitry as described in Akaogi with the motivation of improving functionality of the memory device.
Kang/Akaogi does not appear to explicitly teach wherein the peripheral circuit includes the buffer circuit, and the buffer circuit comprises a multiplexer coupled to the storage unit; and receiving, by the peripheral circuit, an address from a command/address (CA) interface through the buffer circuit and the data path, wherein the CA interface is coupled to the multiplexer.
James cures the deficiencies of Kang/Akaogi. James (FIG. 1-5B) teaches wherein the peripheral circuit includes the buffer circuit, (James, (24): “According to another aspect of the embodiments, a CAM device may also include two or more first-in-first-out buffer circuits (FIFO).”) and the buffer circuit comprises a multiplexer coupled to the storage unit; and receiving, by the peripheral circuit, an address from a command/address (CA) interface through the buffer circuit and the data path, wherein the CA interface is coupled to the multiplexer. (James, FIG. 1-5B; James: “(27) According to another aspect of the embodiments, a CAM device may also include a select multiplexer having one input coupled to an input data path and another input coupled to the CAM array.”)
Kang/Akaogi and James are directed to content addressable memory devices and managing the memory of the same. One of ordinary skill in the art would find it obvious to modify the teachings of Kang/Akaogi with the buffer circuit and select multiplexer as described in James with the motivation of adding functionality to the memory device and for improving efficiency of resource utilization related to a content addressable memory device.
Regarding claim 13, Kang/Akaogi/James teaches the method of claim 12, further comprising: comparing the address to the data loaded to the CAMs. (James, col. 1, lines 56-64: “Having described an example of a CAM device, a conventional CAM search operation will now be described. To perform a search operation, a device such as a network processing unit (NPU), may provide a search command to a CAM device 800 on a data/control bus 808. Such a command may include a key value that can be compared to all or a portion of CAM entries within a CAM array 802.”)
Regarding claim 15, Kang/Akaogi/James teaches the method of claim 12, wherein loading the data from the storage unit to the CAMs comprises: controlling the multiplexer to select the storage unit and forward the data from the storage unit to the data path. (Kang, [0007]: “The nonvolatile memory device storing the option information in the CAM cell requires an operation of loading data stored in the CAM cell during a reset operation and storing the loaded data in an internal register after a power-on operation. The operation of loading the data of the CAM cell is performed when a voltage level is stabilized to some extent after supplying a power source.”)
Regarding claim 16, Kang/Akaogi/James teaches the method of claim 12, wherein loading the data from the storage unit to the CAMs comprises: loading the data from the storage unit to the CAMs in a power on reset process of the memory device. (Kang, [0007]: “The nonvolatile memory device storing the option information in the CAM cell requires an operation of loading data stored in the CAM cell during a reset operation and storing the loaded data in an internal register after a power-on operation. The operation of loading the data of the CAM cell is performed when a voltage level is stabilized to some extent after supplying a power source.”)
Regarding claim 17, Kang/Akaogi/James teaches the method of claim 12, wherein receiving the address from the CA interface comprises: controlling the multiplexer to select the CA interface and forward the address to the data path. (James: “(27) According to another aspect of the embodiments, a CAM device may also include a select multiplexer having one input coupled to an input data path and another input coupled to the CAM array.”)
Regarding claim 18, Kang/Akaogi/James teaches the method of claim 12, wherein receiving the address from the CA interface comprises: receiving the address from the CA interface after a power on reset process of the memory device. (Kang, [0007]: “The nonvolatile memory device storing the option information in the CAM cell requires an operation of loading data stored in the CAM cell during a reset operation and storing the loaded data in an internal register after a power-on operation. The operation of loading the data of the CAM cell is performed when a voltage level is stabilized to some extent after supplying a power source.”)
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Akaogi in view of James in view of Cho.
Regarding claim 19, Kang/Akaogi/James teaches the method of claim 12, but does not appear to explicitly teach wherein the storage unit is a one-time programmable (OTP) memory configured to store defective row addresses.
Cho cures the deficiencies of Kang/Akaogi/James. Cho teaches wherein the storage unit is a one-time programmable (OTP) memory configured to store defective row addresses. (Cho, [0007]: “According to example embodiments, a semiconductor memory device includes a memory cell array, an OTP memory device, an address comparator and a repair address generator. The memory cell array includes a plurality of memory cell rows and each of the plurality of memory cell rows includes a plurality of memory cells. The OTP memory device is configured to store at least one defective address of at least one defective memory cell row including an uncorrectable error that is determined based on testing the plurality of memory cell rows.”)
Kang/Akaogi/James and Cho are both directed to semiconductor memory devices and managing the memory of the same. One of ordinary skill in the art would find it obvious to modify the teachings of Kang/Akaogi/James with the OTP memory device for storing a defective address of Cho with the motivation of adding functionality to the memory device and for improving reliability and usability.
Allowable Subject Matter
Claims 2, 11, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, Akaogi/James teaches the memory device of claim 1, but does not appear to teach wherein the buffer circuit further comprises a buffer coupled between the data path and the multiplexer, and the multiplexer comprises a first input coupled to the CA interface, a second input coupled to the storage unit, and an output coupled to the buffer. Although the prior art of record teaches several of the components of the claim language, it is silent towards this configuration of the buffer circuit, and such configuration in combination with claim 1 does not appear to be taught by the prior art of record, and does not appear to be obvious to one of ordinary skill in the art.
Therefore, regarding claim 2, the prior art of record does not appear to teach a memory device, comprising: a memory array comprising memory banks; and a peripheral circuit coupled to the memory array, the peripheral circuit comprising: content addressable memories (CAMs); a data path; and a buffer circuit coupled to the CAMs through the data path, wherein the buffer circuit comprises a multiplexer coupled to a storage unit and a command/address (CA) interface, and the multiplexer is configured to select either the storage unit or the CA interface, wherein the buffer circuit further comprises a buffer coupled between the data path and the multiplexer, and the multiplexer comprises a first input coupled to the CA interface, a second input coupled to the storage unit, and an output coupled to the buffer.
Regarding claim 11, the prior art of record does not appear to teach a memory device, comprising: a memory array comprising memory banks; and a peripheral circuit coupled to the memory array, the peripheral circuit comprising: content addressable memories (CAMs); a data path; and a buffer circuit coupled to the CAMs through the data path, wherein the buffer circuit comprises a multiplexer coupled to a storage unit and a command/address (CA) interface, and the multiplexer is configured to select either the storage unit or the CA interface, wherein the peripheral circuit is configured to: load data from the storage unit to the CAMs in a power on reset process of the memory device, wherein the peripheral circuit further comprises a match circuit coupled between the data path and the CAMs, and the match circuit comprises comparator circuits and is configured to: in response to receiving an address from the CA interface, compare the address to the data loaded to the CAMs and generate a comparison result.
Regarding claim 14, the prior art of record does not appear to teach a method of operating a memory device, comprising: loading, by a peripheral circuit of the memory device, data from a storage unit to content addressable memories (CAMs) through a buffer circuit and a data path, wherein the peripheral circuit comprises the CAMs, the buffer circuit, and the data path, and the buffer circuit comprises a multiplexer coupled to the storage unit; and receiving, by the peripheral circuit, an address from a command/address (CA) interface through the buffer circuit and the data path, wherein the CA interface is coupled to the multiplexer, wherein loading the data from the storage unit to the CAMs comprises: controlling a shift register coupled to the CAMs to enable writing of a first CAM of the CAMs; loading a first portion of the data from the storage unit to the first CAM; controlling the shift register to enable writing of a second CAM of the CAMs; and loading a second portion of the data from the storage unit to the second CAM.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm.
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/DANIEL JOHN KING/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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