Response to Arguments
Applicant's arguments filed 12/10/2025 have been fully considered but they are not persuasive.
Claims 1/13 was amended but not included all the limitations was from claim 4/15, the reference PARK YONG SEOK (KR20220093764, English machine translation), which reads on the newly amended claim 1 and/or 15. See figs. 6, 8, of PARK YONG SEOK (KR20220093764), wherein the carry signal output (Vgout) unit includes: an eighth transistor (T6) including a first electrode connected to a gate low voltage supply line (VGL), a gate electrode connected to the Q1 node (Q node), and a second electrode connected to a carry signal output terminal (Vgout); and a ninth transistor (T7) including a first electrode connected to a gate high voltage supply line (VGH), a gate electrode connected to the QB 1 node (QB node) , and a second electrode connected to the carry signal output terminal (Vgout).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 10-14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by PARK YONG SEOK (KR20220093764, English machine translation).
Regarding claim 1, 13, Park Yong Seok, figs. 6-8, discloses a gate driver, comprising: a plurality of stages which are connected to one another, wherein each of the plurality of stages includes (A gate driving circuit according to an embodiment of the present invention for achieving the above object includes a plurality of stages connected in a cascade, and the nth stage is a start signal or an output of the previous stage and a first clock signal): a node controller configured to control voltages of a Q node, a Q1 node, a Q2 node, a QB node, a QB1 node, and a QB2 node based on a first clock signal and a second clock signal ([One cycle of each of the clock signals CLK1 and CLK2 has a period of 4H, a low level of each of the clock signals CLK1 and CLK2 maintains a period of 2H-1u, and each of the clock signals CLK1 and CLK2 has a period of 2H-1u. A low level of n may maintain a period of 2H+1u. The second clock signal CLK2 is shifted by about 1u from the first clock signal CLK1); a carry signal output unit configured to output a carry signal to a next stage based on the voltages of the Q1 node and the QB1 node (see fig. 6, Vgout, clock signals CLK1 and CLK2); and a scan signal output unit configured to output a scan signal to a scan line based on the voltages of the Q node and the QB node (see fig. 6, Vgout, clock signals CLK1 and CLK2), and wherein a width of the scan signal is determined by a toggling timing of the first clock signal and a toggling timing of the second clock signal ([0138] [The start signal VST and the output signals Vgout(n-1), Vgout(n), Vgout(n+1)) maintain a high level for 4H. [0139] [One period of each of the clock signals CLK1 and CLK2 has a period of 4H, a low level of each of the clock signals CLK1 and CLK2 maintains a period of 2H-1u, and each of the clock signals CLK1 and CLK2 has a period of 2H-1u. A low level of n may maintain a period of 2H+1u. The second clock signal CLK2 is shifted by about 1u from the first clock signal CLK1. [0143] [And, after the 4H period, in a state in which the start signal VST or the output signal Vgout(n-1) of the previous stage is input at a low level, the first clock signal CLK1 is gated on again When the voltage (Low level) is applied (t2), the first node Q is charged to the gate-on voltage (Low Level) through the first and second TFTs T11 and T12); wherein the carry signal output (Vgout) unit includes: an eighth transistor (T17) including a first electrode connected to a gate low voltage supply line (VGL), a gate electrode connected to the Q1 node (Q node), and a second electrode connected to a carry signal output terminal (Vgout); and a ninth transistor (T18) including a first electrode connected to a gate high voltage supply line (VGH), a gate electrode connected to the QB 1 node (QB node) , and a second electrode connected to the carry signal output terminal (Vgout).
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Regarding claims 2, 14, Park Yong Seok, figs. 6-8, discloses the gate driver according to claim 1, wherein the scan signal output unit includes: a first transistor (T6) including a first electrode connected to a gate low voltage supply line (VGL), a gate electrode connected to the Q node (Q), and a second electrode connected to a scan signal output terminal (T17); a second transistor (T18) including a first electrode connected to a gate high voltage supply line (VGH), a gate electrode connected to the QB node (QB), and a second electrode connected to the scan signal output terminal (Vgout); and a first capacitor (Cq) connected between the gate electrode and the second electrode of the first transistor (T17, T18).
Regarding claim 3, Park Yong Seok, figs. 6-8, discloses the gate driver according to claim 2, wherein when the second clock signal is toggled from a high level to a low level, the first capacitor is configured to bootstrap the Q node (see fig. 7, ([0138] [The start signal VST and the output signals Vgout(n-1), Vgout(n), Vgout(n+1)) maintain a high level for 4H. [0139] [One period of each of the clock signals CLK1 and CLK2 has a period of 4H, a low level of each of the clock signals CLK1 and CLK2 maintains a period of 2H-1u, and each of the clock signals CLK1 and CLK2 has a period of 2H-1u. A low level of n may maintain a period of 2H+1u. The second clock signal CLK2 is shifted by about 1u from the first clock signal CLK1. [0143] [And, after the 4H period, in a state in which the start signal VST or the output signal Vgout(n-1) of the previous stage is input at a low level, the first clock signal CLK1 is gated on again When the voltage (Low level) is applied (t2), the first node Q is charged to the gate-on voltage (Low Level) through the first and second TFTs T11 and T12).
Regarding claim 10, Park Yong Seok, figs. 6-8, discloses the gate driver according to claim 1, wherein when the first clock signal is toggled from a high level to a low level, the scan signal is toggled from a low level to a high level, and when the second clock signal is toggled from a high level to a low level, the scan signal is toggled from a high level to a low level (see fig. 7).
Regarding claim 11, Park Yong Seok, figs. 6-8, discloses the gate driver according to claim 1, wherein when the first clock signal is toggled from a high level to a low level, the carry signal is toggled (see fig. 7).
Regarding claim 12, Park Yong Seok, figs. 6-8, discloses the gate driver according to claim 1, wherein a plurality of transistors included in each of the plurality of stages is p-type transistors (see pars. 48, 56, 65).
Allowable Subject Matter
Claims 4-9, 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Van N Chow whose telephone number is (571)272-7590. The examiner can normally be reached M-F 10-6PM.
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/VAN N CHOW/Primary Examiner, Art Unit 2627