Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
Claims 1-20 are presented for examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/13/2025, 01/18/2025, 01/17/2025, 01/16/2025, 01/14/2025, 01/08/2025, 12/28/2024, 12/10/2024, and 11/22/2024 have been considered. The submission is in compliance with the provisions of 37 CFR 1.97. Form PTO-1449 is signed and attached hereto.
Drawings
The drawings filed on 11/14/2024 are accepted by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims of Patent # 12,182,317 contains every element of claims of the instant application. Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting. A later patent claim is not patentably distinct from an earlier claim if the later claim is anticipated by the earlier claim. See the claim comparison below.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Furthermore, the ODP is not the only outstanding rejection and the claims, if allowed, would improperly extend the "right to exclude" already granted in the patent. A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Claim Comparison
Instant Application # 18/948,099
US Patent # 12,182,317
1. An apparatus comprising: memory to store data; decode circuitry to decode an instruction, the instruction to include a source operand; and execution circuitry to execute the decoded instruction according to the source operand to identify a pointer to a portion of the data stored in the memory, wherein the portion of the data is to be stored in a first region of the memory, wherein the first region of the memory includes a plurality of identically sized allocation slots, wherein each slot of the plurality of identically sized allocation slots is to store per-allocation metadata, wherein the per-allocation metadata comprises a reference counter.
2. The apparatus of claim 1, wherein the execution circuitry is to determine whether the pointer is within spatial bounds for a referenced allocation.
3. The apparatus of claim 1, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation.
4. The apparatus of claim 1, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation and the per-allocation metadata.
5. The apparatus of claim 1, wherein the per-allocation metadata further comprises allocation bounds information and allocation type information.
6. The apparatus of claim 1, wherein the per-allocation metadata further comprises an allocation type identifier, wherein a comparison of the allocation type identifier is to mitigate type confusion.
7. The apparatus of claim 1, wherein the execution circuitry is to consult a page table entry to determine a size and an offset for the plurality of identically sized allocation slots on a page.
8. An apparatus comprising: memory to store data; decode circuitry to decode an instruction, the instruction to include a first operand; and execution circuitry to execute the decoded instruction according to the first operand to determine a slot for an original pointer, wherein the original pointer is to point to a portion of the data stored in the memory, wherein the portion of the data is to be stored in a first region of the memory, wherein the first region of the memory includes a plurality of identically sized allocation slots, wherein each slot of the plurality of identically sized allocation slots is to store per-allocation metadata, wherein the per-allocation metadata comprises a reference counter.
9. The apparatus of claim 8, where the execution circuitry is to determine whether the original pointer is poisoned.
10. The apparatus of claim 9, where the execution circuitry is to determine a location of the poisoned original pointer.
11. The apparatus of claim 8, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation.
12. The apparatus of claim 8, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation and the per-allocation metadata.
13. The apparatus of claim 8, wherein the per-allocation metadata further comprises allocation bounds information and allocation type information.
14. The apparatus of claim 8, wherein the original pointer is unencrypted.
15. The apparatus of claim 8, wherein the original pointer is encrypted.
16. One or more non-transitory computer-readable media comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to: store data in a memory; decode an instruction, the instruction to include a source operand; and execute the decoded instruction according to the source operand to identify a pointer to a portion of the data stored in the memory, wherein the portion of the data is to be stored in a first region of the memory, wherein the first region of the memory includes a plurality of identically sized allocation slots, wherein each slot of the plurality of identically sized allocation slots is to store per-allocation metadata, wherein the per-allocation metadata comprises a reference counter.
17. The one or more non-transitory computer-readable media of claim 16, further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to determine whether the pointer is within spatial bounds for a referenced allocation.
18. The one or more non-transitory computer-readable media of claim 16, further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause each slot of the plurality of identically sized allocation slots to store a single allocation.
19. The one or more non-transitory computer-readable media of claim 16, further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause each slot of the plurality of identically sized allocation slots to store a single allocation and the per-allocation metadata.
20. The one or more non-transitory computer-readable media of claim 16, wherein the per-allocation metadata further comprises allocation bounds information and allocation type information.
1. An apparatus comprising: memory to store data; decode circuitry to decode an instruction, the instruction to include a source operand; and execution circuitry to execute the decoded instruction according to the source operand to encrypt a pointer to a portion of the data stored in the memory, wherein the portion of the data is to be stored in a first region of the memory, wherein the first region of the memory includes a plurality of identically sized allocation slots, wherein each slot of the plurality of identically sized allocation slots is to store per-allocation metadata, wherein the per-allocation metadata comprises allocation type information, allocation bounds information, and a reference counter.
2. The apparatus of claim 1, wherein the execution circuitry is to determine whether the pointer is within spatial bounds for a referenced allocation.
3. The apparatus of claim 1, wherein the decode circuitry is to decode a second instruction, the second instruction to include at least one source operand, wherein the execution circuitry is to execute the decoded second instruction according to the at least one source operand to decrypt the encrypted pointer.
4. The apparatus of claim 3, wherein the execution circuitry is to execute the decoded second instruction to determine whether the decrypted pointer is canonical.
5. The apparatus of claim 1, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation.
6. The apparatus of claim 1, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation and the per-allocation metadata.
7. The apparatus of claim 1, wherein the per-allocation metadata further comprises an allocation type identifier, wherein a comparison of the allocation type identifier is to mitigate type confusion.
8. The apparatus of claim 1, wherein the execution circuitry is to consult a page table entry to determine a size and an offset for the plurality of identically sized allocation slots on a page.
9. An apparatus comprising: memory to store data; decode circuitry to decode an instruction, the instruction to include a source operand; and execution circuitry to execute the decoded instruction according to the source operand to decrypt a pointer to a portion of the data stored in the memory, wherein the portion of the data is to be stored in a first region of the memory, wherein the first region of the memory includes a plurality of identically sized allocation slots, wherein each slot of the plurality of identically sized allocation slots is to store per-allocation metadata, wherein the per-allocation metadata comprises allocation type information, allocation bounds information, and a reference counter.
10. The apparatus of claim 9, wherein the execution circuitry is to determine whether the decrypted pointer is canonical.
11. The apparatus of claim 9, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation.
12. The apparatus of claim 9, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation and the per-allocation metadata.
13. The apparatus of claim 10, wherein an exception is to be generated in response to a determination that a portion of an attempted access is outside of bounds of a slot containing an allocation that the pointer is authorized to reference.
14. An apparatus comprising: memory to store data; decode circuitry to decode an instruction, the instruction to include a first operand; and execution circuitry to execute the decoded instruction according to the first operand to determine a slot for an original pointer, wherein the original pointer is to point to a portion of the data stored in the memory, wherein the portion of the data is to be stored in a first region of the memory, wherein the first region of the memory includes a plurality of identically sized allocation slots, wherein each slot of the plurality of identically sized allocation slots is to store per-allocation metadata, wherein the per-allocation metadata comprises allocation type information, allocation bounds information, and a reference counter.
15. The apparatus of claim 14, where the execution circuitry is to determine whether the original pointer is poisoned.
16. The apparatus of claim 15, where the execution circuitry is to determine a location of the poisoned original pointer.
17. The apparatus of claim 14, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation.
18. The apparatus of claim 14, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation and the per-allocation metadata.
19. The apparatus of claim 14, wherein the original pointer is unencrypted.
20. One or more non-transitory computer-readable media comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to: store data in memory; decode an instruction, the instruction to include a source operand; and execute the decoded instruction according to the source operand to encrypt a pointer to a portion of the data stored in the memory, wherein the portion of the data is to be stored in a first region of the memory, wherein the first region of the memory includes a plurality of identically sized allocation slots, wherein each slot of the plurality of identically sized allocation slots is to store per-allocation metadata, wherein the per-allocation metadata comprises allocation type information, allocation bounds information, and a reference counter.
21. The one or more computer-readable media of claim 20, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause determination of whether the pointer is within a spatial bounds for a referenced allocation.
22. The one or more computer-readable media of claim 20, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause decoding of a second instruction, the second instruction to include at least one source operand, and to cause execution of the decoded second instruction according to the at least one source operand to decrypt the encrypted pointer.
23. The apparatus of claim 9, wherein the per-allocation metadata further comprises an allocation type identifier, wherein a comparison of the allocation type identifier is to mitigate type confusion.
24. The apparatus of claim 14, wherein the per-allocation metadata further comprises an allocation type identifier, wherein a comparison of the allocation type identifier is to mitigate type confusion.
25. The one or more computer-readable media of claim 20, wherein the per-allocation metadata further comprises an allocation type identifier, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause a comparison of the allocation type identifier to mitigate type confusion.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
1. Claims 1-20 rejected under 35 U.S.C. 103 as being unpatentable over Gopal et al. (US Pub No. 2017/0093567, hereinafter “Gopal”) in view of Sugimoto et al. (US Pub No. 2015/0254186, hereinafter “Sugimoto”), further in view of Jain et al. (US Patent No. 11,182, 372, hereafter (“Jain”).
Regarding claim 1, Gopal does disclose, apparatus comprising: memory to store data; decode circuitry to decode an instruction, the instruction to include a source operand; and execution circuitry to execute the decoded instruction according to the source operand to identify a pointer to a portion of the data stored in the memory (Gopal, (para. [0030]), an instruction may include an opcode and one or more operands, where the opcode may be decoded into one or more micro-instructions or micro-operations for execution by execution unit 230; (para. [0050]), … where “rsi” and “rdi” represent implicit operands, a source register and a destination register, respectively, as described above, where the source register holds a pointer to the input buffer to be encrypted and the destination register holds a pointer to an output buffer in which to store the handle).
Gopal does not explicitly disclose, but Sugimoto does disclose, wherein the portion of the data is to be stored in a first region of the memory, wherein the first region of the memory includes a plurality of identically sized allocation slots (Sugimoto, (para. [0171]), if the size of the partial region is the same size as the cache segment, then it becomes possible to allocate the memory according to the access characteristics of each cache segment. However, if the size of the partial region is small, the amount of the access monitor table 342 that must be maintained and managed increases. Therefore, the size of the partial region may be an integral multiple of the cache segment size (for example, a size of the slot), or an integral multiple of the slot size; (para. [0094]), An entry 100a … of the cache directory 100 stores a directory entry pointer showing a slot control table 110 … corresponding to the slot ID. The slot here is a data unit … for performing exclusive control. For example, one slot can comprise multiple cache segments. In a case where data is only stored in a portion of the slot, the slot may comprise only one cache segment).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Gopal by including the first region of the memory includes a plurality of identically sized allocation slots taught by Sugimoto for the advantage of reducing cost of the IT systems (Sugimoto, (para. [0051])).
Gopal-Sugimoto does not explicitly disclose but the analogous art Jain discloses, wherein each slot of the plurality of identically sized allocation slots is to store per-allocation metadata, wherein the per-allocation metadata comprises a reference counter (Jain, (col. 21 lines 1-5), the reference counter may be stored as metadata for the parent partition. For example, a metadata store for the partitions may store relevant metadata, including the reference counter).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Gopal-Sugimoto by including wherein the per-allocation metadata comprises a reference counter taught by Jain for the advantage of improving computational efficiency by providing a single point of data to determine the number of child partitions that depend from the change log for the given partition (Jain, (col. 8 lines 46-49)).
Regarding claim 2, the combination of Gopal-Sugimoto-Jain does disclose, the apparatus of claim 1, wherein the execution circuitry is to determine whether the pointer is within spatial bounds for a referenced allocation (Sugimoto, (para. [0095]), the forward pointer 110b is a pointer which shows the anterior SLCT 110 in a sequence in either the clean queue or the dirty queue. The backward pointer 110c is a pointer which shows the posterior SLCT 110 in a sequence in either the clean queue or the dirty queue. …. The SGCT pointer 110f is a pointer which points to the SGCT 120 corresponding to the cache segment included in the relevant slot)
Regarding claim 3, the combination of Gopal-Sugimoto-Jain does disclose, the apparatus of claim 1, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation (Sugimoto, (para. [0171]), if the size of the partial region is the same size as the cache segment, then it becomes possible to allocate the memory according to the access characteristics of each cache segment. ….; (para. [0094]), an entry 100a … of the cache directory 100 stores a directory entry pointer showing a slot control table 110 … corresponding to the slot ID. The slot here is a data unit … for performing exclusive control. For example, one slot can comprise multiple cache segments. In a case where data is only stored in a portion of the slot, the slot may comprise only one cache segment)
Regarding claim 4, the combination of Gopal-Sugimoto-Jain does disclose, the apparatus of claim 1, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation and the per-allocation metadata (Sugimoto, (para. [0171]), if the size of the partial region is the same size as the cache segment, then it becomes possible to allocate the memory according to the access characteristics of each cache segment. ….; (para. [0094]), an entry 100a … of the cache directory 100 stores a directory entry pointer showing a slot control table 110 … corresponding to the slot ID. The slot here is a data unit … for performing exclusive control. For example, one slot can comprise multiple cache segments. In a case where data is only stored in a portion of the slot, the slot may comprise only one cache segment; (para. [0134]), …. Metadata …).
Regarding claim 5, the combination of Gopal-Sugimoto-Jain does disclose, the apparatus of claim 1, wherein the per-allocation metadata further comprises allocation bounds information and allocation type information (Sugimoto, (para. [0135]), … performs a cache allocation based on the criteria ….).
Regarding claim 6, the combination of Gopal-Sugimoto-Jain does disclose, the apparatus of claim 1, wherein the per-allocation metadata further comprises an allocation type identifier, wherein a comparison of the allocation type identifier is to mitigate type confusion (Sugimoto, (para. [0139]), metadata comprises control information, which either was saved and stored, or is to be saved and stored in the drive (40, 41) from the storage controller 30 RAM 34. Whether or not the access-target data is metadata).
Regarding claim 7, the combination of Gopal-Sugimoto-Jain does disclose, the apparatus of claim 1, wherein the execution circuitry is to consult a page table entry to determine a size and an offset for the plurality of identically sized allocation slots on a page (Sugimoto, (para. [0003, 0072]), … each FM block is comprised of multiple pages (physical pages) ….; (para. [0138]), …. provides the real page being allocated to the logical volume ….; (para. 0172]), … providing a logical volume accompanying a so-called thin provisioning includes a function of tabulating the access frequency and the like for each partial region (which is called a page), in order to determine the storage area to be allocated to each page of the logical volume).
Regarding claim 8, the substance of the claimed invention is similar to that of claim 1. Accordingly, this claim is rejected under the same rationale.
Regarding claim 9, the combination of Gopal-Sugimoto-Jain does disclose, the apparatus of claim 8, where the execution circuitry is to determine whether the original pointer is poisoned (Sugimoto, (para. [0095, 0105]), the forward pointer 110b is a pointer which shows the anterior SLCT 110 in a sequence in either the clean queue or the dirty queue).
Regarding claim 10, the combination of Gopal-Sugimoto-Jain does disclose, the apparatus of claim 9, where the execution circuitry is to determine a location of the poisoned original pointer (Sugimoto, (para. [0095]), the forward pointer 110b is a pointer which shows the anterior SLCT 110 in a sequence in either the clean queue or the dirty queue. The backward pointer 110c is a pointer which shows the posterior SLCT 110 in a sequence in either the clean queue or the dirty queue. …. The SGCT pointer 110f is a pointer which points to the SGCT 120 corresponding to the cache segment included in the relevant slot).
Regarding claim 11, the substance of the claimed invention is similar to that of claim 3. Accordingly, this claim is rejected under the same rationale.
Regarding claim 12, the substance of the claimed invention is similar to that of claim 4. Accordingly, this claim is rejected under the same rationale.
Regarding claim 13, the substance of the claimed invention is similar to that of claim 5. Accordingly, this claim is rejected under the same rationale.
Regarding claim 14, the combination of Gopal-Sugimoto-Jain does disclose, the apparatus of claim 8, wherein the original pointer is unencrypted (Gopal, (para. [0050]), where the source register holds a pointer to the input buffer to be encrypted and the destination register holds a pointer to an output buffer in which to store the handle).
Regarding claim 15, the combination of Gopal-Sugimoto-Jain does disclose, the apparatus of claim 8, wherein the original pointer is encrypted (Gopal, (para. [0050]), where the source register holds a pointer to the input buffer to be encrypted and the destination register holds a pointer to an output buffer in which to store the handle); (para. [0072]), the processor may use the decrypted key to encrypt or decrypt the information as requested in box 554. The box 564, the processor discards the decrypted key).
Regarding claim 16, the substance of the claimed invention is similar to that of claim 1. Accordingly, this claim is rejected under the same rationale.
Regarding claim 17, the substance of the claimed invention is similar to that of claim 2. Accordingly, this claim is rejected under the same rationale.
Regarding claim 18, the substance of the claimed invention is similar to that of claim 3. Accordingly, this claim is rejected under the same rationale.
Regarding claim 19, the substance of the claimed invention is similar to that of claim 4. Accordingly, this claim is rejected under the same rationale.
Regarding claim 20, the substance of the claimed invention is similar to that of claim 20. Accordingly, this claim is rejected under the same rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Publication No. 2019/0095345, “Memory encryption protects the confidentiality of memory-resident data. Memory encryption is primarily designed to protect against passive attacks where an attacker tries to silently observe the data lines as the data lines move on and off the processing device die. Some processing devices include an encryption module that encrypts sensitive data before the data is stored into a protected region of the memory. On a memory read to the protected region, the data line is decrypted before being fed into the processing device. The encryption and decryption algorithms can be chosen based on the security level required by the user. In various embodiments described herein, the secure memory paging can be performed with respect to secure containers, referred to herein as Secure Enclaves (SEs) or just “enclave.” The system software (OS or VMM) may create one or more SEs in a protected region of memory. The SEs are designed to protect third-party secrets from both hardware and software attacks. SE can protect the confidentiality of enclave secrets by ensuring that the enclave secrets are stored encrypted when resident in platform memory. In order to provide complete protection from hardware attacks, SEs provide integrity protection and replay protection. In the absence of such protections, an attacker with physical access to the system can record snapshots of enclave cache lines and replay them at a later point in time. In order to achieve these protections, SE employs a memory encryption engine (MEE), which provides cryptographic mechanisms for encryption, integrity, and replay protection.”.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MORSHED MEHEDI whose telephone number is (571) 270-7640. The examiner can normally be reached on M - F, 8:00 am to 4:00 pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Linglan Edwards can be reach on (571) 270-5440. The fax number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from their Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (In USA or Canada) or 571-272-1000.
/MORSHED MEHEDI/Primary Examiner, Art Unit 2408