Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This office action has been issued in response to arguments/amendments filed on 06/10/2026. Claims 1, 8, and 16 are amended. Claims 1-20 are presented for examination.
Response to Arguments
1. Applicant's arguments see pages 5-7, filed on 06/10/2026, with respect to the rejection of claims 1-20 under USC § 103(a) have been fully considered, and with the newly amended features, the arguments are persuasive. Accordingly, the rejection under 35 USC § 103(a) is withdrawn. However, the double patenting rejection is maintained.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims of Patent # 12,182,317 contains every element of claims of the instant application. Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting. A later patent claim is not patentably distinct from an earlier claim if the later claim is anticipated by the earlier claim. See the claim comparison below.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Furthermore, the ODP is not the only outstanding rejection and the claims, if allowed, would improperly extend the "right to exclude" already granted in the patent. A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Claim Comparison
Instant Application # 18/948,099
US Patent # 12,182,317
1. An apparatus comprising: memory to store data; decode circuitry to decode an instruction, the instruction to include a source operand; and execution circuitry to execute the decoded instruction according to the source operand to identify a pointer to a portion of the data stored in the memory, wherein the portion of the data is to be stored in a first region of the memory, wherein the first region of the memory includes a plurality of identically sized allocation slots, wherein each slot of the plurality of identically sized allocation slots is to store per-allocation metadata, wherein the per-allocation metadata comprises an object reference counter.
2. The apparatus of claim 1, wherein the execution circuitry is to determine whether the pointer is within spatial bounds for a referenced allocation.
3. The apparatus of claim 1, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation.
4. The apparatus of claim 1, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation and the per-allocation metadata.
5. The apparatus of claim 1, wherein the per-allocation metadata further comprises allocation bounds information and allocation type information.
6. The apparatus of claim 1, wherein the per-allocation metadata further comprises an allocation type identifier, wherein a comparison of the allocation type identifier is to mitigate type confusion.
7. The apparatus of claim 1, wherein the execution circuitry is to consult a page table entry to determine a size and an offset for the plurality of identically sized allocation slots on a page.
8. An apparatus comprising: memory to store data; decode circuitry to decode an instruction, the instruction to include a first operand; and execution circuitry to execute the decoded instruction according to the first operand to determine a slot for an original pointer, wherein the original pointer is to point to a portion of the data stored in the memory, wherein the portion of the data is to be stored in a first region of the memory, wherein the first region of the memory includes a plurality of identically sized allocation slots, wherein each slot of the plurality of identically sized allocation slots is to store per-allocation metadata, wherein the per-allocation metadata comprises a reference counter.
9. The apparatus of claim 8, where the execution circuitry is to determine whether the original pointer is poisoned.
10. The apparatus of claim 9, where the execution circuitry is to determine a location of the poisoned original pointer.
11. The apparatus of claim 8, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation.
12. The apparatus of claim 8, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation and the per-allocation metadata.
13. The apparatus of claim 8, wherein the per-allocation metadata further comprises allocation bounds information and allocation type information.
14. The apparatus of claim 8, wherein the original pointer is unencrypted.
15. The apparatus of claim 8, wherein the original pointer is encrypted.
16. One or more non-transitory computer-readable media comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to: store data in a memory; decode an instruction, the instruction to include a source operand; and execute the decoded instruction according to the source operand to identify a pointer to a portion of the data stored in the memory, wherein the portion of the data is to be stored in a first region of the memory, wherein the first region of the memory includes a plurality of identically sized allocation slots, wherein each slot of the plurality of identically sized allocation slots is to store per-allocation metadata, wherein the per-allocation metadata comprises a reference counter.
17. The one or more non-transitory computer-readable media of claim 16, further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to determine whether the pointer is within spatial bounds for a referenced allocation.
18. The one or more non-transitory computer-readable media of claim 16, further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause each slot of the plurality of identically sized allocation slots to store a single allocation.
19. The one or more non-transitory computer-readable media of claim 16, further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause each slot of the plurality of identically sized allocation slots to store a single allocation and the per-allocation metadata.
20. The one or more non-transitory computer-readable media of claim 16, wherein the per-allocation metadata further comprises allocation bounds information and allocation type information.
1. An apparatus comprising: memory to store data; decode circuitry to decode an instruction, the instruction to include a source operand; and execution circuitry to execute the decoded instruction according to the source operand to encrypt a pointer to a portion of the data stored in the memory, wherein the portion of the data is to be stored in a first region of the memory, wherein the first region of the memory includes a plurality of identically sized allocation slots, wherein each slot of the plurality of identically sized allocation slots is to store per-allocation metadata, wherein the per-allocation metadata comprises allocation type information, allocation bounds information, and a reference counter.
2. The apparatus of claim 1, wherein the execution circuitry is to determine whether the pointer is within spatial bounds for a referenced allocation.
3. The apparatus of claim 1, wherein the decode circuitry is to decode a second instruction, the second instruction to include at least one source operand, wherein the execution circuitry is to execute the decoded second instruction according to the at least one source operand to decrypt the encrypted pointer.
4. The apparatus of claim 3, wherein the execution circuitry is to execute the decoded second instruction to determine whether the decrypted pointer is canonical.
5. The apparatus of claim 1, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation.
6. The apparatus of claim 1, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation and the per-allocation metadata.
7. The apparatus of claim 1, wherein the per-allocation metadata further comprises an allocation type identifier, wherein a comparison of the allocation type identifier is to mitigate type confusion.
8. The apparatus of claim 1, wherein the execution circuitry is to consult a page table entry to determine a size and an offset for the plurality of identically sized allocation slots on a page.
9. An apparatus comprising: memory to store data; decode circuitry to decode an instruction, the instruction to include a source operand; and execution circuitry to execute the decoded instruction according to the source operand to decrypt a pointer to a portion of the data stored in the memory, wherein the portion of the data is to be stored in a first region of the memory, wherein the first region of the memory includes a plurality of identically sized allocation slots, wherein each slot of the plurality of identically sized allocation slots is to store per-allocation metadata, wherein the per-allocation metadata comprises allocation type information, allocation bounds information, and a reference counter.
10. The apparatus of claim 9, wherein the execution circuitry is to determine whether the decrypted pointer is canonical.
11. The apparatus of claim 9, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation.
12. The apparatus of claim 9, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation and the per-allocation metadata.
13. The apparatus of claim 10, wherein an exception is to be generated in response to a determination that a portion of an attempted access is outside of bounds of a slot containing an allocation that the pointer is authorized to reference.
14. An apparatus comprising: memory to store data; decode circuitry to decode an instruction, the instruction to include a first operand; and execution circuitry to execute the decoded instruction according to the first operand to determine a slot for an original pointer, wherein the original pointer is to point to a portion of the data stored in the memory, wherein the portion of the data is to be stored in a first region of the memory, wherein the first region of the memory includes a plurality of identically sized allocation slots, wherein each slot of the plurality of identically sized allocation slots is to store per-allocation metadata, wherein the per-allocation metadata comprises allocation type information, allocation bounds information, and a reference counter.
15. The apparatus of claim 14, where the execution circuitry is to determine whether the original pointer is poisoned.
16. The apparatus of claim 15, where the execution circuitry is to determine a location of the poisoned original pointer.
17. The apparatus of claim 14, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation.
18. The apparatus of claim 14, wherein each slot of the plurality of identically sized allocation slots is to store a single allocation and the per-allocation metadata.
19. The apparatus of claim 14, wherein the original pointer is unencrypted.
20. One or more non-transitory computer-readable media comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to: store data in memory; decode an instruction, the instruction to include a source operand; and execute the decoded instruction according to the source operand to encrypt a pointer to a portion of the data stored in the memory, wherein the portion of the data is to be stored in a first region of the memory, wherein the first region of the memory includes a plurality of identically sized allocation slots, wherein each slot of the plurality of identically sized allocation slots is to store per-allocation metadata, wherein the per-allocation metadata comprises allocation type information, allocation bounds information, and a reference counter.
21. The one or more computer-readable media of claim 20, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause determination of whether the pointer is within a spatial bounds for a referenced allocation.
22. The one or more computer-readable media of claim 20, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause decoding of a second instruction, the second instruction to include at least one source operand, and to cause execution of the decoded second instruction according to the at least one source operand to decrypt the encrypted pointer.
23. The apparatus of claim 9, wherein the per-allocation metadata further comprises an allocation type identifier, wherein a comparison of the allocation type identifier is to mitigate type confusion.
24. The apparatus of claim 14, wherein the per-allocation metadata further comprises an allocation type identifier, wherein a comparison of the allocation type identifier is to mitigate type confusion.
25. The one or more computer-readable media of claim 20, wherein the per-allocation metadata further comprises an allocation type identifier, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause a comparison of the allocation type identifier to mitigate type confusion.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MORSHED MEHEDI whose telephone number is (571) 270-7640. The examiner can normally be reached on M - F, 8:00 am to 4:00 pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Linglan Edwards can be reach on (571) 270-5440. The fax number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from their Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (In USA or Canada) or 571-272-1000.
/MORSHED MEHEDI/Primary Examiner, Art Unit 2408
Prosecution Insights