DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
This office action is in response to the amendment filed on 03/27/2026.
Claims 1-2, 5, 8-10, 26-37 are presented for further examination.
The amendment to independent claims overcome the rejection based on Moon and Zulauf. However, upon further searching and analysis, additional prior arts are identified are identified that teach the amended claim(s).
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 5, 26-28, and 32-34 are rejected under 35 U.S.C. 103 as being unpatentable over Nickolls et al. (US2011/0072213, hereinafter Nickolls) in view of Zulauf (US2008/0052466)
Regarding independent claims 1, 26 and 32, taking claim 1 as exemplary analysis, Nickolls teaches A graphics processor, comprising: processing resources to perform graphics operations (Nickolls discloses a graphics processing subsystem having PPUs, GPCs, execution units, load/store units, and cache hierarchy resources including L1 and L2 caches as shown in Figs. 2-5; Abstract;
[0009], a method for managing a parallel cache hierarchy in a processing unit; [0146], The program(s) of the program product define functions of the embodiments (including the methods described herein) and can be contained on a variety of computer-readable storage media));
Nickolls teaches cache control instructions “cctl” and “cache operations” (.cop) controlling a cache coupled to the processing resources ([0073-[0077]; [0085], The default ld instruction cache operation is ld.ca, which allocates cache lines in all levels (L1 and L2) with normal eviction policy; [0086], Alternatively, a program can bypass the L1 cache level with the ld.cg load cache global operation described below, to avoid fetching stale L1 data), however, Nickolls does not expressly teach a cache controller.
In an analogous art of cache configuration, Zulauf teaches a cache controller of a cache ([0020], the cache controller 108 includes a cache line allocation controller 136 to determine the cache line allocation polices for the cache 110 and to configure the cache controller 108 to comply with the selected cache line allocation policies).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention was made, with the teachings of Nickolls and Zulauf before them, to incorporate Zulauf’s cache controller to implement a certain cache line allocation policy with Nickolls’ cache control instructions “cctl” for the motivation that cache controller is well known in the field that implements cache line allocation policies.
The combination of Nickolls and Zulauf further teaches wherein the cache controller is configured to control cache priority by determining whether default cache settings or an instruction to control cache operations for the cache (
Nickolls, [0085], The default ld instruction cache operation is ld.ca, which allocates cache lines in all levels (L1 and L2) with normal eviction policy; [0086], Alternatively, a program can bypass the L1 cache level with the ld.cg load cache global operation described below, to avoid fetching stale L1 data); [0132], At step 604, the LSU determines whether the memory access instruction includes a cache operations (.cop) modifier. If the LSU determines that the memory access instruction does not include a .cop modifier (i.e., default memory access instruction), then the method 600 proceeds to step 606. At step 606, the LSU causes data associated with the memory access instruction to be cached in both the L1 and L2 caches with normal eviction policies;
Zulauf also teaches a cache controller configured to determine whether a default cache allocation policy or an instruction-specific cache allocation policy should control cache operation. See Zulauf Fig. 2, Fig. 4, [0021], the cache line allocation controller 136 initially configures the cache controller 108 to implement default (or instruction independent) cache line allocation polices for corresponding memory addresses or memory regions (or to implement a default global cache line allocation policy). As the execution of instructions commences, the cache allocation controller 136 is notified of an instruction to be executed and, based on the instruction and other information, the cache allocation controller 136 configures the cache controller 108 to implement an alternate cache line allocation policy (other than the default cache line allocation policy) for the instruction if so warranted by the instruction and by a policy arbitration process), wherein the cache controller is configured to receive a store message having a write-streaming attribute to stream data for a streaming store that is cached at low priority in the cache (
Nickolls teaches an evict-first cache policy for streaming data in Figure 6, block 616, “Cache with evict-first policy in L1 and L2.” An evict-first cache policy would have been understood by one of ordinary skill in the art as assigning lower cache residency priority to cache lines associated with streaming data.
[0136], At step 614, the LSU determines whether the .cop is equal to “.cs” (i.e., cache streaming). If the LSU determines that the .cop is equal to “.cs,” then the method 600 proceeds to step 616. At step 616, the LSU causes data associated with the memory access instruction to be cached in both the L1 and L2 caches with “evict-first” eviction policies. In one implementation, this data is only going to be read once, used once, and never used again, and can bypass the L1 and L2 caches in a streaming cache or FIFO).
Regarding claim(s) 2, 27 and 33, the combination of Nickolls and Zulauf further teaches wherein the cache controller is configured to determine the default cache settings and further to determine whether the instruction has been received, wherein the cache controller is configured to apply the instruction if the instruction has been received, and wherein the cache controller to apply the default cache settings if the instruction has not been received (Zulauf discloses default cache line allocation policies, alternate instruction-specific cache policies, and policy arbitration logic selecting between default and alternate policies, see Zulauf Fig. 2; Fig. 4; [0021]-[0023];
Nickolls, [0085], The default ld instruction cache operation is ld.ca, which allocates cache lines in all levels (L1 and L2) with normal eviction policy; [0086], Alternatively, a program can bypass the L1 cache level with the ld.cg load cache global operation described below, to avoid fetching stale L1 data); [0132], At step 604, the LSU determines whether the memory access instruction includes a cache operations (.cop) modifier).
Regarding claim(s) 5, 28 and 34, the combination of Nickolls and Zulauf further teaches wherein the cache comprises a first level cache of the processing resources (Nickolls, Fig. 5, L1 cache), wherein the default cache settings comprise one or more of caching, write-through, write-back, write-streaming for store or atomics operations, load caching, or load streaming for load or prefetch operations (Zulauf, [0016], Examples of caching actions can include, for example, “no caching” … one cache line allocation policy can designate a certain write action as a write-through action;
Nickolls [0136], At step 614, the LSU determines whether the .cop is equal to “.cs” (i.e., cache streaming). If the LSU determines that the .cop is equal to “.cs,” then the method 600 proceeds to step 616. At step 616, the LSU causes data associated with the memory access instruction to be cached in both the L1 and L2 caches with “evict-fist” eviction policies).
Claims 8, 29, and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Nickolls et al. (US 2011/0072213, hereinafter Nickolls) in view of Zulauf (US 2008/0052466), further in of Biswas (US 2014/0089602) and Damron et al. (US 6,578,111; hereinafter Damron).
Regarding claim(s) 8, 29 and 35, Nickolls and Zulauf do not explicitly disclose using an LRU position to merge partial writes until a complete cache line is generated.
Biswas teaches accumulation and merging of partial writes into a cache line as shown in Fig. 10; [0074]-[0082]. Biswas discloses receiving a first partial write request, storing partial data in a cache line, receiving additional partial write requests directed to the same cache line, and updating the cache line and associated masks until a complete cache line is formed.
Damron teaches cache replacement using least-recently-used (LRU) information and selecting cache locations based on LRU status as shown in Damron col. 7, ll. 1-35; col. 10, ll. 10-45).
It would have been obvious to employ the well-known LRU cache management techniques of Damron in the cache architecture of Biswas so that cache locations used to accumulate partial writes could be selected and maintained according to known cache replacement criteria, thereby improving cache utilization and replacement efficiency.
Thus, the combination of Nickolls, Zulauf, Biswas and Damron teaches wherein a least recently used (LRU) position of the cache is used to merge partial writes in the cache until a full cache line is generated based on a plurality of partial writes.
Claims 9, 30 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Nickolls et al. (US 2011/0072213, hereinafter Nickolls) in view of Zulauf (US 2008/0052466), further in of Lepak et al. (US 7,640,399; hereinafter Lepak).
Regarding claim(s) 9, 30 and 36, Nickolls teaches instruction-controlled load operations. However, Nickolls and Zulauf do not explicitly disclose invalid after read.
In analogous art of cache management, Lepak teaches invalid after read policy for private data as shown in col. 4, ll. 48-67, "Scheme 5: Private Data Policy for Modified data. If a line is in a modified (M) coherency state in the L3 cache and a read transaction hits it, invalidate the line and return to the accessing core the data as modified (M)."
Lepak further explains: this may be conditioned on whether the modified data is "private" or "shared," i.e., whether the processing entity that installed the line is the same entity subsequently accessing it.
Lepak further teaches: "Scheme 6: Private Data Policy for Shared/Exclusive data. If a line is in a shared or exclusive (S/E) coherency state in the L3 cache and a read hits the line, invalidate the line if the access is a non-shared access..."
A person of ordinary skill in the art would have been motivated to combine Nickolls with Lepak for addressing the same technical problem: reducing cache pollution and unnecessary writebacks for private/one-time data in multi-core/parallel processors, including those used for graphics processing. Nickolls already provides a GPU-specific mechanism using per-load attributes for private memory accesses. Lepak’s private-data conditional invalidation policy is a natural enhancement or alternative implementation that improves efficiency in shared cache hierarchies. Applying Lepak’s private-data-based invalidation rule to Nickolls’ attribute-controlled load messages would have been a predictable improvement that yields a cache controller capable of receiving a load message with an “invalid after read” attribute and performing the claimed invalidation when the data is private.
Thus, the combination of Nickolls, Zulauf and Lepak teaches wherein the cache controller is configured to receive a load message having an invalid after read attribute to invalidate data for a cache hit in the cache after a read operation if the data is from a private memory.
Claims 10, 31 and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Nickolls et al. (US 2011/0072213, hereinafter Nickolls) in view of Zulauf (US 2008/0052466), further in of Damron et al. (US 6,578,111; hereinafter Damron).
Regarding claim(s) 10, 31 and 37, the combination of Nickolls and Zulauf further teaches wherein the cache controller is configured to receive Nickolls teaches cache operation modifiers associated with load instructions and expressly teaches streaming behavior for load/store memory operations ([0008]).
Nickolls further teaches caching such data using an evict-first cache policy (Fig. 6 block 616; Fig. 7 block 716)).
Nickolls and Zulauf do not explicitly disclose a prefetch message having a load streaming attribute, which is taught by Damron (col. 11, ll. 43-51, Referring to FIG. 9, the method of determining whether the data is streaming-data involves receiving in cache controller 140 a request to load data to cache 135 from main-memory 115 (step 420), and recognizing whether the request includes a special pre-fetch instruction to pre-fetch streaming-data from main-memory. (step 425) The special instruction can take the form, for example, of PREFETCH [A], STREAMING_DATA, where A is the address of the data in main-memory 115).
A person of ordinary skill in the art would have been motivated to modify Nickolls to employ the stream-prefetch cache management technique of Damron so that prefetched streaming data is cached with reduced priority and preferentially evicted relative to ordinary cache data. Doing so would have predictably reduced cache pollution from streamed data having low temporal locality while preserving cache capacity for data more likely to be reused, thereby improving overall cache utilization and system performance.
The combination of Nickolls, Zulauf and Damron further teaches wherein the data being streamed is then evicted using a LRU position in the cache (Damron, col. 4, ll. 18-21, There are various different replacement algorithms that can be used. The most commonly utilized replacement algorithm is known as Least Recently Used (LRU))
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-2, 5-10, 26-37 rejected on the ground of nonstatutory double patenting as being anticipated by claims 1-13 of U.S. Patent No. 12,210,477).
Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are anticipated as shown below.
Current application
PAT 12,210,477
1,
26,
32
A graphics processor, comprising:
processing resources to perform graphics operations; and
a cache controller of a cache coupled to the processing resources, wherein the cache controller is configured to
control cache priority by determining whether default cache settings
or an instruction to control cache operations for the cache,
the cache controller is configured to receive a store message having a write-streaming attribute to stream data for a streaming store that is cached at low priority in the cache.
1
A graphics processor, comprising:
processing resources to perform graphics operations; and
a cache controller of a cache of the graphics processor coupled to the processing resources, wherein the cache controller is configured to
control cache priority by determining a default setting having a default cache attribute to be applied if no received instruction,
determining whether an instruction from an application with an associated cache attribute has been received, and applying the instruction and the associated cache attribute when the instruction is received by the cache controller, wherein the cache controller is configured to receive the instruction including a store instruction having a write-streaming attribute to stream data for a streaming store that is cached with a low priority cache attribute in the cache.
2,
27,
33
the cache controller is configured to determine the default cache settings and
further to determine whether the instruction has been received,
wherein the cache controller is configured to apply the instruction if the instruction has been received,
and wherein the cache controller to apply the default cache settings if the instruction has not been received.
1
3
4
the cache controller is configured to … determining a default setting having a default cache attribute to be applied if no received instruction,
determining whether an instruction from an application with an associated cache attribute has been received
the cache controller is configured to apply the instruction and associated cache attribute if the instruction has been received.
the cache controller applies the default cache attribute if an instruction has not been received.
5,
28,
34
the cache comprises a first level cache of the processing resources,
wherein the default cache settings comprise one or more of caching, write-through, write-back, write-streaming for store or atomics operations,
load caching, or load streaming for load or prefetch operations.
5
6
7
the cache comprises a first level cache of the processing resources.
the associated cache attribute comprises no caching, write-through, write-back, or write-streaming for store or atomics operations.
the associated cache attribute comprises no caching, load caching, or load streaming for load or prefetch operations.
8,
29,
35
a least recently used (LRU) position of the cache is used
to merge partial writes in the cache until a full cache line is generated based on a plurality of partial writes.
1
8
11
wherein the data being streamed for a streaming store that is cached at low priority in the cache is evicted using a least recently used (LRU) position of the cache
wherein a least recently used (LRU) position of the cache is used to merge partial writes in the cache until a full cache line is generated based on a plurality of partial writes
9,
30,
36
the cache controller is configured to receive a load message having an invalid after read attribute to invalidate data for a cache hit in the cache after a read operation if the data is from a private memory.
9
the cache controller is configured to receive a load message having an invalid after read attribute to invalidate data for a cache hit in the cache after a read operation if the data is from a private memory
10,
31,
37
the cache controller is configured to receive a prefetch message having a load streaming attribute with data being streamed that is prefetched into the cache and given low priority, wherein the data being streamed is then evicted using a LRU position in the cache.
10
the cache controller is configured to receive a prefetch message having a load streaming attribute with data being streamed that is prefetched into the cache and given low priority, wherein the data being streamed is then evicted using a LRU position in the cache
Conclusion
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/TRACY C CHAN/ Primary Examiner, Art Unit 2138
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