Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim(s) 1-23 is/are objected to because of the following informalities:
Claim 1 is suggested to be amended as “the first array data” (in the last paragraph) for addressing informalities.
Claims 2-23 are also objected for being dependent of the base claim.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“flaw extraction unit” in claim(s) 1, 8-11 and 21.
“array generation unit” in claim(s) 1 and 6.
“correction unit” in claim(s) 1, 13 and 16.
“calculation unit” in claim(s) 1, 14, 18 and 20.
“gain adjustment unit” in claim(s) 12.
“nonlinear correction unit” in claim(s) 13.
“demosaicing unit” in claim(s) 16.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 of U.S. Patent No. 12219278 (hereinafter “Pat’278”). Although the claims at issue are not identical, they are not patentably distinct from each other.
Instance Application
Pat’278
1. A processing apparatus comprising:
a first storage unit for storing first array data that is based on output values of a plurality of pixels arranged in an array;
a second storage unit having second array data stored therein to be used for correction of the output values from of the plurality of pixels; and
a flaw extraction unit configured to extract an output value and a position of a flaw pixel from the first array data;
an array generation unit configured to generate third array data based on the second array data and the output value and the position of the flaw pixel, the third array data being estimated flaw array data; and
a correction unit having a calculation unit configured to correct an output value of at least one pixel of the plurality of pixels based on the first array date and the third array data.
1. A processing apparatus comprising:
a first storage unit for storing first array data that is based on output values of a plurality of pixels arranged in an array;
a second storage unit having second array data stored therein to be used for correction of the output values from the plurality of pixels;
a correction unit including a calculation unit configured to correct an output value of at least one pixel of the plurality of pixels based on the first array data and the second array data;
a flaw extraction unit configured to extract an output value and a position of a flaw pixel from the first array data; and
an array generation unit configured to generate third array data based on the second array data and the output value and the position of the flaw pixel, wherein the second array data is generated based on a pattern of a flaw pixel in an optical black (OB) region of the plurality of pixels.
2. The processing apparatus according to claim 1, wherein the calculation unit is configured to correct an output value of at least one surrounding pixel positioned around the flaw pixel, based on the first array data and the third array data.
20. The processing apparatus according to claim 1, wherein, after
an output value of a surrounding pixel provided in a neighborhood of the flaw pixel has been corrected by the calculation unit, an output value of the flaw pixel is corrected based on the corrected output value of the surrounding pixel.
3. The processing apparatus according to claim 2, wherein, after an output value of the surrounding pixel has been corrected by the calculation unit, an output value of the flaw pixel is corrected based on the corrected output value of the surrounding pixel.
Claims 1-23 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3 and 6-24 of U.S. Patent No. 12219278 (hereinafter “Pat’278”) in view of Kishima (US 20140016005 A1) or Aldrich et al (US 8310570 B1).
Instance Application
Pat’278
1. A processing apparatus comprising:
a first storage unit for storing first array data that is based on output values of a plurality of pixels arranged in an array;
a second storage unit having second array data stored therein to be used for correction of the output values from of the plurality of pixels; and
a flaw extraction unit configured to extract an output value and a position of a flaw pixel from the first array data;
an array generation unit configured to generate third array data based on the second array data and the output value and the position of the flaw pixel,
1. A processing apparatus comprising:
a first storage unit for storing first array data that is based on output values of a plurality of pixels arranged in an array;
a second storage unit having second array data stored therein to be used for correction of the output values from the plurality of pixels;
a correction unit including a calculation unit configured to correct an output value of at least one pixel of the plurality of pixels based on the first array data and the second array data;
a flaw extraction unit configured to extract an output value and a position of a flaw pixel from the first array data; and
an array generation unit configured to generate third array data based on the second array data and the output value and the position of the flaw pixel, wherein the second array data is generated based on a pattern of a flaw pixel in an optical black (OB) region of the plurality of pixels.
but fails to teach the strike-out features.
However, in the same field of endeavor Kishima/Aldrich teaches the strike-out features as presented in the claim rejections below.
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Kishima/Aldrich in claim 1 of Pat’278 to have the features for utilizing optimized correction data to correct defective image data so that better image quality can be obtained yielding a predicted result.
Claims 2-5
Claims 6-9
Claim 6
In the same field of endeavor, Kishima teaches claim 6’s feature as presented below in the 102 rejections. Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Kishima in claim 1 of Pat’278 to have the feature of claim 6 for utilizing optimized correction data type to correct defective image data so that better image quality can be obtained yielding a predicted result.
Claims 7-18
Claims 10-21
Claim 19
Claim 1: wherein the second array data is generated based on a pattern of a flaw pixel in an optical black (OB) region of the plurality of pixels
Claim 20
Claim 3
Claims 21-23
Claims 22-24
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9, 11, 13, 16, 17, 20 and 22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kishima (US 20140016005 A1).
Regarding claim 1, Kishima teaches A processing apparatus (Figs. 19, 27, 28) comprising:
a first storage unit (43) for storing first array data (S0) that is based on output values of a plurality of pixels arranged in an array (Fig. 19);
a second storage unit (45) having second array data (DM) stored therein to be used for correction of the output values from of the plurality of pixels (Figs. 19, 28; paras. 0115-0117, 0178-0180); and
a flaw extraction unit configured to extract an output value (S0 x 4) and a position (DM) of a flaw pixel from the first array data (Figs. 19, 28; paras. 0115-0117, 0178-0180);
an array generation unit configured to generate third array data (NM*S0 x 4) based on the second array data (DM) and the output value (S0) and the position (DM) of the flaw pixel, the third array data being estimated flaw array data (Fig. 19; para. 0117; the logical inversion matrix NM is obtained by logically inverting "0" and "1" of the defective position matrix DM); and
a correction unit having a calculation unit configured to correct an output value of at least one pixel of the plurality of pixels based on the first array date and the third array data (Fig. 19; paras. 0127-0135).
Regarding claim 2, Kishima teaches the processing apparatus according to claim 1, wherein the second array data includes at least three pieces of data, and wherein one-dimensional data corresponding to at least one row or one column of the second array data has a peak value or a bottom value at a center (Figs. 19, 21).
Regarding claim 3, Kishima teaches the processing apparatus according to claim 2, wherein the one-dimensional data has a distribution monotonously changing from the peak value or the bottom value toward data ends (Figs. 19, 21).
Regarding claim 4, Kishima teaches the processing apparatus according to claim 2, wherein different one-dimensional data that shares the peak value or the bottom value of the one-dimensional data, and is arrayed in a direction intersecting with the one-dimensional data has a distribution monotonously changing from a peak value or a bottom value of the different one-dimensional data toward data ends (Figs. 19, 21).
Regarding claim 5, Kishima teaches the processing apparatus according to claim 1, wherein the first array data includes data of N rows and M columns, where one of the N and the M is an integer larger than or equal to 2, and the other one of the N and the M is an integer larger than or equal to 1 (Figs. 19, 21).
Regarding claim 6, Kishima teaches the processing apparatus according to claim 1, wherein the second storage unit has a plurality of types of the second array data stored therein, and wherein the array generation unit is configured to select a type of the second array data to be used in accordance with an environment in which image capturing is performed (Figs. 19, 21, 28; paras. 0114-0117).
Regarding claim 7, Kishima teaches the processing apparatus according to claim 1, wherein the third array data is generated by multiplication of the second array data and array data generated based on the output value of the flaw pixel (Fig. 19).
Regarding claim 8, Kishima teaches the processing apparatus according to claim 1, wherein the flaw extraction unit extracts the flaw pixel based on address data of the flaw pixel that has been acquired in advance (Figs. 19, 21, 28; paras. 0114-0117).
Regarding claim 9, Kishima teaches the processing apparatus according to claim 1, wherein, in a case where a difference between an output value of a first pixel and an output value of a second pixel adjacent to the first pixel is larger than or equal to a fixed threshold value, the flaw extraction unit determines the first pixel or the second pixel to be the flaw pixel (paras. 0082-0085, 0091).
Regarding claim 11, Kishima teaches the processing apparatus according to claim 1, wherein the flaw extraction unit determines a pixel having the output value that is larger than or equal to a fixed threshold value, to be the flaw pixel (paras. 0062, 0082-0085, 0091).
Regarding claim 13, Kishima teaches the processing apparatus according to claim 1, wherein the correction unit includes a nonlinear correction unit configured to perform nonlinear correction of the first array data (Fig. 28; para. 0173; gamma correction).
Regarding claim 16, Kishima teaches the processing apparatus according to claim 1, wherein the correction unit includes a demosaicing unit (as a subsequent unit of the calculation unit (Fig. 28; para. 0181).
Regarding claim 17, Kishima teaches the processing apparatus according to claim 1, wherein, based on address data of the flaw pixel or an output value of the flaw pixel that has been extracted from the output values of the plurality of pixels in a first frame, correction of output values of the plurality of pixels in a second frame acquired later than the first frame is performed (Figs. 19, 28).
Regarding claim 20, Kishima teaches the processing apparatus according to claim 1, wherein, after an output value of a surrounding pixel provided in a neighborhood of the flaw pixel has been corrected by the calculation unit, an output value of the flaw pixel is corrected based on the corrected output value of the surrounding pixel (Figs. 19, 28).
Regarding claim 22, Kishima teaches A photoelectric conversion system comprising:
the processing apparatus according to claim 1; and the plurality of pixels configured to output the first array data (Figs. 19, 28).
Claim(s) 1 and 20-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aldrich et al (US 8310570 B1).
Regarding claim 1, Aldrich teaches A processing apparatus (Figs. 1-5) comprising:
a first storage unit (delay line 300) for storing first array data (A-I) that is based on output values of a plurality of pixels arranged in an array (Fig. 3);
a second storage unit (memory 150) having second array data (pixel repair information 115) stored therein to be used for correction of the output values from of the plurality of pixels (Fig. 1; col. 5); and
a flaw extraction unit configured to extract an output value (C, D, E, F, or G) and a position (dead pixel LUT 110) of a flaw pixel from the first array data (Fig. 3);
an array generation unit configured to generate third array data (repair equations or instructions from TABLE 2) based on the second array data (pixel repair information 115) and the output value and the position of the flaw pixel, the third array data being estimated flaw array data (Fig. 3; cols. 5-6); and
a correction unit having a calculation unit configured to correct an output value of at least one pixel of the plurality of pixels based on the first array date and the third array data (Fig. 3; cols. 5-6).
Regarding claim 20, Aldrich teaches the processing apparatus according to claim 1, wherein, after an output value of a surrounding pixel provided in a neighborhood of the flaw pixel has been corrected by the calculation unit, an output value of the flaw pixel is corrected based on the corrected output value of the surrounding pixel (Figs. 1-5).
Regarding claim 21, Aldrich teaches the processing apparatus according to claim 1, wherein the flaw extraction unit is configured to extract the flaw pixel by pattern matching (Fig. 3; cols. 5-6; patterns as shown in TABLE 2).
Regarding claim 22, Aldrich teaches A photoelectric conversion system comprising:
the processing apparatus according to claim 1; and the plurality of pixels configured to output the first array data (Figs. 1-5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kishima (US 20140016005 A1) or Aldrich et al (US 8310570 B1) in view of Silverstein et al (US 20180007241 A1).
Regarding claim 10, Kishima/Aldrich teaches everything as claimed in claim 1, but fails to teach
wherein, in a case where a ratio between an output value of a first pixel and an output value of a second pixel adjacent to the first pixel is larger than or equal to a fixed threshold value, the flaw extraction unit determines the first pixel or the second pixel to be the flaw pixel.
However, in the same field of endeavor Silverstein teaches
wherein, in a case where a ratio between an output value of a first pixel and an output value of a second pixel adjacent to the first pixel is larger than or equal to a fixed threshold value, the flaw extraction unit determines the first pixel or the second pixel to be the flaw pixel (paras. 0068-0069; evaluating the criteria involves computing a ratio that quantifies how the pixel value is different from neighboring pixel values, comparing the computed ratio to a corresponding threshold value, and determining if the pixel is defective if the computed ratio is larger than the corresponding threshold value).
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Silverstein in Kishima/Aldrich to have wherein, in a case where a ratio between an output value of a first pixel and an output value of a second pixel adjacent to the first pixel is larger than or equal to a fixed threshold value, the flaw extraction unit determines the first pixel or the second pixel to be the flaw pixel for utilizing different detection criteria for detecting multiple defective pixel so that better image quality can be obtained by correcting all possible detectable defective values yielding a predicted result.
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Aldrich et al (US 8310570 B1) in view of Yanof et al (US 20060221214 A1).
Regarding claim 12, Aldrich teaches everything as claimed in claim 1, but fails to teach
further comprising, as a preceding unit of the first storage unit, a gain adjustment unit configured to apply a digital gain to the output values of the plurality of pixels.
However, in the same field of endeavor Yanof teaches
further comprising, as a preceding unit of the first storage unit, a gain adjustment unit configured to apply a digital gain to the output values of the plurality of pixels (Fig. 2; para. 0029; gain stage 202 before bad pixel replacement 206).
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Yanof in Aldrich to have further comprising, as a preceding unit of the first storage unit, a gain adjustment unit configured to apply a digital gain to the output values of the plurality of pixels for automatic exposure control and white balancing improving image quality yielding a predicted result.
Regarding claim 13, Aldrich teaches everything as claimed in claim 1, but fails to teach
wherein the correction unit includes a nonlinear correction unit configured to perform nonlinear correction of the first array data.
However, in the same field of endeavor Yanof teaches
wherein the correction unit includes a nonlinear correction unit configured to perform nonlinear correction of the first array data (Fig. 2; para. 0029; gamma correction).
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Yanof in Aldrich to have wherein the correction unit includes a nonlinear correction unit configured to perform nonlinear correction of the first array data for improving the contrast of the image yielding a predicted result.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Aldrich et al (US 8310570 B1) in view of Takayama et al (US 6683643 B1).
Regarding claim 18, Aldrich teaches everything as claimed in claim 1, but fails to teach
wherein, whether to execute the correction in the calculation unit is selected in accordance with a signal level of a subject or a temperature of the plurality of pixels.
However, in the same field of endeavor Takayama teach
wherein, whether to execute the correction in the calculation unit is selected in accordance with a signal level of a subject or a temperature of the plurality of pixels (col. 9, lines 18-48).
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Takayama in Aldrich to have wherein, whether to execute the correction in the calculation unit is selected in accordance with a signal level of a subject or a temperature of the plurality of pixels for controlling the number of defective pixel determining and correction based on image sensor temperature and image signal level so that image quality can be improved yielding a predicted result.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Aldrich et al (US 8310570 B1) in view of Sasaki et al (US 20190327424 A1).
Regarding claim 23, Aldrich teaches everything as claimed in claim 22, but fails to teach
wherein each of the plurality of pixels includes an avalanche photodiode.
However, in the same field of endeavor Sasaki teaches
wherein each of the plurality of pixels includes an avalanche photodiode (paras. 0002, 0030, 0037, 0039).
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Sasaki in Aldrich to have wherein each of the plurality of pixels includes an avalanche photodiode for utilizing a highly sensitive sensor for superior sensitivity and signal to noise ratio yielding a predicted result.
Allowable Subject Matter
Claims 14, 15 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if overcame the nonstatutory double patenting rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Quan Pham whose telephone number is (571)272-4438. The examiner can normally be reached Mon-Fri 9am-7pm.
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/Quan Pham/Primary Examiner, Art Unit 2637
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