DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to Applicant's communication filed March 13, 2026 in response to the Office action dated December 18,2025.
Claims 1-20 are pending.
Terminal Disclaimer
The terminal disclaimer filed on 3/13/26 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of 12175127 has been reviewed and is accepted. The terminal disclaimer has been recorded.
NOTE:
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art reference and any interpretations of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim.
Regarding claim 1, Kim teaches a memory device, comprising: one or more memory arrays (Fig.1, Para31-34 "The memory cells in the memory device 110 are used to store data and may be arranged in a memory cell Array"); and one or more controllers coupled with the one or more memory arrays and configured to cause the memory device to: receive, at the memory device, an indication of one or more parameters for monitoring access commands at the memory device (Fig.5-8; memory controller monitors read command count and write command count; Para149-155 "FIG. 8 illustrates an example of monitoring a command received from a host during a target time period TAR_Period by a memory system 100 according to embodiments of the present disclosure");
receive, at the memory device, one or more access commands to access the one or more memory arrays(Fig.1, 8,15,Para140-147, 151-152 "the memory system 100 has received, during the target time period TAR_Period, the read command R_CMD[0, 1] for the logical block addresses LBA 0 and LBA 1 once, the read command R_CMD[2] for the logical block address LBA 2 the "a" times, and the write command W CMD[ 4, 5] for logical block addresses LBA 4 and LBA 5 the "b" times");
modify, in accordance with the indicated one or more parameters, a respective value of one or more fields of a register of the memory device in response to receiving the one or more access commands(Fig.5,6,7,8 Para122-125;140-147-"the memory controller 120 may increment the write command count for the corresponding logical block address LBA from 11 to 12" increment read/write command count corresponds to modifying);.
However, Kim fails to teach but Lee teaches transmit, from the memory device, an indication of the respective value of at least one of the one or more fields of the register (Fig.1A,B,8; send updated read count and L2P map to host Para9-10 "the controller may read first data from a first block corresponding to the first physical address and sends a response to the read col11111and to the host, the response including the first data and updated information relating to the first read count."Para50-51, 113-114).
Kim and Lee are analogous art because they are from the same field of endeavor. They both relate to data management in a storage system.
Therefore, before the effective filling date of claimed invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by Kim, and incorporating the data transfer method to host, as taught by Lee.
One of ordinary skill in the art would have been motivated to do this modification in order to utilize more efficient approach of data management, as suggested by Lee (Para3-7).
Regarding claim 2, the combination of Kim and Lee teaches all the limitations of the base claims as outlined above.
Further, Kim teaches wherein: the one or more parameters indicate a threshold quantity of access operations; and the one or more controllers are configured to cause the memory device to modify the respective value of one or more fields of the register based on a quantity of access operations associated with the one or more access commands satisfying the indicated threshold quantity of access operations(Fig.6 Para140-142 "Since the read command count for the logical block address LBA 0 and LBA 1 is 53 or greater, which is the first threshold count 1 st_Threshold, the memory controller 120 may determine the data type of data corresponding to the corresponding logical block address LBA as the read-intensive type R_Intensive").
Regarding claim 3, the combination of Kim and Lee teaches all the limitations of the base claims as outlined above.
Further, Kim teaches wherein: the one or more parameters indicate one or more types of access operation; and the one or more controllers are configured to cause the memory device to modify the respective value of one or more fields of the register based on at least one of the one or more access commands corresponding to the indicated one or more types of access operation(Fig.6,7; Para140-147 read and write operation) .
Regarding claim 4, the combination of Kim and Lee teaches all the limitations of the base claims as outlined above.
Further, Kim teaches wherein: the one or more parameters indicate a range of addresses; and the one or more controllers are configured to cause the memory device to modify the respective value of one or more fields of the register based on at least one of the one or more access commands being within the indicated range of addresses.(Fig.6,7,8 Para140-147-"the memory controller 120 may increment the write command count for the corresponding logical block address LBA from 11 to 12" increment read/write command count corresponds to modifying parameters)
Regarding claim 5, the combination of Kim and Lee teaches all the limitations of the base claims as outlined above.
Further, Kim teaches wherein: the one or more parameters indicate a quantity of mapping functions associated with the register; and the one or more controllers are configured to cause the memory device to modify the respective value of one or more fields of the register is based on the indicated quantity of mapping functions(Fig.6,7,8 Para140-147).
Regarding claim 6, the combination of Kim and Lee teaches all the limitations of the base claims as outlined above.
Further, Kim teaches wherein: the one or more parameters indicate a size of the register; and the one or more controllers are configured to cause the memory device to configure the register in accordance with the indicated size of the register(Fig.6,7,8 Para140-147).
Regarding claim 7, the combination of Kim and Lee teaches all the limitations of the base claims as outlined above.
Further, Kim teaches wherein, for at least one of the one or more access commands, the one or more controllers are configured to cause the memory device to modify respective values of multiple fields of the register(Fig.6,7,8 Para140-147).
Regarding claim 8, the combination of Kim and Lee teaches all the limitations of the base claims as outlined above.
Further, Kim teaches wherein the one or more controllers are configured to cause the memory device to: receive, at the memory device, a command to monitor access operation occurrence; and modify the respective value of one or more fields of the register based on receiving the command(Fig.1, 8,15,Para140-147, 151-152).
Regarding claim 9, the combination of Kim and Lee teaches all the limitations of the base claims as outlined above.
Further, the combination teaches wherein the one or more controllers are configured to cause the memory device to: receive, at the memory device, a request for access operation monitoring information(Kim: Fig.1, 8,15,Para140-147, 151-152); and transmit, from the memory device, the indication of the respective value of at least one of the one or more fields of the register in response to receiving the request(Lee:Fig.1A,B,8; send updated read count and L2P map to host Para9-10 "the controller may read first data from a first block corresponding to the first physical address and sends a response to the read col11111and to the host, the response including the first data and updated information relating to the first read count."Para50-51, 113-114).
Regarding claim 10, the combination of Kim and Lee teaches all the limitations of the base claims as outlined above.
Further, Lee teaches wherein the one or more controllers are configured to cause the memory device to: transmit, from the memory device, the indication of the respective value of at least one of the one or more fields of the register based on the respective value satisfying a threshold(Fig.1A,B,8; send updated read count and L2P map to host Para9-10 "the controller may read first data from a first block corresponding to the first physical address and sends a response to the read col11111and to the host, the response including the first data and updated information relating to the first read count."Para50-51, 113-114).
Regarding claims 11-20, the combination of Kim and Lee teaches these claims according to the reasoning set forth in claims 1-10.
Response to Arguments
Applicant's arguments with respect to claims 1-20 have been considered and they are no persuasive.
Applicant argued prior art fails to teach “receive, at the memory device, an indication of one or more parameters for monitoring access commands at the memory device” and “modify, in accordance with the indicated one or more parameters, a respective value of one or more fields of a register of the memory device in response to receiving the one or more access commands.” The Examiner respectfully disagrees. The “parameters” are not further defined in the claim. Note that although the claims are interpreted in light of the specification, limitations appearing in the Specification but not being claimed are not read into the claims. See (MPEP 2111 [R-lD. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Kim teaches incrementing, i.e. modifying read count and write count based on logical block address, i.e. parameter received with the read/write command (Fig.5,6,7,8 Para140-147-"the memory controller 120 may increment the write command count for the corresponding logical block address LBA from 11 to 12" increment read/write command count corresponds to modifying).
Therefore, the combination of Kim and Lee renders these claim unpatentable.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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TASNIMA . MATIN
Primary Examiner
Art Unit 2135
/TASNIMA MATIN/Primary Examiner, Art Unit 2135
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