DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
NOTE:
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art reference and any interpretations of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Information Disclosure Statement
The references cited in the information disclosure statement (IDS) submitted on 2/4/25 and 6/11/25 have been considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-23 of U.S. Patent No.12175127. Although the claims at issue are not identical, they are not patentably distinct from each other because they contain similar subject matter according to table below. Only one claim is shown for illustrative purpose.
Instant Application
U.S. Patent No.12175127
1. A memory device, comprising: one or more memory arrays; and one or more controllers coupled with the one or more memory arrays and configured to cause the memory device to: receive, at the memory device, an indication of one or more parameters for monitoring access commands at the memory device; receive, at the memory device, one or more access commands to access the one or more memory arrays;
modify, in accordance with the indicated one or more parameters, a respective value of one or more fields of a register of the memory device in response to receiving the one or more access commands; and transmit, from the memory device, an indication of the respective value of at least one of the one or more fields of the register.
15. A memory device, comprising: one or more memory arrays; and one or more controllers coupled with the one or more memory arrays and configured to cause the memory device to: perform one or more access operations each associated with a respective address of a plurality of addresses of the memory device;
modify, for each access operation of the one or more access operations, in a register comprising a plurality of fields, a respective value of each field of a set of multiple fields of the plurality of fields that is associated with the respective address, wherein each field of the plurality of fields of the register is associated with a respective set of multiple addresses of the plurality of addresses; receive a request for information associated with access operation occurrence at the memory device; and transmit, based on the request for information, an indication of the respective value of at least one field of the plurality of fields.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et. al. U.S. Patent Pub No. 20230114493 (hereinafter Kim) in view of Lee et. al. US Patent Pub.No. 20210004167 (hereinafter Lee).
Regarding claim 1, Kim teaches a memory device, comprising: one or more memory arrays (Fig.1, Para31-34 "The memory cells in the memory device 110 are used to store data and may be arranged in a memory cell Array"); and one or more controllers coupled with the one or more memory arrays and configured to cause the memory device to: receive, at the memory device, an indication of one or more parameters for monitoring access commands at the memory device (Fig.5-8; memory controller monitors read command count and write command count; Para149-155 "FIG. 8 illustrates an example of monitoring a command received from a host during a target time period TAR_Period by a memory system 100 according to embodiments of the present disclosure");
receive, at the memory device, one or more access commands to access the one or more memory arrays(Fig.1, 8,15,Para140-147, 151-152 "the memory system 100 has received, during the target time period TAR_Period, the read command R_CMD[0, 1] for the logical block addresses LBA 0 and LBA 1 once, the read command R_CMD[2] for the logical block address LBA 2 the "a" times, and the write command W CMD[ 4, 5] for logical block addresses LBA 4 and LBA 5 the "b" times");
modify, in accordance with the indicated one or more parameters, a respective value of one or more fields of a register of the memory device in response to receiving the one or more access commands(Fig.6,7,8 Para140-147-"the memory controller 120 may increment the write command count for the corresponding logical block address LBA from 11 to 12" increment read/write command count corresponds to modifying parameters);.
However, Kim fails to teach but Lee teaches transmit, from the memory device, an indication of the respective value of at least one of the one or more fields of the register (Fig.1A,B,8; send updated read count and L2P map to host Para9-10 "the controller may read first data from a first block corresponding to the first physical address and sends a response to the read col11111and to the host, the response including the first data and updated information relating to the first read count."Para50-51, 113-114).
Kim and Lee are analogous art because they are from the same field of endeavor. They both relate to data management in a storage system.
Therefore, before the effective filling date of claimed invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by Kim, and incorporating the data transfer method to host, as taught by Lee.
One of ordinary skill in the art would have been motivated to do this modification in order to utilize more efficient approach of data management, as suggested by Lee (Para3-7).
Regarding claim 2, the combination of Kim and Lee teaches all the limitations of the base claims as outlined above.
Further, Kim teaches wherein: the one or more parameters indicate a threshold quantity of access operations; and the one or more controllers are configured to cause the memory device to modify the respective value of one or more fields of the register based on a quantity of access operations associated with the one or more access commands satisfying the indicated threshold quantity of access operations(Fig.6 Para140-142 "Since the read command count for the logical block address LBA 0 and LBA 1 is 53 or greater, which is the first threshold count 1 st_Threshold, the memory controller 120 may determine the data type of data corresponding to the corresponding logical block address LBA as the read-intensive type R_Intensive").
Regarding claim 3, the combination of Kim and Lee teaches all the limitations of the base claims as outlined above.
Further, Kim teaches wherein: the one or more parameters indicate one or more types of access operation; and the one or more controllers are configured to cause the memory device to modify the respective value of one or more fields of the register based on at least one of the one or more access commands corresponding to the indicated one or more types of access operation(Fig.6,7; Para140-147 read and write operation) .
Regarding claim 4, the combination of Kim and Lee teaches all the limitations of the base claims as outlined above.
Further, Kim teaches wherein: the one or more parameters indicate a range of addresses; and the one or more controllers are configured to cause the memory device to modify the respective value of one or more fields of the register based on at least one of the one or more access commands being within the indicated range of addresses.(Fig.6,7,8 Para140-147-"the memory controller 120 may increment the write command count for the corresponding logical block address LBA from 11 to 12" increment read/write command count corresponds to modifying parameters)
Regarding claim 5, the combination of Kim and Lee teaches all the limitations of the base claims as outlined above.
Further, Kim teaches wherein: the one or more parameters indicate a quantity of mapping functions associated with the register; and the one or more controllers are configured to cause the memory device to modify the respective value of one or more fields of the register is based on the indicated quantity of mapping functions(Fig.6,7,8 Para140-147).
Regarding claim 6, the combination of Kim and Lee teaches all the limitations of the base claims as outlined above.
Further, Kim teaches wherein: the one or more parameters indicate a size of the register; and the one or more controllers are configured to cause the memory device to configure the register in accordance with the indicated size of the register(Fig.6,7,8 Para140-147).
Regarding claim 7, the combination of Kim and Lee teaches all the limitations of the base claims as outlined above.
Further, Kim teaches wherein, for at least one of the one or more access commands, the one or more controllers are configured to cause the memory device to modify respective values of multiple fields of the register(Fig.6,7,8 Para140-147).
Regarding claim 8, the combination of Kim and Lee teaches all the limitations of the base claims as outlined above.
Further, Kim teaches wherein the one or more controllers are configured to cause the memory device to: receive, at the memory device, a command to monitor access operation occurrence; and modify the respective value of one or more fields of the register based on receiving the command(Fig.1, 8,15,Para140-147, 151-152).
Regarding claim 9, the combination of Kim and Lee teaches all the limitations of the base claims as outlined above.
Further, the combination teaches wherein the one or more controllers are configured to cause the memory device to: receive, at the memory device, a request for access operation monitoring information(Kim: Fig.1, 8,15,Para140-147, 151-152); and transmit, from the memory device, the indication of the respective value of at least one of the one or more fields of the register in response to receiving the request(Lee:Fig.1A,B,8; send updated read count and L2P map to host Para9-10 "the controller may read first data from a first block corresponding to the first physical address and sends a response to the read col11111and to the host, the response including the first data and updated information relating to the first read count."Para50-51, 113-114).
Regarding claim 10, the combination of Kim and Lee teaches all the limitations of the base claims as outlined above.
Further, Lee teaches wherein the one or more controllers are configured to cause the memory device to: transmit, from the memory device, the indication of the respective value of at least one of the one or more fields of the register based on the respective value satisfying a threshold(Fig.1A,B,8; send updated read count and L2P map to host Para9-10 "the controller may read first data from a first block corresponding to the first physical address and sends a response to the read col11111and to the host, the response including the first data and updated information relating to the first read count."Para50-51, 113-114).
Regarding claims 11-20, the combination of Kim and Lee teaches these claims according to the reasoning set forth in claims 1-10.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Brice et.al US20110320643 teaches tracking count and modifying PCI instruction.
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TASNIMA . MATIN
Primary Examiner
Art Unit 2135
/TASNIMA MATIN/Primary Examiner, Art Unit 2135