DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/07/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 11-15 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. U.S. Patent Publication No. 2021/0150977 (hereinafter Ryu) in view of Lee et al. U.S. Patent Publication No. 2024/0355279 (hereinafter Lee).
Consider claim 1, Ryu teaches a pixel circuit, comprising: a compensation circuit connected to a data line, a first gate line, and a second gate line (Figure 3, SWT11-13, SWT15, Cst, DL, Scan and EM), the compensation circuit being configured to receive first and second voltages alternately through the data line (Vdata in figure 4a and Vdata in figure 4b), a first gate signal through the first gate line, and a second gate signal through the second gate line (Figure 4a, Scan and Em); a light-emitting element (Figure 4a, ED); a driving element (Figure 4a, DRT) including a gate electrode configured to receive the second voltage via the compensation circuit, the driving element being configured to generate a current to drive the light-emitting element based on the second voltage (Figure 4B, Vdata); and a switch element including a gate electrode configured to receive the second gate signal via the compensation circuit (Figure 4a, SWT14 and EM via SWT13), the switch element being configured to switch a path of the current between the driving element and the light-emitting element based on the second gate signal (Figure 4a, SWT14 and Em), wherein the light-emitting element, the driving element, and the switch element are connected in series between a first power line and a second power line (Figure 4a, Vdd, DRT, SWT14, ED and Vss), the compensation circuit includes: a capacitor coupled between a first node and a second node (Figure 4a, Cst); a first switch element connected between the data line and the first node and configured to turn on in response to a gate-on voltage of the first gate signal to electrically connect the data line to the first node (Figure 4a, SWT11 and respective connections); a second switch element connected between the second node and a third node (Figure 4a, SWT12 and respective connections); a third switch element connected to the first node and configured to turn on in response to a gate-on voltage of the second gate signal to apply low first voltage to the first node (Figure 4a, SWT13 and respective connections); wherein low first voltage is constant voltage from a constant voltage line (Figure 4a, Vdata during P11), and wherein, during one horizontal period, the first switch element is configured to turn on to apply low first voltage from the constant voltage line via data line to the first node simultaneously with the third switch element being turned on to apply low first voltage to the first node (Figure 4a, Vdata (low-voltage), Vss (low-voltage) when SWT11 and SWT13 are ON during P11).
Ryu does not appear to specifically the first voltage from the same constant volage line.
However, in a related field of endeavor, Lee teaches a pixel circuit in figure 5 and further teaches the first voltage from the same constant voltage line (Figures 4-5, DL(Vref) during P1-P2).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective fling date of the claimed invention to provide a same constant voltage line as taught by Lee with the benefit that reference voltage VREF is applied to the first node N1 in the first period P1 and the second period P2, fluctuation of the first power supply voltage ELVDD due to the current is reduced as suggested in [0087].
Consider claim 2, Ryu and Lee teach all the limitations of claim 1. In addition, Ryu teaches the compensation circuit further includes: a fifth switch element connected to a fourth node and configured to turn on in response to the gate-on voltage of the first gate signal to apply the first voltage from the constant voltage line to the fourth node (Figure 4a, SWT15 and respective connections); the second switch element is configured to turn on in response to the gate-on voltage of the first gate signal to electrically connect the second node to the third node (Figure 4a, SWT12 and respective connections); the switch element includes a fourth switch element connected between the third node and the fourth node and configured to turn on in response to the gate-on voltage of the second gate signal to electrically connect the third node to the fourth node (Figure 4a, SWT14 and respective connections); the driving element includes a gate electrode connected to the second node, a first electrode connected to the first power line configured to receive a pixel driving voltage, and a second electrode connected to the third node (Figure 4a, DT and respective connections); the light-emitting element includes an anode electrode connected to the fourth node, and a cathode electrode connected to the second power line configured to receive a cathode voltage (Figure 4a, ED and respective connections); the first voltage is a reference voltage or the cathode voltage (Figure 4a, low voltage in Vdata or the cathode voltage Vss), and the second voltage is a data voltage of pixel data (Figure 4b, Vdata during P12); and the data line is configured to receive the data voltage of pixel data after receiving the reference voltage or the cathode voltage (Figure 4a-b, Vdata during P11-P12).
Consider claim 11, Ryu and Lee teach all the limitations of claim 1. In addition, Ryu teaches wherein: the first voltage either a reference voltage from a reference voltage line or a cathode voltage from the second power line (Figure 4a, Vdata during P11); the second voltage is a data voltage corresponding to a pixel data (Figure 4b, Vdata during P12); and during the one horizontal period, the first switch element is further configured to receive the first voltage through the data line and then to receive the second voltage through the data line (Figures 4a-b, SWT11, P11 and P12).
Consider claim 12, Ryu and Lee teach all the limitations of claim 11. In addition, Ryu and Lee teach wherein: the one horizontal period includes a horizontal blank period and a horizontal active period; during the horizontal blank period, the first switch element is further configured to receive the first voltage, and not the second voltage, through the data line (Figure 4a, Vdata during P11) and to apply the first voltage from the constant voltage line to the first node simultaneously with the third switch element being turned on to apply to the first voltage from the constant voltage line to the first node (Figure 4a, SWT11 and SWT13. Lee’s figure 4-5, DL/Vref, see motivation to combine in claim 1); and during the horizontal active period, the first switch element is further configured to receive the second voltage through the data line to write the pixel data to the pixel circuit (Figure 4b, Vdata during P12).
Consider claim 13, Ryu and Lee teach all the limitations of claim 11. In addition, Ryu teaches wherein: the one horizontal period includes a horizontal blank period and a horizontal active period; during the horizontal blank period, the first gate signal and the second gate signal are at a gate-on voltage (Figure 4a, Scan and EM during P11); and during the horizontal active period, the first gate signal is at the gate-on voltage, and the second gate signal is at a gate-off voltage (Figure 4b, Scan and EM during P12).
Consider claim 14, Ryu and Lee teach all the limitations of claim 1. In addition, Ryu teaches a display device, comprising: a display panel including a plurality of data lines, a plurality of gate lines (Figure 1, GL and DL), a plurality of power lines (Figure 3, Vdd and Vss), and a plurality of pixel circuits (Figure 1, SP), at least one of the pixel circuits being the pixel circuit of claim 1 (Figure 3); a data driver configured to output the first and second voltages (Figure 1, 130); a gate driver configured to supply at least one gate signal to the gate lines (Figure 1, 120); and a control circuit configured to control the data driver and the gate driver (Figure 1, 140), wherein the plurality of data lines include the data line (Figure 3, DL), the plurality of gate lines include the first gate line and the second gate line, the at least one gate signal includes the first gate signal and the second gate signal (Figure 3, Scan and Em), and the plurality of power lines include the first power line and the second power line (Figure 3, Vdd and Vss).
Consider claim 15, Ryu and Lee teach all the limitations of claim 14. In addition, Ryu teaches wherein: the compensation circuit further includes: a fifth switch element connected to a fourth node and configured to turn on in response to the gate-on voltage of the first gate signal to apply the first voltage from the constant voltage line to the fourth node (Figure 4a, SWT15 and respective connections); the second switch element is configured to turn on in response to the gate-on voltage of the first gate signal to electrically connect the second node to the third node (Figure 4a, SWT12 and respective connections); the switch element includes a fourth switch element connected between the third node and the fourth node and configured to turn on in response to the gate-on voltage of the second gate signal to electrically connect the third node to the fourth node (Figure 4a, SWT14 and respective connections); the driving element includes a gate electrode connected to the second node, a first electrode connected to the first power line configured to receive a pixel driving voltage, and a second electrode connected to the third node (Figure 4a, DRT and respective connections); the light-emitting element includes an anode electrode connected to the fourth node, and a cathode electrode connected to the second power line configured to receive a cathode voltage (Figure 4a, ED and respective connections); and the first voltage includes a reference voltage or the cathode voltage Figure 4a, low voltage in Vdata or the cathode voltage Vss) and the second voltage includes a data voltage of pixel data (Figure 4b, Vdata during P12).
Consider claim 22, Ryu and Lee teach all the limitations of claim 1. In addition, Lee teaches wherein: either the first voltage is a constant reference voltage from a reference voltage line, the reference voltage line being the constant voltage line (Figures 4-5, DL/Vref during P1-P2, see motivation to combine in claim 1); or the first voltage is a cathode voltage from the second power line, the second power line being the constant voltage line.
Claim(s) 3-10, 16, 17 and 19-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryu and Lee as applied to claim 2 above, and further in view of Kim et al. U.S. Patent Publication No. 2014/0084805 (hereinafter Kim).
Consider claim 3, Ryu and Lee teach all the limitations of claim 2. In addition, Ryu teaches wherein during the one horizontal period, the first node is configured to receive the reference voltage simultaneously via the data line and the first switch element as via the third switch element (Figure 4a, SWT11 and SWT13 are ON during P11).
Ryu does not appear to specifically disclose the reference voltage is a constant voltage greater than the cathode voltage and smaller than the pixel driving voltage.
However, Kim teaches the reference voltage is a constant voltage greater than the cathode voltage and smaller than the pixel driving voltage ([0054], the reference voltage (Vref) may be the voltage value which is not less than 0V and is less than 2V).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a particular voltage as taught by Kim the benefit the reference voltage (Vref) may be the voltage value which is not less than 0V and is less than 2V as suggested in [0054]. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art.
Consider claim 4, Ryu, Lee and Kim teach all the limitations of claim 3. In addition, Ryu teaches wherein the second node, the third node, and the fourth node are configured to receive the reference voltage when the reference voltage is applied to the first node (Figure 4a, N11-N14).
Consider claim 5, Ryu, Lee and Kim teach all the limitations of claim 3. In addition, Ryu teaches wherein: a driving period of the pixel circuit includes a first phase in which the pixel circuit is configured to be initialized (Figure 4a, P11), a second phase in which the capacitor is configured to receive a threshold voltage of the driving element and the data voltage (Figure 4b, P12), and a third phase in which the light-emitting element is configured to emit light (Figure 4d, P14); the first gate signal is configured to be at the gate-on voltage of the first gate signal in the first phase and the second phase, and at a gate-off voltage of the first gate signal in the third phase (Figures 4a-b,d, Scan); the second gate signal is configured to be at a gate-off voltage of the second gate signal in the second phase, and at the gate-on voltage of the second gate signal in the first and third phases (Figures 4a-b,d, EM); the first, second, and fifth switch elements are configured to turn on in response to the gate-on voltage of the first gate signal and to turn off in response to the gate-off voltage of the first gate signal (Figures 4a-b,d, SWT11-12,15); the third and fourth switch elements are configured to turn on in response to the gate-on voltage of the second gate signal and to turn off in response to the gate-off voltage of the second gate signal (Figures 4a-b,d, SWT13-14); the one horizontal period includes periods of the first phase and the second phase (Figures 4a-b,d, P11 and P12); and the data line is configured to be at the reference voltage in the first phase (Figure 4a, Vdata (low voltage) during P11) and at the data voltage in the second phase (Figure 4a, Vdata during P12).
Consider claim 6, Ryu, Lee and Kim teach all the limitations of claim 5. In addition, Ryu teaches wherein: the first switch element includes a gate electrode configured to receive the first gate signal, a first electrode connected to the data line, and a second electrode connected to the first node (Figure 4a, SWT11 and respective connections); the second switch element includes a gate electrode configured to receive the first gate signal, a first electrode connected to the second node, and a second electrode connected to the third node (Figure 4a, SWT12 and respective connections); the third switch element includes a gate electrode configured to receive the second gate signal, a first electrode connected to the first node, and a second electrode configured to receive the reference voltage (Figure 4a, SWT13 and respective connections); the fourth switch element includes a gate electrode configured to receive the second gate signal, a first electrode connected to the third node, and a second electrode connected to the fourth node (Figure 4a, SWT14 and respective connections); and the fifth switch element includes a gate electrode configured to receive the first gate signal, a first electrode configured to receive the reference voltage, and a second electrode connected to the fourth node (Figure 4a, SWT15 and respective connections).
Consider claim 7, Ryu and Lee teach all the limitations of claim 2. In addition, Ryu teaches wherein during one horizontal period, the first node is configured to receive the low voltage simultaneously via the data line and the first switch element as via the third switch element (Figure 4a, Vdata (low-voltage), Vss (low-voltage) when SWT11 and SWT13 are ON during P11).
Ryu does not appear to specifically disclose cathode voltage via the data line.
However, in a related field of endeavor, Kim teaches a pixel circuit (abstract) and further teaches cathode voltage via the data line ([0054] and figure 2, vref may be ideally set to 0V (see also DLi). [0065] and figure 2, V2 for example 0V (see also PL2 or cathode of OLED)).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a cathode voltage via the data line with the benefit that the reference voltage (Vref) is set to a predetermined voltage value which is lower than that of a driving voltage of the light emitting device (OLED). In addition, 0V is ideal reference voltage according to [0054].
Consider claim 8, Ryu, Lee and Kim teach all the limitations of claim 7. In addition, Ryu teaches wherein the second node, the third node, and the fourth node are configured to receive the cathode voltage when the cathode voltage is applied to the first node (Figure 4a, N11-N14 and Vss).
Consider claim 9, Ryu, Lee and Kim teach all the limitations of claim 7. In addition, Ryu teaches wherein: a driving period of the pixel circuit includes a first phase in which the pixel circuit is configured to be initialized, a second phase in which the capacitor is configured to receive a threshold voltage of the driving element and the data voltage, and a third phase in which the light-emitting element is configured to emit light (Figures 4a-b,d, P11, P12 and P14); the first gate signal is configured to be at the gate-on voltage of the first gate signal in the first phase and the second phase, and at a gate-off voltage of the first gate signal in the third phase(Figures 4a-b, d, Scan) the second gate signal is configured to be at a gate-off voltage of the second gate signal in the second phase, and at the gate-on voltage of the second gate signal in the first and third phases (Figures 4a-b, d, EM); the first, second, and fifth switch elements are configured to turn on in response to the gate-on voltage of the first gate signal and to turn off in response to the gate-off voltage of the first gate signal (Figures 4a-b,d, SWT11-12, SWT15); the third and fourth switch elements are configured to turn on in response to the gate-on voltage of the second gate signal and to turn off in response to the gate-off voltage of the second gate signal (Figures 4a-b,d, SWT13-14); the one horizontal period includes periods of the first phase and the second phase (Figures 4a-b,d, P11-P12); and the data line is configured to be at the low voltage in the first phase (Figure 4a, Vdata during P11) and at the data voltage in the second phase (Figure 4a, Vdata during P12). In addition, Kim teaches the data line is configured to be at the cathode voltage in the first phase ([0054] and figure 2, vref may be ideally set to 0V (see also DLi). [0065] and figure 2, V2 for example 0V (see also PL2 or cathode of OLED), see motivation to combine in claim 7).
Consider claim 10, Ryu, Lee and Kim teach all the limitations of claim 9. In addition, Ryu teaches wherein: the first switch element includes a gate electrode configured to receive the first gate signal, a first electrode connected to the data line, and a second electrode connected to the first node (Figure 4a, SWT11 and respective connections); the second switch element includes a gate electrode configured to receive the first gate signal, a first electrode connected to the second node, and a second electrode connected to the third node (Figure 4a, SWT12 and respective connections); the third switch element includes a gate electrode configured to receive the second gate signal, a first electrode connected to the first node, and a second electrode configured to receive the cathode voltage (Figure 4a, SWT13 and respective connections); the fourth switch element includes a gate electrode configured to receive the second gate signal, a first electrode connected to the third node, and a second electrode connected to the fourth node (Figure 4a, SWT14 and respective connections); and the fifth switch element includes a gate electrode configured to receive the first gate signal, a first electrode configured to receive the cathode voltage, and a second electrode connected to the fourth node (Figure 4a, SWT15 and respective connections).
Consider claim 16, Ryu and Lee teach all the limitations of claim 14. In addition, Ryu teaches the control circuit is configured to transmit digital signal ([0037], suggests image data from the controller 140 and converts the image data into an analog data voltage and thus data is received in digital form).
Ryu does not appear to specifically disclose wherein: the control circuit is configured to transmit initialization data to the data driver as a digital signal; and the data driver is configured to output the first voltage in response to the initialization data.
However, Kim teaches wherein: the control circuit is configured to transmit initialization data to the data driver as a signal (Figure 10 and [0134], the data driver 400 alternately supplies the predetermined reference voltage (Vref) and the data voltage (Vdata) to the corresponding data line (DL1 to DLm) during each horizontal period overlapped with the first switching control signal according to the data timing control signal (DTCS) supplied from the timing controller 200); and the data driver is configured to output the first voltage in response to the initialization data [0134].
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to output first voltage in response to initialization data as taught by Kim with the benefit that the data driver 400 generates the predetermined reference voltage (Vref) and supplies the generated reference voltage (Vref) to the corresponding data line (DL1 to DLm) during the partial period for each horizontal period (or the first half period) according to the data timing control signal (DTCS).
Consider claim 17, Ryu, Lee and Kim teach all the limitations of claim 16. In addition, Kim teaches wherein: the control circuit is configured to update the initialization data every horizontal period (Figure 3, DL. Figure 10 and [0134], the data driver 400 alternately supplies the predetermined reference voltage (Vref) and the data voltage (Vdata) to the corresponding data line (DL1 to DLm) during each horizontal period overlapped with the first switching control signal according to the data timing control signal (DTCS) supplied from the timing controller 200); and the first voltage has a voltage level corresponding to the initialization data [0134], see motivation to combine in claim 16.
Consider claim 19, Ryu and Lee teach all the limitations of claim 14.
Ryu does not appear to specifically disclose a switch circuit configured to alternately select one of the first voltage and the second voltage and to supply the selected one of the first voltage and the second voltage to the data lines.
However, Kim teaches a switch circuit connected to the constant voltage line and a data output channel of the data driver ([0134] and figure 10, the plurality of output voltage selectors are switched by the half unit for each horizontal period according to a data output selecting signal of the data timing control signal (DTCS) supplied from the timing controller 200, whereby the reference voltage (Vref) is output during the partial period for each horizontal period (or the first half period), and the data voltage (Vdata) is output during the remaining period for each horizontal period (or the last half period)), the switch circuit being configured to alternately select one of the first voltage from the constant voltage line and the second voltage from the data output channel and to supply the selected one of the first voltage and the second voltage to the data line ([0134], the plurality of output voltage selectors are switched by the half unit for each horizontal period according to a data output selecting signal of the data timing control signal (DTCS) supplied from the timing controller 200, whereby the reference voltage (Vref) is output during the partial period for each horizontal period (or the first half period), and the data voltage (Vdata) is output during the remaining period for each horizontal period (or the last half period). Figure 10, Vref or Vdata).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a switch circuit or selector so as to alternately output the predetermined reference voltage (Vref) and the data voltage (Vdata) for each horizontal period as suggested in [0134].
Consider claim 20, Ryu, Lee and Kim teach all the limitations of claim 19. In addition, Kim teaches wherein the switch circuit is further configured to select and supply the first voltage from the constant voltage line to the data line ([0134] and figure 2) and then to select and supply to second voltage from the data output channel to the data line within the one horizontal period ([0134] and figure 2), see motivation to combine in claim 19.
Consider claim 21, Ryu and Lee teach all the limitations of claim 1. In addition, Ryu teaches the first power line is configured to supply a pixel driving voltage, and the second power line is configured to supply a cathode voltage (Figure 4a, Vdd and Vss).
Ryu does not appear to specifically disclose the first voltage is a reference voltage greater than the cathode voltage.
However, Kim teaches the first voltage is a reference voltage greater than the cathode voltage ([0054], the reference voltage (Vref) may be the voltage value which is not less than 0V and is less than 2V).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a particular voltage as taught by Kim the benefit the reference voltage (Vref) may be the voltage value which is not less than 0V and is less than 2V as suggested in [0054]. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryu and Lee as applied to claim 14 above, and further in view of Ahn et al. U.S. Patent Publication No. 2020/0211437 (hereinafter Ahn).
Consider claim 18, Ryu and Lee teach all the limitations of claim 14.
Ryu does not appear to specifically disclose wherein the display panel includes: a plurality of circuit parts in which the pixel circuits are disposed; and a plurality of stretchable wires electrically connecting the plurality of circuit parts, and wherein the stretchable wires include the data lines, the gate lines, and the power lines.
However, in a related field of endeavor, Ahn teaches a stretchable display panel (abstract) and further teaches wherein the display panel includes: a plurality of circuit parts in which the pixel circuits are disposed (Figure 1, 112); and a plurality of stretchable wires electrically connecting the plurality of circuit parts (Figure 1, 180), and wherein the stretchable wires include the data lines, the gate lines, and the power lines [0070].
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a stretchable wires and display as taught by Ahn with the benefit that the shape of the stretchable display device may be freely changed in accordance with operation by the user such as bending or stretching the stretchable display device. For example, when a user holds and pulls an end of a stretchable display device, the stretchable display device may be stretched by the force of the user. Alternatively, when a user puts a stretchable display device on an uneven wall, the stretchable display device may be disposed to be bent in the surface shape of the wall. Further, when the force applied by a user is removed, a stretchable display device may return into the initial shape as suggested in [0055].
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument (see new reference Lee).
Conclusion
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621
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