DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/14/2024, 04/18/2025, 05/30/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16 are rejected under 35 U.S.C. 102(b)(1) as anticipated by Kim (KR 102475066 B1, see attached EPO translation also) or, in the alternative, under 35 U.S.C. 103 as obvious over Kim (KR 102475066 B1, see attached EPO translation also) in view of Jeong (US 2025/0061940 A1).
Regarding claim 1, Kim teaches a universal logic memory cell (Fig. 4A, [0110] logic-in-memory cell 400), comprising a first network device and a second network device using a plurality of triple-gate silicon devices ([0110] triple gate feedback memory devices 401),
wherein each of the triple-gate silicon devices (Fig. 1a, 100, [0058]) comprises a drain region ([0060] a drain region 101), a channel region (102), and a source region (103);
a supply voltage is applied to the drain region and the source region ([0112] drain/source voltages applied);
a gate region on which first and second programming gate electrodes (108) and a control gate electrode (107, [0019]) are formed is formed on the channel region;
depending on a level of a program voltage (VPG) applied through the first and second programming gate electrodes, the channel region under the first and second programming gate electrodes operates in one of a first channel mode and a second channel mode ([0019] a first channel operation and a second channel operation according to the level of Vpg, [0020]); and
the triple-gate silicon device is determined to be in either an on-state or an off-state based on a level of a control voltage (VCG) applied through the control gate electrode ([0021] OFF state, [0022] ON state), and
the first and second network devices perform a logic operation function ([0112] logic operation function) and a memory function ([0105] memory function) by determining a level of an output voltage (VOUT) as one of a positive level, a zero level, and a negative level depending on any one of the states in any one of the channel modes (Figs. 4a, 4b, 5a, 5b).
Kim does not explicitly teach the first and second network devices perform a ternary logic operation function.
However, this limitation appears to be merely a statement of intent of the memory cell apparatus. It has been held that a recitation directed to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114.II also.
However, if the limitation regarding the ternary logic operation function is not considered a mere limitation of intended use, Jeong teaches an apparatus that performs a ternary logic operation function (Figs. 3 and 4).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to have provided the logic memory cell apparatus of Kim for a ternary logic operation function in view of Jeong as a ternary logic operation function is well-known in the art for its advantages over binary operation (Jeong, Background).
Regarding claim 2, all the limitations of claim 1 are taught by Kim.
Kim further teaches the universal logic memory cell, wherein the first and second network devices are composed of a first parallel connection formed by connecting common drain regions between a first serial connection in which the drain regions and source regions of two of the four triple-gate silicon devices are connected in series (Fig. 4a, parallel-serial connection of 4 of 401s between Vdd and 402) and a second serial connection in which the drain regions and source regions of the remaining two triple-gate silicon devices are connected in series and a second parallel connection formed by connecting common source regions therebetween (Fig. 4a, parallel-serial connection of 4 of 401s between 402 and Vss), a drain voltage (VDD) of the common voltage is applied through the first parallel connection of the first network device (Fig. 4a, Vdd), a source voltage (VSS) of the common voltage is applied through the second parallel connection of the second network device (Fig. 4a, Vss), and an output voltage (VOUT) is measured at a point where the second parallel connection of the first network device and the first parallel connection of the second network device are connected (Fig. 4a, 402).
Regarding claim 3, all the limitations of claim 2 are taught by Kim.
Kim further teaches the universal logic memory cell, wherein the first network device operates in the second channel mode (Fig. 5a, 501) and the second network device operates in the first channel mode (Fig. 5a, 502).
Kim does not explicitly teach the universal logic memory cell, wherein the ternary logic operation function of determining a level of the output voltage (VOUT) as a positive level when a level of the control voltage (VCG) is a negative level, determining a level of the output voltage (VOUT) as a negative level when a level of the control voltage (VCG) is a positive level, and determining a level of the output voltage (VOUT) as a zero level when a level of the control voltage (VCG) is a zero level is performed.
However, this limitation appears to be merely a statement of intent of the memory cell apparatus. It has been held that a recitation directed to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114.II also.
However, if the limitation regarding the ternary logic operation function is not considered a mere limitation of intended use, Jeong teaches an apparatus that performs a ternary logic operation function (Figs. 3 and 4).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to have provided the logic memory cell apparatus of Kim for a ternary logic operation function in view of Jeong as a ternary logic operation function is well-known in the art for its advantages over binary operation (Jeong, Background).
Regarding claim 4, all the limitations of claim 2 are taught by Kim.
Kim further teaches the universal logic memory cell, wherein the first network device operates in the first channel mode (Fig. 6, 601) and the second network device operates in the second channel mode (Fig. 6, 602).
Kim does not explicitly teach the universal logic memory cell, wherein the ternary logic operation function of determining a level of the output voltage (VOUT) as a negative level when a level of the control voltage (VCG) is a negative level, determining a level of the output voltage (VOUT) as a positive level when a level of the control voltage (VCG) is a positive level, and determining a level of the output voltage (VOUT) as a zero level when a level of the control voltage (VCG) is a zero level is performed.
However, this limitation appears to be merely a statement of intent of the memory cell apparatus. It has been held that a recitation directed to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114.II also.
However, if the limitation regarding the ternary logic operation function is not considered a mere limitation of intended use, Jeong teaches an apparatus that performs a ternary logic operation function (Figs. 3 and 4).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to have provided the logic memory cell apparatus of Kim for a ternary logic operation function in view of Jeong as a ternary logic operation function is well-known in the art for its advantages over binary operation (Jeong, Background).
Regarding claim 5, all the limitations of claim 2 are taught by Kim.
Kim does not explicitly teach the universal logic memory cell, wherein the ternary logic operation function of determining a level of the output voltage (VOUT) as a positive level when the first network device operates in the second channel mode, the second network device operates in the first channel mode, a first control voltage (VIN1) of the control voltage (VCG) is applied to a left side of the first network device and an upper side of the second network device, a second control voltage (VIN2) of the control voltage (VCG) is applied to a right side of the first network device and a lower side of the second network device, and any one level of levels of the first control voltage (VIN1) and the second control voltage (VIN2) is a negative level, determining a level of the output voltage (VOUT) as a negative level when levels of the first control voltage (VIN1) and the second control voltage (VIN2) are both positive levels, and determining a level of the output voltage (VOUT) as a zero level when levels of the first control voltage (VIN1) and the second control voltage (VIN2) are both zero levels or one level is a zero level and the other level is a positive level is performed.
However, this limitation appears to be merely a statement of intent of the memory cell apparatus. It has been held that a recitation directed to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114.II also.
Regarding claims 6-10 and 12-15, these claim have substantially the same subject matter as that in claim 5. Therefore, claims 6-10 and 12-15 are rejected under the same rationale as claim 5 above.
Regarding claim 11, all the limitations of claim 1 are taught by Kim.
Kim further teaches the universal logic memory cell, wherein the drain region is in a p-doped state; the source region is in an n-doped state; the channel region is in an intrinsic state (Fig. 1a); and the channel region under the first and second programming gate electrodes operates as an n-channel corresponding to the first channel mode when a level of the program voltage (VPG) is a positive level (Fig. 3d) and operates as a p-channel corresponding to the second channel mode when a level of the program voltage (VPG) is a negative level (Fig. 3a).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEOKJIN KIM whose telephone number is (571)272-1487. The examiner can normally be reached M-F: 8:30am-5:00pm.
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/SEOKJIN KIM/Primary Examiner, Art Unit 2844